[U-Boot] [PATCH 3/3] mpc83xx: turn on icache in core initialization to improve u-boot boot time
before, MPC8349ITX boots u-boot in 4.3sec:
column1 is elapsed time since first message column2 is elapsed time since previous message column3 is the message 0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX 0.000 0.000: 0.000 0.000: Reset Status: 0.000 0.000: 0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz 0.032 0.000: Board: Freescale MPC8349E-mITX 0.032 0.000: UPMA: Configured for compact flash 0.032 0.000: I2C: ready 0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) 1.516 1.456: FLASH: 16 MB 2.641 1.125: PCI: Bus Dev VenId DevId Class Int 2.652 0.011: 00 10 1095 3114 0180 00 2.652 0.000: PCI: Bus Dev VenId DevId Class Int 2.652 0.000: In: serial 2.652 0.000: Out: serial 2.652 0.000: Err: serial 2.682 0.030: Board revision: 1.0 (PCF8475A) 3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic 3.080 0.000: TSEC0, TSEC1 4.300 1.219: IDE: Bus 0: .** Timeout **
after, MPC8349ITX boots u-boot in 3.0sec:
0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX 0.010 0.000: 0.010 0.000: Reset Status: 0.010 0.000: 0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz 0.017 0.000: Board: Freescale MPC8349E-mITX 0.038 0.020: UPMA: Configured for compact flash 0.038 0.000: I2C: ready 0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) 0.260 0.222: FLASH: 16 MB 1.390 1.130: PCI: Bus Dev VenId DevId Class Int 1.390 0.000: 00 10 1095 3114 0180 00 1.390 0.000: PCI: Bus Dev VenId DevId Class Int 1.400 0.010: In: serial 1.400 0.000: Out: serial 1.400 0.000: Err: serial 1.400 0.000: Board revision: 1.0 (PCF8475A) 1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic 1.832 0.000: TSEC0, TSEC1 3.038 1.205: IDE: Bus 0: .** Timeout **
also tested on these boards (albeit with a less accurate boottime measurement method):
seconds: before after 8349MDS ~2.6 ~2.2 8360MDS ~2.8 ~2.6 8313RDB ~2.5 ~2.3 #nand boot 837xRDB ~3.1 ~2.3
also tested on an 8323ERDB.
Signed-off-by: Kim Phillips kim.phillips@freescale.com --- please test!
include/configs/MPC8313ERDB.h | 3 ++- include/configs/MPC8315ERDB.h | 5 +++-- include/configs/MPC8323ERDB.h | 5 +++-- include/configs/MPC832XEMDS.h | 5 +++-- include/configs/MPC8349EMDS.h | 3 ++- include/configs/MPC8360EMDS.h | 5 +++-- include/configs/MPC8360ERDK.h | 5 +++-- include/configs/MPC837XEMDS.h | 5 +++-- include/configs/MPC837XERDB.h | 5 +++-- include/configs/MVBLM7.h | 3 ++- include/configs/SIMPC8313.h | 5 +++-- include/configs/TQM834x.h | 3 ++- include/configs/km83xx-common.h | 3 ++- include/configs/sbc8349.h | 3 ++- include/configs/vme8349.h | 3 ++- 15 files changed, 38 insertions(+), 23 deletions(-)
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index a2e4cd4..94695fc 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -517,7 +517,8 @@
#define CONFIG_SYS_HID0_INIT 0x000000000 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2 HID2_HBE
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index b106aa9..6972fe8 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -536,8 +536,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 HID2_HBE
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 50aea79..7c84393 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -438,8 +438,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f7632e0..7bd2793 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -455,8 +455,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 5c410c9..73dbea4 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -598,7 +598,8 @@ #define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE)
/* #define CONFIG_SYS_HID0_FINAL (\ HID0_ENABLE_INSTRUCTION_CACHE |\ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 620e32c..87a137b 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -495,8 +495,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index a43e465..e78cf60 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -412,8 +412,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 1565ff9..b30d0e3 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -544,8 +544,9 @@ extern int board_pci_host_broken(void); /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 97a05a2..1654f46 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -552,8 +552,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 6cc8d58..26897c6 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -321,7 +321,8 @@ #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT +#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ + HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE #define CONFIG_HIGH_BATS 1 diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 40e89d9..84af8df 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -411,8 +411,9 @@ | SICRL_ETSEC2_A )
#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT ) +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
#define CONFIG_SYS_HID2 HID2_HBE
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index f08c0a9..c1e0e64 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -405,7 +405,8 @@ extern int tqm834x_num_flash_banks;
/* i-cache and d-cache disabled */ #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT +#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */ diff --git a/include/configs/km83xx-common.h b/include/configs/km83xx-common.h index 71dfd25..a551b4d 100644 --- a/include/configs/km83xx-common.h +++ b/include/configs/km83xx-common.h @@ -255,7 +255,8 @@ * Core HID Setup */ #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 80f83ac..deaddde 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -542,7 +542,8 @@ #define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE)
/* #define CONFIG_SYS_HID0_FINAL (\ HID0_ENABLE_INSTRUCTION_CACHE |\ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index cb987a1..f493e75 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -449,7 +449,8 @@ #define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
On Fri, Apr 16, 2010 at 1:36 AM, Kim Phillips kim.phillips@freescale.com wrote:
before, MPC8349ITX boots u-boot in 4.3sec:
[snip]
after, MPC8349ITX boots u-boot in 3.0sec:
Thanks for the good news! Memory POST test on my board with icach disabled was lasting for hours until I enabled icach locally before and disabled it after time consuming tests.
BTW is there any reason that you enable icach in board specific rather than in common code?
-michael
On Fri, 16 Apr 2010 20:06:02 +0300 Michael Zaidman michael.zaidman@gmail.com wrote:
On Fri, Apr 16, 2010 at 1:36 AM, Kim Phillips kim.phillips@freescale.com wrote:
before, MPC8349ITX boots u-boot in 4.3sec:
[snip]
after, MPC8349ITX boots u-boot in 3.0sec:
Thanks for the good news! Memory POST test on my board with icach disabled was lasting for hours until I enabled icach locally before and disabled it after time consuming tests.
BTW is there any reason that you enable icach in board specific rather than in common code?
not really, was just following the existing HID0-setting paradigm - I presume the paradigm came about to allow different cpu/board combinations to enable/disable different HID bits. Does that not sound valid to you?
Kim
Kim Phillips wrote:
On Fri, 16 Apr 2010 20:06:02 +0300 Michael Zaidman michael.zaidman@gmail.com wrote:
On Fri, Apr 16, 2010 at 1:36 AM, Kim Phillips kim.phillips@freescale.com wrote:
before, MPC8349ITX boots u-boot in 4.3sec:
[snip]
after, MPC8349ITX boots u-boot in 3.0sec:
Thanks for the good news! Memory POST test on my board with icach disabled was lasting for hours until I enabled icach locally before and disabled it after time consuming tests.
BTW is there any reason that you enable icach in board specific rather than in common code?
not really, was just following the existing HID0-setting paradigm - I presume the paradigm came about to allow different cpu/board combinations to enable/disable different HID bits. Does that not sound valid to you?
Shouldn't you be using icache_enable(), or at least using HID0_INIT to do invalidation and lock clearing?
-Scott
On Mon, 19 Apr 2010 15:19:24 -0500 Scott Wood scottwood@freescale.com wrote:
Kim Phillips wrote:
On Fri, 16 Apr 2010 20:06:02 +0300 Michael Zaidman michael.zaidman@gmail.com wrote:
On Fri, Apr 16, 2010 at 1:36 AM, Kim Phillips kim.phillips@freescale.com wrote:
before, MPC8349ITX boots u-boot in 4.3sec:
[snip]
after, MPC8349ITX boots u-boot in 3.0sec:
Thanks for the good news! Memory POST test on my board with icach disabled was lasting for hours until I enabled icach locally before and disabled it after time consuming tests.
BTW is there any reason that you enable icach in board specific rather than in common code?
not really, was just following the existing HID0-setting paradigm - I presume the paradigm came about to allow different cpu/board combinations to enable/disable different HID bits. Does that not sound valid to you?
Shouldn't you be using icache_enable(), or at least using HID0_INIT to do invalidation and lock clearing?
the invalidation should occur whether or not the cache enable bit is set in HID0_INIT, and there is no locking being done prior to this point in the code. But I see your point; we should be using a more formal approach. I'll see what I can do - it's just that this patch preserved the existing code size, which could be important for e.g., future nand bootstrap development.
Kim
Kim Phillips wrote:
On Mon, 19 Apr 2010 15:19:24 -0500 Scott Wood scottwood@freescale.com wrote:
Shouldn't you be using icache_enable(), or at least using HID0_INIT to do invalidation and lock clearing?
the invalidation should occur whether or not the cache enable bit is set in HID0_INIT,
OK, was thinking of some other caches that don't automatically clear out the random junk on power-on -- but e300 manual says it does.
But I see your point; we should be using a more formal approach. I'll see what I can do - it's just that this patch preserved the existing code size, which could be important for e.g., future nand bootstrap development.
Right. It looks like we could shrink the NAND SPL some more by #ifndefing the cache functions in start.S.
-Scott
On Thu, Apr 15, 2010 at 5:36 PM, Kim Phillips kim.phillips@freescale.com wrote:
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
What was so special about the 8349ITX that icache() didn't work? You're changing the HDI0 values for all of the 83xx boards, but AFAIK, only the ITX had this problem.
Timur Tabi wrote:
On Thu, Apr 15, 2010 at 5:36 PM, Kim Phillips kim.phillips@freescale.com wrote:
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
HID0_ENABLE_INSTRUCTION_CACHE | \HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)What was so special about the 8349ITX that icache() didn't work? You're changing the HDI0 values for all of the 83xx boards, but AFAIK, only the ITX had this problem.
All 83xx boards had the performance problem of not enabling icache until after relocation.
-Scott
On Mon, Apr 19, 2010 at 3:41 PM, Scott Wood scottwood@freescale.com wrote:
What was so special about the 8349ITX that icache() didn't work? You're changing the HDI0 values for all of the 83xx boards, but AFAIK, only the ITX had this problem.
All 83xx boards had the performance problem of not enabling icache until after relocation.
That's not what I was asking. The ITX was different from other 83xx boards. It doesn't define CONFIG_MPC83xx (and with this patch, it still won't define it), so a lot of things weren't happening, including this:
#if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83xx) icache_enable (); /* it's time to enable the instruction cache */ #endif
Kim references the ITX in this patch, but I don't see how the problem I just described is fixed.
On Mon, 19 Apr 2010 16:05:11 -0500 Timur Tabi timur.tabi@gmail.com wrote:
On Mon, Apr 19, 2010 at 3:41 PM, Scott Wood scottwood@freescale.com wrote:
What was so special about the 8349ITX that icache() didn't work? You're changing the HDI0 values for all of the 83xx boards, but AFAIK, only the ITX had this problem.
All 83xx boards had the performance problem of not enabling icache until after relocation.
That's not what I was asking. The ITX was different from other 83xx boards. It doesn't define CONFIG_MPC83xx (and with this patch, it
why doesn't it, btw?
still won't define it), so a lot of things weren't happening, including this: #if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83xx) icache_enable (); /* it's time to enable the instruction cache */ #endif
Kim references the ITX in this patch, but I don't see how the problem I just described is fixed.
patch submission snafu; I'll send another version that includes the ITX.
Kim
On Mon, Apr 19, 2010 at 4:37 PM, Kim Phillips kim.phillips@freescale.com wrote:
That's not what I was asking. The ITX was different from other 83xx boards. It doesn't define CONFIG_MPC83xx (and with this patch, it
why doesn't it, btw?
It's been a while, but I believe the reason the ITX does not defined CONFIG_MPC83xx is specifically so that this code:
#if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83xx) icache_enable (); /* it's time to enable the instruction cache */ #endif
is *not* executed. That is, on the ITX, calling icache_enable() at that point causes U-Boot to hang or crash.
Therefore, I don't think any 83xx cache-related patch is complete until MPC8349ITX.h includes CONFIG_MPC83xx.
before, MPC8349ITX boots u-boot in 4.3sec:
column1 is elapsed time since first message column2 is elapsed time since previous message column3 is the message 0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX 0.000 0.000: 0.000 0.000: Reset Status: 0.000 0.000: 0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz 0.032 0.000: Board: Freescale MPC8349E-mITX 0.032 0.000: UPMA: Configured for compact flash 0.032 0.000: I2C: ready 0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) 1.516 1.456: FLASH: 16 MB 2.641 1.125: PCI: Bus Dev VenId DevId Class Int 2.652 0.011: 00 10 1095 3114 0180 00 2.652 0.000: PCI: Bus Dev VenId DevId Class Int 2.652 0.000: In: serial 2.652 0.000: Out: serial 2.652 0.000: Err: serial 2.682 0.030: Board revision: 1.0 (PCF8475A) 3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic 3.080 0.000: TSEC0, TSEC1 4.300 1.219: IDE: Bus 0: .** Timeout **
after, MPC8349ITX boots u-boot in 3.0sec:
0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX 0.010 0.000: 0.010 0.000: Reset Status: 0.010 0.000: 0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz 0.017 0.000: Board: Freescale MPC8349E-mITX 0.038 0.020: UPMA: Configured for compact flash 0.038 0.000: I2C: ready 0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) 0.260 0.222: FLASH: 16 MB 1.390 1.130: PCI: Bus Dev VenId DevId Class Int 1.390 0.000: 00 10 1095 3114 0180 00 1.390 0.000: PCI: Bus Dev VenId DevId Class Int 1.400 0.010: In: serial 1.400 0.000: Out: serial 1.400 0.000: Err: serial 1.400 0.000: Board revision: 1.0 (PCF8475A) 1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic 1.832 0.000: TSEC0, TSEC1 3.038 1.205: IDE: Bus 0: .** Timeout **
also tested on these boards (albeit with a less accurate boottime measurement method):
seconds: before after 8349MDS ~2.6 ~2.2 8360MDS ~2.8 ~2.6 8313RDB ~2.5 ~2.3 #nand boot 837xRDB ~3.1 ~2.3
also tested on an 8323ERDB.
v2: also remove the delayed icache enablement assumption in arch ppc's board.c, and add a CONFIG_MPC83xx define in the ITX config file for consistency (even though it was already being defined in 83xx' config.mk).
Signed-off-by: Kim Phillips kim.phillips@freescale.com --- arch/ppc/lib/board.c | 2 +- include/configs/MPC8313ERDB.h | 3 ++- include/configs/MPC8315ERDB.h | 5 +++-- include/configs/MPC8323ERDB.h | 5 +++-- include/configs/MPC832XEMDS.h | 5 +++-- include/configs/MPC8349EMDS.h | 3 ++- include/configs/MPC8349ITX.h | 5 +++-- include/configs/MPC8360EMDS.h | 5 +++-- include/configs/MPC8360ERDK.h | 5 +++-- include/configs/MPC837XEMDS.h | 5 +++-- include/configs/MPC837XERDB.h | 5 +++-- include/configs/MVBLM7.h | 3 ++- include/configs/SIMPC8313.h | 5 +++-- include/configs/TQM834x.h | 3 ++- include/configs/km83xx-common.h | 3 ++- include/configs/sbc8349.h | 3 ++- include/configs/vme8349.h | 3 ++- 17 files changed, 42 insertions(+), 26 deletions(-)
diff --git a/arch/ppc/lib/board.c b/arch/ppc/lib/board.c index a30acee..7b09fb5 100644 --- a/arch/ppc/lib/board.c +++ b/arch/ppc/lib/board.c @@ -686,7 +686,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
WATCHDOG_RESET();
-#if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83xx) +#if defined(CONFIG_SYS_DELAYED_ICACHE) icache_enable (); /* it's time to enable the instruction cache */ #endif
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index a2e4cd4..94695fc 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -517,7 +517,8 @@
#define CONFIG_SYS_HID0_INIT 0x000000000 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2 HID2_HBE
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index b106aa9..6972fe8 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -536,8 +536,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 HID2_HBE
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 50aea79..7c84393 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -438,8 +438,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f7632e0..7bd2793 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -455,8 +455,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 5c410c9..73dbea4 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -598,7 +598,8 @@ #define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE)
/* #define CONFIG_SYS_HID0_FINAL (\ HID0_ENABLE_INSTRUCTION_CACHE |\ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 09f9e38..9be571f 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -63,6 +63,7 @@ /* * High Level Configuration Options */ +#define CONFIG_MPC83xx 1 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ #define CONFIG_MPC8349 /* MPC8349 specific */
@@ -596,8 +597,8 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) /* USB DR as device + USB MPH as host */
-#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT +#define CONFIG_SYS_HID0_INIT 0x00000000 +#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
#define CONFIG_SYS_HID2 HID2_HBE #define CONFIG_HIGH_BATS 1 /* High BATs supported */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 620e32c..87a137b 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -495,8 +495,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index a43e465..e78cf60 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -412,8 +412,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 1565ff9..b30d0e3 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -544,8 +544,9 @@ extern int board_pci_host_broken(void); /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 97a05a2..1654f46 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -552,8 +552,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 6cc8d58..26897c6 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -321,7 +321,8 @@ #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT +#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ + HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE #define CONFIG_HIGH_BATS 1 diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 40e89d9..84af8df 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -411,8 +411,9 @@ | SICRL_ETSEC2_A )
#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT ) +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
#define CONFIG_SYS_HID2 HID2_HBE
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index f08c0a9..c1e0e64 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -405,7 +405,8 @@ extern int tqm834x_num_flash_banks;
/* i-cache and d-cache disabled */ #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT +#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */ diff --git a/include/configs/km83xx-common.h b/include/configs/km83xx-common.h index 71dfd25..a551b4d 100644 --- a/include/configs/km83xx-common.h +++ b/include/configs/km83xx-common.h @@ -255,7 +255,8 @@ * Core HID Setup */ #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
/* diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 80f83ac..deaddde 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -542,7 +542,8 @@ #define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE)
/* #define CONFIG_SYS_HID0_FINAL (\ HID0_ENABLE_INSTRUCTION_CACHE |\ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index cb987a1..f493e75 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -449,7 +449,8 @@ #define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
Hi Kim,
I recently rebased our platform from uboot 2009.11 to 2010.09 and tried out the ICACHE improvements you made in commit 1a2e203b31d33fb720f2cf1033b241ad36ab405a
It does not work on our platform (similar to MPC8360EMDS). I think this is specific to our platform because we need to initialize i2c and use i2c while still executing from flash in checkboard()) to read and parse a board-id i2c-eeprom to support a unified uboot binary for multiple board flavors.
I pasted checkboard code below; none of the underlying code uses malloc, just static buffer allocations.
Just an FYI mostly, I am okay with not having ICACHE for our board while in uboot. Just curious if you know of a reason from the limited explanation I've provided.
Also, as a general rule, does uboot accept hosting custom non-eval-platform boards? I'm tempted to mainline our code (mostly contained under /board/$company_name/...)
Thanks for your time
- Richard
/* ------------------- gd->board_type is identified here -------------------- */ int checkboard(void) { int rc = -EINVAL; int i = -1; int nbytes = 0; char pnbuf[512] = {0};
rc = -EINVAL; /* Initialize return code */
/* * Based on code from cm5200, called while u-boot is executing in flash, * thus things like malloc are not allowed. */
/* * We need I2C to access HW ID data from EEPROM, so we call i2c_init() * here despite the fact that it will be called again later on. We * also use a little trick to silence I2C-related output. */ gd->flags |= GD_FLG_SILENT; i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); gd->flags &= ~GD_FLG_SILENT;
/* Reset i2c controller(s) to clear any stuck-bus conditions */ i2c_bus_reset(CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); #if defined(CONFIG_SYS_I2C2_OFFSET) i2c_bus_reset(CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET); #endif /* CONFIG_SYS_I2C2_OFFSET */ /* Print a message to stay off the i2c bus for devices to settle */ puts("I2C: Reset\n");
rc = rc_id_board_from_esig(); /* fills in gd->board_type */ if (rc == 0) { printf("BOARD: %s [%08lX]\n", rc_get_string_from_board_type(gd->board_type), gd->board_type); } else {
/* BAD PARTNUMBER OR BAD I2C ACCESS, REBOOT */ printf("BOARD: FAILED IDENTIFICATION, error %d\n", rc); }
/* Always return 0, otherwise u-boot will halt and ask for reset */ return 0; }
Dear Richard Retanubun,
In message 4CBDC153.30008@RuggedCom.com you wrote:
It does not work on our platform (similar to MPC8360EMDS). I think this is specific to our platform because we need to initialize i2c and use i2c while still executing from flash in checkboard()) to read and parse a board-id i2c-eeprom to support a unified uboot binary for multiple board flavors.
Many boards do that. Some keep the environment in I2C EEPROM as well. This should not collide ith instruction caches on.
Just an FYI mostly, I am okay with not having ICACHE for our board while in uboot. Just curious if you know of a reason from the limited explanation I've provided.
Check how your boot device (NOR flash) is mapped - make sure it has the BI (burst inhibit) bit set (or whatever it may be called on that CPU).
Also, as a general rule, does uboot accept hosting custom non-eval-platform boards?
Yes, of course. We have tons of them.
I'm tempted to mainline our code (mostly contained under /board/$company_name/...)
That is highly recommended, as it will make it much easier for you to keep the code working during the product's lifetime.
Best regards,
Wolfgang Denk
On 10/20/10 15:50, Wolfgang Denk wrote:
Dear Richard Retanubun,
In message4CBDC153.30008@RuggedCom.com you wrote:
It does not work on our platform (similar to MPC8360EMDS). I think this is specific to our platform because we need to initialize i2c and use i2c while still executing from flash in checkboard()) to read and parse a board-id i2c-eeprom to support a unified uboot binary for multiple board flavors.
Many boards do that. Some keep the environment in I2C EEPROM as well. This should not collide With instruction caches on.
Just an FYI mostly, I am okay with not having ICACHE for our board while in uboot. Just curious if you know of a reason from the limited explanation I've provided.
Check how your boot device (NOR flash) is mapped - make sure it has the BI (burst inhibit) bit set (or whatever it may be called on that CPU).
Thanks for taking the time Wolfgang, now you got me curious, so I did a little reading. For MPC8360MDS reference board access the NOR flash in GPCM (General Purpose Control Machine) mode which does not have a "burst inhibit" bit, only the UPM mode of the local bus controller have this.
The only other place 'inhibit' is mentioned that would make sense is the Block Address Translation (BAT) my settings are identical to MPC8360MDS with one exception, MDS maps flash to BAT3 (considered low-BAT) mine is on BAT6 (considered high-BAT), and yes my HID1 register setting enables the high-BATs.
Not sure how any of these matters, though.
Another observation I've made is by turning on CONFIG_DISPLAY_AER_FULL or CONFIG_DISPLAY_AER_BRIEF and printing it from cpu_init.c:prt_83xx_rsr() causes the same checkboard() function to fail accessing the i2c-eeprom, even though the contents are correct. However, if I move the printf of:
printf("AEATR=0x%08lX, AEADR=0x%08lX\n", gd->arbiter_event_attributes, gd->arbiter_event_address); Into checkboard() (before i2c early init, all works okay)
So there seems to be a sensitivity in fsl-i2c drive while running from flash during early init although I am too ignorant to suspect anything right now.
Thanks for everyone's time...
- Richard
participants (6)
-
Kim Phillips -
Michael Zaidman -
Richard Retanubun -
Scott Wood -
Timur Tabi -
Wolfgang Denk