[U-Boot] [PATCH v7 01/19] nand: mxc: Prepare to add support for i.MX5
Add some abstraction to NFC definitions so that some parts of the current code can also be used for future i.MX5 code.
Clean up a few things by the way.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: - Fix typo in patch description.
Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: - Separate code reformatting from behavioral changes.
Changes in v2: - Fix warning for unused tmp variable in board_nand_init() for NFC V1.
drivers/mtd/nand/mxc_nand.c | 92 +++++++++++++++++++++--------------------- include/fsl_nfc.h | 72 ++++++++++++--------------------- nand_spl/nand_boot_fsl_nfc.c | 47 +++++++++++---------- 3 files changed, 97 insertions(+), 114 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index d0ded48..045df49 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -150,7 +150,7 @@ static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size
/* * This function polls the NANDFC to wait for the basic operation to - * complete by checking the INT bit of config2 register. + * complete by checking the INT bit. */ static void wait_op_done(struct mxc_nand_host *host, int max_retries, uint16_t param) @@ -158,10 +158,10 @@ static void wait_op_done(struct mxc_nand_host *host, int max_retries, uint32_t tmp;
while (max_retries-- > 0) { - if (readw(&host->regs->config2) & NFC_INT) { - tmp = readw(&host->regs->config2); - tmp &= ~NFC_INT; - writew(tmp, &host->regs->config2); + tmp = readnfc(&host->regs->config2); + if (tmp & NFC_V1_V2_CONFIG2_INT) { + tmp &= ~NFC_V1_V2_CONFIG2_INT; + writenfc(tmp, &host->regs->config2); break; } udelay(1); @@ -180,8 +180,8 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd) { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
- writew(cmd, &host->regs->flash_cmd); - writew(NFC_CMD, &host->regs->config2); + writenfc(cmd, &host->regs->flash_cmd); + writenfc(NFC_CMD, &host->regs->operation);
/* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, cmd); @@ -196,8 +196,8 @@ static void send_addr(struct mxc_nand_host *host, uint16_t addr) { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
- writew(addr, &host->regs->flash_addr); - writew(NFC_ADDR, &host->regs->config2); + writenfc(addr, &host->regs->flash_addr); + writenfc(NFC_ADDR, &host->regs->operation);
/* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, addr); @@ -229,19 +229,19 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, } }
- writew(buf_id, &host->regs->buf_addr); + writenfc(buf_id, &host->regs->buf_addr);
/* Configure spare or page+spare access */ if (!host->pagesize_2k) { - uint16_t config1 = readw(&host->regs->config1); + uint16_t config1 = readnfc(&host->regs->config1); if (spare_only) - config1 |= NFC_SP_EN; + config1 |= NFC_CONFIG1_SP_EN; else - config1 &= ~NFC_SP_EN; - writew(config1, &host->regs->config1); + config1 &= ~NFC_CONFIG1_SP_EN; + writenfc(config1, &host->regs->config1); }
- writew(NFC_INPUT, &host->regs->config2); + writenfc(NFC_INPUT, &host->regs->operation);
/* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only); @@ -256,19 +256,19 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
- writew(buf_id, &host->regs->buf_addr); + writenfc(buf_id, &host->regs->buf_addr);
/* Configure spare or page+spare access */ if (!host->pagesize_2k) { - uint32_t config1 = readw(&host->regs->config1); + uint32_t config1 = readnfc(&host->regs->config1); if (spare_only) - config1 |= NFC_SP_EN; + config1 |= NFC_CONFIG1_SP_EN; else - config1 &= ~NFC_SP_EN; - writew(config1, &host->regs->config1); + config1 &= ~NFC_CONFIG1_SP_EN; + writenfc(config1, &host->regs->config1); }
- writew(NFC_OUTPUT, &host->regs->config2); + writenfc(NFC_OUTPUT, &host->regs->operation);
/* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only); @@ -296,14 +296,14 @@ static void send_read_id(struct mxc_nand_host *host) uint16_t tmp;
/* NANDFC buffer 0 is used for device ID output */ - writew(0x0, &host->regs->buf_addr); + writenfc(0x0, &host->regs->buf_addr);
/* Read ID into main buffer */ - tmp = readw(&host->regs->config1); - tmp &= ~NFC_SP_EN; - writew(tmp, &host->regs->config1); + tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_CONFIG1_SP_EN; + writenfc(tmp, &host->regs->config1);
- writew(NFC_ID, &host->regs->config2); + writenfc(NFC_ID, &host->regs->operation);
/* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, 0); @@ -323,14 +323,14 @@ static uint16_t get_dev_status(struct mxc_nand_host *host) /* store the main area1 first word, later do recovery */ store = readl(main_buf); /* NANDFC buffer 1 is used for device status */ - writew(1, &host->regs->buf_addr); + writenfc(1, &host->regs->buf_addr);
/* Read status into main buffer */ - tmp = readw(&host->regs->config1); - tmp &= ~NFC_SP_EN; - writew(tmp, &host->regs->config1); + tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_CONFIG1_SP_EN; + writenfc(tmp, &host->regs->config1);
- writew(NFC_STATUS, &host->regs->config2); + writenfc(NFC_STATUS, &host->regs->operation);
/* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, 0); @@ -359,13 +359,13 @@ static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on) { struct nand_chip *nand_chip = mtd->priv; struct mxc_nand_host *host = nand_chip->priv; - uint16_t tmp = readw(&host->regs->config1); + uint16_t tmp = readnfc(&host->regs->config1);
if (on) - tmp |= NFC_ECC_EN; + tmp |= NFC_V1_V2_CONFIG1_ECC_EN; else - tmp &= ~NFC_ECC_EN; - writew(tmp, &host->regs->config1); + tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN; + writenfc(tmp, &host->regs->config1); }
#ifdef CONFIG_MXC_NAND_HWECC @@ -698,7 +698,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, * additional correction. 2-Bit errors cannot be corrected by * HW ECC, so we need to return failure */ - uint16_t ecc_status = readw(&host->regs->ecc_status_result); + uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { MTDDEBUG(MTD_DEBUG_LEVEL0, @@ -1241,24 +1241,24 @@ int board_nand_init(struct nand_chip *this) #endif
#ifdef MXC_NFC_V2_1 - tmp = readw(&host->regs->config1); - tmp |= NFC_ONE_CYCLE; - tmp |= NFC_4_8N_ECC; - writew(tmp, &host->regs->config1); + tmp = readnfc(&host->regs->config1); + tmp |= NFC_V2_CONFIG1_ONE_CYCLE; + tmp |= NFC_V2_CONFIG1_ECC_MODE_4; + writenfc(tmp, &host->regs->config1); if (host->pagesize_2k) - writew(64/2, &host->regs->spare_area_size); + writenfc(64/2, &host->regs->spare_area_size); else - writew(16/2, &host->regs->spare_area_size); + writenfc(16/2, &host->regs->spare_area_size); #endif
/* * preset operation * Unlock the internal RAM Buffer */ - writew(0x2, &host->regs->config); + writenfc(0x2, &host->regs->config);
/* Blocks to be unlocked */ - writew(0x0, &host->regs->unlockstart_blkaddr); + writenfc(0x0, &host->regs->unlockstart_blkaddr); /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the * unlockend_blkaddr, but the magic 0x4000 does not always work * when writing more than some 32 megabytes (on 2k page nands) @@ -1270,10 +1270,10 @@ int board_nand_init(struct nand_chip *this) * This might be NAND chip specific and the i.MX31 datasheet is * extremely vague about the semantics of this register. */ - writew(0xFFFF, &host->regs->unlockend_blkaddr); + writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
/* Unlock Block Command for given address range */ - writew(0x4, &host->regs->wrprot); + writenfc(0x4, &host->regs->wrprot);
return 0; } diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h index ff537b4..013e9e2 100644 --- a/include/fsl_nfc.h +++ b/include/fsl_nfc.h @@ -113,58 +113,38 @@ struct fsl_nfc_regs { #endif };
-/* - * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command - * operation - */ -#define NFC_CMD 0x1 +/* Set FCMD to 1, rest to 0 for Command operation */ +#define NFC_CMD 0x1
-/* - * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address - * operation - */ -#define NFC_ADDR 0x2 +/* Set FADD to 1, rest to 0 for Address operation */ +#define NFC_ADDR 0x2
-/* - * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input - * operation - */ -#define NFC_INPUT 0x4 +/* Set FDI to 1, rest to 0 for Input operation */ +#define NFC_INPUT 0x4
-/* - * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data - * Output operation - */ -#define NFC_OUTPUT 0x8 +/* Set FDO to 001, rest to 0 for Data Output operation */ +#define NFC_OUTPUT 0x8
-/* - * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID - * operation - */ -#define NFC_ID 0x10 +/* Set FDO to 010, rest to 0 for Read ID operation */ +#define NFC_ID 0x10
-/* - * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read - * Status operation - */ -#define NFC_STATUS 0x20 +/* Set FDO to 100, rest to 0 for Read Status operation */ +#define NFC_STATUS 0x20
-/* - * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status - * operation - */ -#define NFC_INT 0x8000 +#define NFC_CONFIG1_SP_EN (1 << 2) +#define NFC_CONFIG1_RST (1 << 6) +#define NFC_CONFIG1_CE (1 << 7) +#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) +#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) +#define NFC_V1_V2_CONFIG1_BIG (1 << 5) +#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) +#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) +#define NFC_V2_CONFIG1_FP_INT (1 << 11)
-#ifdef MXC_NFC_V2_1 -#define NFC_4_8N_ECC (1 << 0) -#endif -#define NFC_SP_EN (1 << 2) -#define NFC_ECC_EN (1 << 3) -#define NFC_INT_MSK (1 << 4) -#define NFC_BIG (1 << 5) -#define NFC_RST (1 << 6) -#define NFC_CE (1 << 7) -#define NFC_ONE_CYCLE (1 << 8) -#define NFC_FP_INT (1 << 11) +#define NFC_V1_V2_CONFIG2_INT (1 << 15) + +#define operation config2 +#define readnfc readw +#define writenfc writew
#endif /* __FSL_NFC_H */ diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c index a40c998..615e820 100644 --- a/nand_spl/nand_boot_fsl_nfc.c +++ b/nand_spl/nand_boot_fsl_nfc.c @@ -36,13 +36,13 @@ static void nfc_wait_ready(void) { uint32_t tmp;
- while (!(readw(&nfc->config2) & NFC_INT)) + while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT)) ;
/* Reset interrupt flag */ - tmp = readw(&nfc->config2); - tmp &= ~NFC_INT; - writew(tmp, &nfc->config2); + tmp = readnfc(&nfc->config2); + tmp &= ~NFC_V1_V2_CONFIG2_INT; + writenfc(tmp, &nfc->config2); }
static void nfc_nand_init(void) @@ -51,43 +51,45 @@ static void nfc_nand_init(void) int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; int config1;
- writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size); + writenfc(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
/* unlocking RAM Buff */ - writew(0x2, &nfc->config); + writenfc(0x2, &nfc->config);
/* hardware ECC checking and correct */ - config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK | - NFC_ONE_CYCLE | NFC_FP_INT; + config1 = readnfc(&nfc->config1) | NFC_V1_V2_CONFIG1_ECC_EN | + NFC_V1_V2_CONFIG1_INT_MSK | NFC_V2_CONFIG1_ONE_CYCLE | + NFC_V2_CONFIG1_FP_INT; /* * if spare size is larger that 16 bytes per 512 byte hunk * then use 8 symbol correction instead of 4 */ if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16) - config1 &= ~NFC_4_8N_ECC; + config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4; else - config1 |= NFC_4_8N_ECC; - writew(config1, &nfc->config1); + config1 |= NFC_V2_CONFIG1_ECC_MODE_4; + writenfc(config1, &nfc->config1); #elif defined(MXC_NFC_V1) /* unlocking RAM Buff */ - writew(0x2, &nfc->config); + writenfc(0x2, &nfc->config);
/* hardware ECC checking and correct */ - writew(NFC_ECC_EN | NFC_INT_MSK, &nfc->config1); + writenfc(NFC_V1_V2_CONFIG1_ECC_EN | NFC_V1_V2_CONFIG1_INT_MSK, + &nfc->config1); #endif }
static void nfc_nand_command(unsigned short command) { - writew(command, &nfc->flash_cmd); - writew(NFC_CMD, &nfc->config2); + writenfc(command, &nfc->flash_cmd); + writenfc(NFC_CMD, &nfc->operation); nfc_wait_ready(); }
static void nfc_nand_address(unsigned short address) { - writew(address, &nfc->flash_addr); - writew(NFC_ADDR, &nfc->config2); + writenfc(address, &nfc->flash_addr); + writenfc(NFC_ADDR, &nfc->operation); nfc_wait_ready(); }
@@ -121,8 +123,8 @@ static void nfc_nand_data_output(void) int i; #endif
- writew(0, &nfc->buf_addr); - writew(NFC_OUTPUT, &nfc->config2); + writenfc(0, &nfc->buf_addr); + writenfc(NFC_OUTPUT, &nfc->operation); nfc_wait_ready(); #ifdef NAND_MXC_2K_MULTI_CYCLE /* @@ -130,8 +132,8 @@ static void nfc_nand_data_output(void) * for pages larger than 512 bytes. */ for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) { - writew(i, &nfc->buf_addr); - writew(NFC_OUTPUT, &nfc->config2); + writenfc(i, &nfc->buf_addr); + writenfc(NFC_OUTPUT, &nfc->operation); nfc_wait_ready(); } #endif @@ -160,7 +162,8 @@ static int nfc_nand_check_ecc(void)
static void nfc_nand_read_page(unsigned int page_address) { - writew(0, &nfc->buf_addr); /* read in first 0 buffer */ + /* read in first 0 buffer */ + writenfc(0, &nfc->buf_addr); nfc_nand_command(NAND_CMD_READ0); nfc_nand_page_address(page_address);
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: - Separate code reformatting from behavioral changes.
Changes in v2: None
arch/arm/include/asm/arch-mx5/imx-regs.h | 9 +++ drivers/mtd/nand/mxc_nand.c | 129 +++++++++++++++++++++++++++--- include/fsl_nfc.h | 79 +++++++++++++++++- nand_spl/nand_boot_fsl_nfc.c | 67 +++++++++++++++- 4 files changed, 269 insertions(+), 15 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 249d15a..9aa0c6a 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -224,6 +224,15 @@ #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
/* + * SRC register definitions + */ +#if defined(CONFIG_MX51) +#define SRC_SBMR_NF16B (1 << 2) +#elif defined(CONFIG_MX53) +#define SRC_SBMR_NF16B (1 << 13) +#endif + +/* * CSPI register definitions */ #define MXC_ECSPI diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 045df49..cead757 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -22,7 +22,8 @@ #include <nand.h> #include <linux/err.h> #include <asm/io.h> -#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) +#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \ + defined(CONFIG_MX51) || defined(CONFIG_MX53) #include <asm/arch/imx-regs.h> #endif #include <fsl_nfc.h> @@ -36,6 +37,9 @@ struct mxc_nand_host { struct nand_chip *nand;
struct fsl_nfc_regs __iomem *regs; +#ifdef MXC_NFC_V3_2 + struct fsl_nfc_ip_regs __iomem *ip_regs; +#endif int spare_only; int status_request; int pagesize_2k; @@ -77,7 +81,7 @@ static struct nand_ecclayout nand_hw_eccoob2k = { .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} }, }; #endif -#elif defined(MXC_NFC_V2_1) +#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) #ifndef CONFIG_SYS_NAND_LARGEPAGE static struct nand_ecclayout nand_hw_eccoob = { .eccbytes = 9, @@ -130,6 +134,16 @@ static int is_16bit_nand(void) else return 0; } +#elif defined(CONFIG_MX51) || defined(CONFIG_MX53) +static int is_16bit_nand(void) +{ + struct src *src = (struct src *)SRC_BASE_ADDR; + + if (readl(&src->sbmr) & SRC_SBMR_NF16B) + return 1; + else + return 0; +} #else #warning "8/16 bit NAND autodetection not supported" static int is_16bit_nand(void) @@ -158,10 +172,17 @@ static void wait_op_done(struct mxc_nand_host *host, int max_retries, uint32_t tmp;
while (max_retries-- > 0) { +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) tmp = readnfc(&host->regs->config2); if (tmp & NFC_V1_V2_CONFIG2_INT) { tmp &= ~NFC_V1_V2_CONFIG2_INT; writenfc(tmp, &host->regs->config2); +#elif defined(MXC_NFC_V3_2) + tmp = readnfc(&host->ip_regs->ipc); + if (tmp & NFC_V3_IPC_INT) { + tmp &= ~NFC_V3_IPC_INT; + writenfc(tmp, &host->ip_regs->ipc); +#endif break; } udelay(1); @@ -213,7 +234,7 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, if (spare_only) MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
- if (is_mxc_nfc_21()) { + if (is_mxc_nfc_21() || is_mxc_nfc_32()) { int i; /* * The controller copies the 64 bytes of spare data from @@ -229,11 +250,18 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, } }
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) writenfc(buf_id, &host->regs->buf_addr); +#elif defined(MXC_NFC_V3_2) + uint32_t tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_V3_CONFIG1_RBA_MASK; + tmp |= NFC_V3_CONFIG1_RBA(buf_id); + writenfc(tmp, &host->regs->config1); +#endif
/* Configure spare or page+spare access */ if (!host->pagesize_2k) { - uint16_t config1 = readnfc(&host->regs->config1); + uint32_t config1 = readnfc(&host->regs->config1); if (spare_only) config1 |= NFC_CONFIG1_SP_EN; else @@ -256,7 +284,14 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) writenfc(buf_id, &host->regs->buf_addr); +#elif defined(MXC_NFC_V3_2) + uint32_t tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_V3_CONFIG1_RBA_MASK; + tmp |= NFC_V3_CONFIG1_RBA(buf_id); + writenfc(tmp, &host->regs->config1); +#endif
/* Configure spare or page+spare access */ if (!host->pagesize_2k) { @@ -273,7 +308,7 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only);
- if (is_mxc_nfc_21()) { + if (is_mxc_nfc_21() || is_mxc_nfc_32()) { int i;
/* @@ -293,10 +328,16 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, /* Request the NANDFC to perform a read of the NAND device ID. */ static void send_read_id(struct mxc_nand_host *host) { - uint16_t tmp; + uint32_t tmp;
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) /* NANDFC buffer 0 is used for device ID output */ writenfc(0x0, &host->regs->buf_addr); +#elif defined(MXC_NFC_V3_2) + tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_V3_CONFIG1_RBA_MASK; + writenfc(tmp, &host->regs->config1); +#endif
/* Read ID into main buffer */ tmp = readnfc(&host->regs->config1); @@ -315,15 +356,19 @@ static void send_read_id(struct mxc_nand_host *host) */ static uint16_t get_dev_status(struct mxc_nand_host *host) { +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) void __iomem *main_buf = host->regs->main_area[1]; uint32_t store; - uint16_t ret, tmp; +#endif + uint32_t ret, tmp; /* Issue status request to NAND device */
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) /* store the main area1 first word, later do recovery */ store = readl(main_buf); /* NANDFC buffer 1 is used for device status */ writenfc(1, &host->regs->buf_addr); +#endif
/* Read status into main buffer */ tmp = readnfc(&host->regs->config1); @@ -335,12 +380,16 @@ static uint16_t get_dev_status(struct mxc_nand_host *host) /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, 0);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) /* * Status is placed in first word of main buffer * get status, then recovery area 1 data */ ret = readw(main_buf); writel(store, main_buf); +#elif defined(MXC_NFC_V3_2) + ret = readnfc(&host->regs->config1) >> 16; +#endif
return ret; } @@ -359,6 +408,7 @@ static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on) { struct nand_chip *nand_chip = mtd->priv; struct mxc_nand_host *host = nand_chip->priv; +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) uint16_t tmp = readnfc(&host->regs->config1);
if (on) @@ -366,6 +416,15 @@ static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on) else tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN; writenfc(tmp, &host->regs->config1); +#elif defined(MXC_NFC_V3_2) + uint32_t tmp = readnfc(&host->ip_regs->config2); + + if (on) + tmp |= NFC_V3_CONFIG2_ECC_EN; + else + tmp &= ~NFC_V3_CONFIG2_ECC_EN; + writenfc(tmp, &host->ip_regs->config2); +#endif }
#ifdef CONFIG_MXC_NAND_HWECC @@ -377,7 +436,7 @@ static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) */ }
-#ifdef MXC_NFC_V2_1 +#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, int page, int sndcmd) @@ -1167,8 +1226,8 @@ static struct nand_bbt_descr bbt_mirror_descr = { int board_nand_init(struct nand_chip *this) { struct mtd_info *mtd; -#ifdef MXC_NFC_V2_1 - uint16_t tmp; +#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) + uint32_t tmp; #endif
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT @@ -1196,13 +1255,17 @@ int board_nand_init(struct nand_chip *this) this->verify_buf = mxc_nand_verify_buf;
host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; +#ifdef MXC_NFC_V3_2 + host->ip_regs = + (struct fsl_nfc_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE; +#endif host->clk_act = 1;
#ifdef CONFIG_MXC_NAND_HWECC this->ecc.calculate = mxc_nand_calculate_ecc; this->ecc.hwctl = mxc_nand_enable_hwecc; this->ecc.correct = mxc_nand_correct_data; - if (is_mxc_nfc_21()) { + if (is_mxc_nfc_21() || is_mxc_nfc_32()) { this->ecc.mode = NAND_ECC_HW_SYNDROME; this->ecc.read_page = mxc_nand_read_page_syndrome; this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome; @@ -1240,6 +1303,7 @@ int board_nand_init(struct nand_chip *this) this->ecc.layout = &nand_hw_eccoob; #endif
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) #ifdef MXC_NFC_V2_1 tmp = readnfc(&host->regs->config1); tmp |= NFC_V2_CONFIG1_ONE_CYCLE; @@ -1274,6 +1338,49 @@ int board_nand_init(struct nand_chip *this)
/* Unlock Block Command for given address range */ writenfc(0x4, &host->regs->wrprot); +#elif defined(MXC_NFC_V3_2) + writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1); + writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc); + + /* Unlock the internal RAM Buffer */ + writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, + &host->ip_regs->wrprot); + + /* Blocks to be unlocked */ + for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++) + writenfc(0x0 | 0xFFFF << 16, + &host->ip_regs->wrprot_unlock_blkaddr[tmp]); + + writenfc(0, &host->ip_regs->ipc); + + tmp = readnfc(&host->ip_regs->config2); + tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK | + NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK); + tmp |= NFC_V3_CONFIG2_ONE_CYCLE; + + if (host->pagesize_2k) { + tmp |= NFC_V3_CONFIG2_SPAS(64/2); + tmp |= NFC_V3_CONFIG2_PS_2048; + } else { + tmp |= NFC_V3_CONFIG2_SPAS(16/2); + tmp |= NFC_V3_CONFIG2_PS_512; + } + + writenfc(tmp, &host->ip_regs->config2); + + tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) | + NFC_V3_CONFIG3_NO_SDMA | + NFC_V3_CONFIG3_RBB_MODE | + NFC_V3_CONFIG3_SBB(6) | /* Reset default */ + NFC_V3_CONFIG3_ADD_OP(0); + + if (!(this->options & NAND_BUSWIDTH_16)) + tmp |= NFC_V3_CONFIG3_FW8; + + writenfc(tmp, &host->ip_regs->config3); + + writenfc(0, &host->ip_regs->delay_line); +#endif
return 0; } diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h index 013e9e2..48a6448 100644 --- a/include/fsl_nfc.h +++ b/include/fsl_nfc.h @@ -33,7 +33,8 @@ * to support up to 2K byte pagesize nand. * Reading or writing a 2K page requires 4 FDI/FDO cycles. * - * MX25 and MX35 have version 2.1, which has: + * MX25 and MX35 have version 2.1, and MX51 and MX53 have version 3.2, which + * have: * 8 512-byte main buffers and * 8 64-byte spare buffers * to support up to 4K byte pagesize nand. @@ -44,20 +45,29 @@ #define MXC_NFC_V1 #define is_mxc_nfc_1() 1 #define is_mxc_nfc_21() 0 +#define is_mxc_nfc_32() 0 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35) #define MXC_NFC_V2_1 #define is_mxc_nfc_1() 0 #define is_mxc_nfc_21() 1 +#define is_mxc_nfc_32() 0 +#elif defined(CONFIG_MX51) || defined(CONFIG_MX53) +#define MXC_NFC_V3 +#define MXC_NFC_V3_2 +#define is_mxc_nfc_1() 0 +#define is_mxc_nfc_21() 0 +#define is_mxc_nfc_32() 1 #else #error "MXC NFC implementation not supported" #endif +#define is_mxc_nfc_3() is_mxc_nfc_32()
#if defined(MXC_NFC_V1) #define NAND_MXC_NR_BUFS 4 #define NAND_MXC_SPARE_BUF_SIZE 16 #define NAND_MXC_REG_OFFSET 0xe00 #define NAND_MXC_2K_MULTI_CYCLE -#elif defined(MXC_NFC_V2_1) +#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) #define NAND_MXC_NR_BUFS 8 #define NAND_MXC_SPARE_BUF_SIZE 64 #define NAND_MXC_REG_OFFSET 0x1e00 @@ -110,9 +120,28 @@ struct fsl_nfc_regs { u16 unlockend_blkaddr2; u16 unlockstart_blkaddr3; u16 unlockend_blkaddr3; +#elif defined(MXC_NFC_V3_2) + u32 flash_cmd; + u32 flash_addr[12]; + u32 config1; + u32 ecc_status_result; + u32 status_sum; + u32 launch; #endif };
+#ifdef MXC_NFC_V3_2 +struct fsl_nfc_ip_regs { + u32 wrprot; + u32 wrprot_unlock_blkaddr[8]; + u32 config2; + u32 config3; + u32 ipc; + u32 err_addr; + u32 delay_line; +}; +#endif + /* Set FCMD to 1, rest to 0 for Command operation */ #define NFC_CMD 0x1
@@ -131,20 +160,66 @@ struct fsl_nfc_regs { /* Set FDO to 100, rest to 0 for Read Status operation */ #define NFC_STATUS 0x20
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) #define NFC_CONFIG1_SP_EN (1 << 2) #define NFC_CONFIG1_RST (1 << 6) #define NFC_CONFIG1_CE (1 << 7) +#elif defined(MXC_NFC_V3_2) +#define NFC_CONFIG1_SP_EN (1 << 0) +#define NFC_CONFIG1_CE (1 << 1) +#define NFC_CONFIG1_RST (1 << 2) +#endif #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) #define NFC_V1_V2_CONFIG1_BIG (1 << 5) #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) #define NFC_V2_CONFIG1_FP_INT (1 << 11) +#define NFC_V3_CONFIG1_RBA_MASK (0x7 << 4) +#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7) << 4)
#define NFC_V1_V2_CONFIG2_INT (1 << 15) +#define NFC_V3_CONFIG2_PS_MASK (0x3 << 0) +#define NFC_V3_CONFIG2_PS_512 (0 << 0) +#define NFC_V3_CONFIG2_PS_2048 (1 << 0) +#define NFC_V3_CONFIG2_PS_4096 (2 << 0) +#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) +#define NFC_V3_CONFIG2_ECC_EN (1 << 3) +#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) +#define NFC_V3_CONFIG2_NUM_ADDR_PH0 (1 << 5) +#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) +#define NFC_V3_CONFIG2_PPB_MASK (0x3 << 7) +#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7) +#define NFC_V3_CONFIG2_EDC_MASK (0x7 << 9) +#define NFC_V3_CONFIG2_EDC(x) (((x) & 0x7) << 9) +#define NFC_V3_CONFIG2_NUM_ADDR_PH1(x) (((x) & 0x3) << 12) +#define NFC_V3_CONFIG2_INT_MSK (1 << 15) +#define NFC_V3_CONFIG2_SPAS_MASK (0xff << 16) +#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) +#define NFC_V3_CONFIG2_ST_CMD_MASK (0xff << 24) +#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) + +#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) +#define NFC_V3_CONFIG3_FW8 (1 << 3) +#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) +#define NFC_V3_CONFIG3_NUM_OF_DEVS(x) (((x) & 0x7) << 12) +#define NFC_V3_CONFIG3_RBB_MODE (1 << 15) +#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
+#define NFC_V3_WRPROT_UNLOCK (1 << 2) +#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) + +#define NFC_V3_IPC_CREQ (1 << 0) +#define NFC_V3_IPC_INT (1 << 31) + +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) #define operation config2 #define readnfc readw #define writenfc writew +#elif defined(MXC_NFC_V3_2) +#define operation launch +#define readnfc readl +#define writenfc writel +#endif
#endif /* __FSL_NFC_H */ diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c index 615e820..1096727 100644 --- a/nand_spl/nand_boot_fsl_nfc.c +++ b/nand_spl/nand_boot_fsl_nfc.c @@ -30,12 +30,18 @@ #include <asm/io.h> #include <fsl_nfc.h>
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR; +#elif defined(MXC_NFC_V3_2) +static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR_AXI; +static struct fsl_nfc_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR; +#endif
static void nfc_wait_ready(void) { uint32_t tmp;
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT)) ;
@@ -43,11 +49,56 @@ static void nfc_wait_ready(void) tmp = readnfc(&nfc->config2); tmp &= ~NFC_V1_V2_CONFIG2_INT; writenfc(tmp, &nfc->config2); +#elif defined(MXC_NFC_V3_2) + while (!(readnfc(&nfc_ip->ipc) & NFC_V3_IPC_INT)) + ; + + /* Reset interrupt flag */ + tmp = readnfc(&nfc_ip->ipc); + tmp &= ~NFC_V3_IPC_INT; + writenfc(tmp, &nfc_ip->ipc); +#endif }
static void nfc_nand_init(void) { -#if defined(MXC_NFC_V2_1) +#if defined(MXC_NFC_V3_2) + int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; + int tmp; + + tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK | + NFC_V3_CONFIG2_EDC_MASK | NFC_V3_CONFIG2_PS_MASK)) | + NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_SPARE_SIZE / 2) | + NFC_V3_CONFIG2_INT_MSK | NFC_V3_CONFIG2_ECC_EN | + NFC_V3_CONFIG2_ONE_CYCLE; + if (CONFIG_SYS_NAND_PAGE_SIZE == 4096) + tmp |= NFC_V3_CONFIG2_PS_4096; + else if (CONFIG_SYS_NAND_PAGE_SIZE == 2048) + tmp |= NFC_V3_CONFIG2_PS_2048; + else if (CONFIG_SYS_NAND_PAGE_SIZE == 512) + tmp |= NFC_V3_CONFIG2_PS_512; + /* + * if spare size is larger that 16 bytes per 512 byte hunk + * then use 8 symbol correction instead of 4 + */ + if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16) + tmp |= NFC_V3_CONFIG2_ECC_MODE_8; + else + tmp &= ~NFC_V3_CONFIG2_ECC_MODE_8; + writenfc(tmp, &nfc_ip->config2); + + tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) | + NFC_V3_CONFIG3_NO_SDMA | + NFC_V3_CONFIG3_RBB_MODE | + NFC_V3_CONFIG3_SBB(6) | /* Reset default */ + NFC_V3_CONFIG3_ADD_OP(0); +#ifndef CONFIG_SYS_NAND_BUSWIDTH_16 + tmp |= NFC_V3_CONFIG3_FW8; +#endif + writenfc(tmp, &nfc_ip->config3); + + writenfc(0, &nfc_ip->delay_line); +#elif defined(MXC_NFC_V2_1) int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; int config1;
@@ -123,7 +174,13 @@ static void nfc_nand_data_output(void) int i; #endif
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) writenfc(0, &nfc->buf_addr); +#elif defined(MXC_NFC_V3_2) + int config1 = readnfc(&nfc->config1); + config1 &= ~NFC_V3_CONFIG1_RBA_MASK; + writenfc(config1, &nfc->config1); +#endif writenfc(NFC_OUTPUT, &nfc->operation); nfc_wait_ready(); #ifdef NAND_MXC_2K_MULTI_CYCLE @@ -144,7 +201,7 @@ static int nfc_nand_check_ecc(void) #if defined(MXC_NFC_V1) u16 ecc_status = readw(&nfc->ecc_status_result); return (ecc_status & 0x3) == 2 || (ecc_status >> 2) == 2; -#elif defined(MXC_NFC_V2_1) +#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) u32 ecc_status = readl(&nfc->ecc_status_result); int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; int err_limit = CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16 ? 8 : 4; @@ -163,7 +220,13 @@ static int nfc_nand_check_ecc(void) static void nfc_nand_read_page(unsigned int page_address) { /* read in first 0 buffer */ +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) writenfc(0, &nfc->buf_addr); +#elif defined(MXC_NFC_V3_2) + int config1 = readnfc(&nfc->config1); + config1 &= ~NFC_V3_CONFIG1_RBA_MASK; + writenfc(config1, &nfc->config1); +#endif nfc_nand_command(NAND_CMD_READ0); nfc_nand_page_address(page_address);
Benoit,
On Fri, Feb 15, 2013 at 6:54 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
+#elif defined(CONFIG_MX51) || defined(CONFIG_MX53) +static int is_16bit_nand(void) +{
struct src *src = (struct src *)SRC_BASE_ADDR;if (readl(&src->sbmr) & SRC_SBMR_NF16B)return 1;elsereturn 0;
This logic is not working on my tests with mx53ard and it results in:
NAND: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd5 (Samsung NAND 2GiB 3,3) NAND bus width 16 instead 8 bit No NAND device found!!! 0 MiB
I am using NAND, but not booting from it, so I don't think we should use SBMR register to decide the NAND bus width.
If we are not booting from NAND, shouldn't we use a CONFIG_ option in mx53ard.h to tell the NAND bus width?
Regards,
Fabio Estevam
Hi Fabio,
On Tuesday, February 26, 2013 4:33:20 PM, Fabio Estevam wrote:
Benoit,
On Fri, Feb 15, 2013 at 6:54 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
+#elif defined(CONFIG_MX51) || defined(CONFIG_MX53) +static int is_16bit_nand(void) +{
struct src *src = (struct src *)SRC_BASE_ADDR;if (readl(&src->sbmr) & SRC_SBMR_NF16B)return 1;elsereturn 0;This logic is not working on my tests with mx53ard and it results in:
NAND: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd5 (Samsung NAND 2GiB 3,3) NAND bus width 16 instead 8 bit No NAND device found!!! 0 MiB
I am using NAND, but not booting from it, so I don't think we should use SBMR register to decide the NAND bus width.
If we are not booting from NAND, shouldn't we use a CONFIG_ option in mx53ard.h to tell the NAND bus width?
This boot pin / fuse config has been used by this driver for all i.MX platforms from the beginning. I don't think that we really need one more software config here. This is hardware stuff, and the i.MX provides a dedicated hardware configuration for it, so I think that we should use it, even if it's made for NAND boot, since it's just describing the present hardware, just like DT would.
In the particular case of the mx53ard, there is a DIP switch that you can use to fix this config to 8-bit NAND Flash. But if you have blown the fuses to override the boot pin config, then of course we're doomed because a wrong NAND Flash config has been blow.
Best regards, Benoît
On Tue, Feb 26, 2013 at 1:08 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
This boot pin / fuse config has been used by this driver for all i.MX platforms from the beginning. I don't think that we really need one more software config here. This is hardware stuff, and the i.MX provides a dedicated hardware configuration for it, so I think that we should use it, even if it's made for NAND boot, since it's just describing the present hardware, just like DT would.
In the particular case of the mx53ard, there is a DIP switch that you can use to fix this config to 8-bit NAND Flash. But if you have blown the fuses to override the boot pin config, then of course we're doomed because a wrong NAND Flash config has been blow.
The boot config jumpers are correctly set to boot from MMC card and this is what I am using as the boot media.
Why should we decide the NAND width via boot pins if I am not booting from NAND at all?
I see that current mxc nand drivers are doing like this, but I don't think this makes sense if we use NAND and does not boot from it.
I agree with this comment from tt01.h:
"/* * it's not 16 bit: * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT * the current u-boot mxc_nand.c tries to auto-detect, but this only * reads the boot settings during reset (which might be wrong) */"
and we can also see the a workaround at board/davedenx/qong/qong.c in order to tell the nand bus width is 8 bits:
void qong_nand_plat_init(void *chip) { struct nand_chip *nand = (struct nand_chip *)chip; nand->chip_delay = 20; nand->select_chip = qong_nand_select_chip; nand->options &= ~NAND_BUSWIDTH_16; board_nand_setup(); }
Hi Fabio,
On Tuesday, February 26, 2013 5:35:28 PM, Fabio Estevam wrote:
On Tue, Feb 26, 2013 at 1:08 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
This boot pin / fuse config has been used by this driver for all i.MX platforms from the beginning. I don't think that we really need one more software config here. This is hardware stuff, and the i.MX provides a dedicated hardware configuration for it, so I think that we should use it, even if it's made for NAND boot, since it's just describing the present hardware, just like DT would.
In the particular case of the mx53ard, there is a DIP switch that you can use to fix this config to 8-bit NAND Flash. But if you have blown the fuses to override the boot pin config, then of course we're doomed because a wrong NAND Flash config has been blow.
The boot config jumpers are correctly set to boot from MMC card and this is what I am using as the boot media.
OK, then we don't have a choice.
Why should we decide the NAND width via boot pins if I am not booting from NAND at all?
I see that current mxc nand drivers are doing like this, but I don't think this makes sense if we use NAND and does not boot from it.
If the NAND boot config for bus width is not used by the actuel boot config to mean something else (which is not your case), then it's a handy way of describing the NAND hardware setup without involving software. But anyway we're not in this case, so we need a software config.
I agree with this comment from tt01.h:
"/*
- it's not 16 bit:
- #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
- the current u-boot mxc_nand.c tries to auto-detect, but this only
- reads the boot settings during reset (which might be wrong)
*/"
and we can also see the a workaround at board/davedenx/qong/qong.c in order to tell the nand bus width is 8 bits:
void qong_nand_plat_init(void *chip) { struct nand_chip *nand = (struct nand_chip *)chip; nand->chip_delay = 20; nand->select_chip = qong_nand_select_chip; nand->options &= ~NAND_BUSWIDTH_16; board_nand_setup(); }
OK, then let's use something like CONFIG_SYS_NAND_BUSWIDTH_16BIT for all boards with mxc_nand enabled.
Best regards, Benoît
On Tue, Feb 26, 2013 at 1:49 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Hi Fabio,
On Tuesday, February 26, 2013 5:35:28 PM, Fabio Estevam wrote:
On Tue, Feb 26, 2013 at 1:08 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
This boot pin / fuse config has been used by this driver for all i.MX platforms from the beginning. I don't think that we really need one more software config here. This is hardware stuff, and the i.MX provides a dedicated hardware configuration for it, so I think that we should use it, even if it's made for NAND boot, since it's just describing the present hardware, just like DT would.
In the particular case of the mx53ard, there is a DIP switch that you can use to fix this config to 8-bit NAND Flash. But if you have blown the fuses to override the boot pin config, then of course we're doomed because a wrong NAND Flash config has been blow.
The boot config jumpers are correctly set to boot from MMC card and this is what I am using as the boot media.
OK, then we don't have a choice.
Why should we decide the NAND width via boot pins if I am not booting from NAND at all?
I see that current mxc nand drivers are doing like this, but I don't think this makes sense if we use NAND and does not boot from it.
If the NAND boot config for bus width is not used by the actuel boot config to mean something else (which is not your case), then it's a handy way of describing the NAND hardware setup without involving software. But anyway we're not in this case, so we need a software config.
I agree with this comment from tt01.h:
"/*
- it's not 16 bit:
- #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
- the current u-boot mxc_nand.c tries to auto-detect, but this only
- reads the boot settings during reset (which might be wrong)
*/"
and we can also see the a workaround at board/davedenx/qong/qong.c in order to tell the nand bus width is 8 bits:
void qong_nand_plat_init(void *chip) { struct nand_chip *nand = (struct nand_chip *)chip; nand->chip_delay = 20; nand->select_chip = qong_nand_select_chip; nand->options &= ~NAND_BUSWIDTH_16; board_nand_setup(); }
OK, then let's use something like CONFIG_SYS_NAND_BUSWIDTH_16BIT for all boards with mxc_nand enabled.
Documentation/devicetree/bindings/mtd/nand.txt says:
nand-bus-width : 8 or 16 bus width if not present 8
I think we could do the same here, ie, if CONFIG_SYS_NAND_BUSWIDTH_16BIT is not defined in the board file, then assume it is 8-bit nand.
I can send this as a separate patch.
Thanks,
Fabio Estevam
Hi Fabio,
On Tuesday, February 26, 2013 6:03:56 PM, Fabio Estevam wrote:
On Tue, Feb 26, 2013 at 1:49 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Hi Fabio,
On Tuesday, February 26, 2013 5:35:28 PM, Fabio Estevam wrote:
On Tue, Feb 26, 2013 at 1:08 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
This boot pin / fuse config has been used by this driver for all i.MX platforms from the beginning. I don't think that we really need one more software config here. This is hardware stuff, and the i.MX provides a dedicated hardware configuration for it, so I think that we should use it, even if it's made for NAND boot, since it's just describing the present hardware, just like DT would.
In the particular case of the mx53ard, there is a DIP switch that you can use to fix this config to 8-bit NAND Flash. But if you have blown the fuses to override the boot pin config, then of course we're doomed because a wrong NAND Flash config has been blow.
The boot config jumpers are correctly set to boot from MMC card and this is what I am using as the boot media.
OK, then we don't have a choice.
Why should we decide the NAND width via boot pins if I am not booting from NAND at all?
I see that current mxc nand drivers are doing like this, but I don't think this makes sense if we use NAND and does not boot from it.
If the NAND boot config for bus width is not used by the actuel boot config to mean something else (which is not your case), then it's a handy way of describing the NAND hardware setup without involving software. But anyway we're not in this case, so we need a software config.
I agree with this comment from tt01.h:
"/*
- it's not 16 bit:
- #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
- the current u-boot mxc_nand.c tries to auto-detect, but this only
- reads the boot settings during reset (which might be wrong)
*/"
and we can also see the a workaround at board/davedenx/qong/qong.c in order to tell the nand bus width is 8 bits:
void qong_nand_plat_init(void *chip) { struct nand_chip *nand = (struct nand_chip *)chip; nand->chip_delay = 20; nand->select_chip = qong_nand_select_chip; nand->options &= ~NAND_BUSWIDTH_16; board_nand_setup(); }
OK, then let's use something like CONFIG_SYS_NAND_BUSWIDTH_16BIT for all boards with mxc_nand enabled.
Documentation/devicetree/bindings/mtd/nand.txt says:
nand-bus-width : 8 or 16 bus width if not present 8
I think we could do the same here, ie, if CONFIG_SYS_NAND_BUSWIDTH_16BIT is not defined in the board file, then assume it is 8-bit nand.
I 100% agree. This should make your patch quite lite.
I can send this as a separate patch.
OK, thanks.
Best regards, Benoît
Don't use several instructions to build constant values.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Acked-by: Stefano Babic sbabic@denx.de --- Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: - New patch.
Changes in v2: None
arch/arm/cpu/armv7/mx5/lowlevel_init.S | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 6d9396a..dfce0ca 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -309,8 +309,7 @@ setup_pll_func: ldr r0, =CCM_BASE_ADDR ldr r1, =0x00015154 str r1, [r0, #CLKCTL_CBCMR] - ldr r1, =0x02888945 - orr r1, r1, #(1 << 16) + ldr r1, =0x02898945 str r1, [r0, #CLKCTL_CBCDR] /* make sure change is effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] @@ -321,10 +320,7 @@ setup_pll_func:
/* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR - ldr r1, =0x00808145 - orr r1, r1, #(2 << 10) - orr r1, r1, #(0 << 16) - orr r1, r1, #(1 << 19) + ldr r1, =0x00888945 str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x00016154
Add support for the Samsung K9LAG08U0M NAND Flash (2-GiB MLC NAND Flash, 2-kiB pages, 256-kiB blocks, 30-ns R/W cycles, 1 CS) on mx53ard.
eNFC_CLK_ROOT is set up with a cycle time of 37.5 ns (400 MHz / 3 / 5) for this board, which satisfies the 30-ns NF R/W cycle requirement.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: - New patch.
Changes in v2: None
board/freescale/mx53ard/mx53ard.c | 18 ++++++++++++++++++ include/configs/mx53ard.h | 10 ++++++++++ 2 files changed, 28 insertions(+)
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index 2fc8570..8907388 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -58,6 +58,23 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; }
+#ifdef CONFIG_NAND_MXC +static void setup_iomux_nand(void) +{ + mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0); +} +#else +static void setup_iomux_nand(void) +{ +} +#endif + static void setup_iomux_uart(void) { /* UART1 RXD */ @@ -277,6 +294,7 @@ static void weim_cs1_settings(void)
int board_early_init_f(void) { + setup_iomux_nand(); setup_iomux_uart(); return 0; } diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 62cb42b..148f7a2 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -41,6 +41,16 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MXC_GPIO
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI +#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_CMD_NAND + #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE
Hi Benoit,
On Fri, Feb 15, 2013 at 6:54 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Add support for the Samsung K9LAG08U0M NAND Flash (2-GiB MLC NAND Flash, 2-kiB pages, 256-kiB blocks, 30-ns R/W cycles, 1 CS) on mx53ard.
eNFC_CLK_ROOT is set up with a cycle time of 37.5 ns (400 MHz / 3 / 5) for this board, which satisfies the 30-ns NF R/W cycle requirement.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
NAND is not detected on my mx53ard.
I think we need to adjust the IOMUX as per: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/board/freescale...
Regards,
Fabio Estevam
On Tue, Feb 26, 2013 at 10:22 AM, Fabio Estevam festevam@gmail.com wrote:
Hi Benoit,
On Fri, Feb 15, 2013 at 6:54 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Add support for the Samsung K9LAG08U0M NAND Flash (2-GiB MLC NAND Flash, 2-kiB pages, 256-kiB blocks, 30-ns R/W cycles, 1 CS) on mx53ard.
eNFC_CLK_ROOT is set up with a cycle time of 37.5 ns (400 MHz / 3 / 5) for this board, which satisfies the 30-ns NF R/W cycle requirement.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
NAND is not detected on my mx53ard.
I think we need to adjust the IOMUX as per: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/board/freescale...
Yes, after using the same IOMUX from FSL U-boot I get:
NAND: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd5 (Samsung NAND 2GiB 3,3) NAND bus width 16 instead 8 bit No NAND device found!!! 0 MiB
....
MX53ARD U-Boot > nand info
Device 0: NAND 2GiB 3,3V 8-bit, sector size 256 KiB Page size 2048 b OOB size 64 b Erase size 262144 b MX53ARD U-Boot >
Hi Benoît,
On Tue, Feb 26, 2013 at 10:35 AM, Fabio Estevam festevam@gmail.com wrote:
Yes, after using the same IOMUX from FSL U-boot I get:
NAND: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd5 (Samsung NAND 2GiB 3,3) NAND bus width 16 instead 8 bit No NAND device found!!! 0 MiB
This should be fixed separetely and it is not related to your patch. I will submit a patch for this 16-bit detection issue
I was able to read and write to NAND, I have also tested to save env vars into NAND and it works fine.
So, after changing the IOMUX as per FSL U-boot you can add my:
Tested-by: Fabio Estevam fabio.estevam@freescale.com
Hi Fabio,
On Tuesday, February 26, 2013 3:21:25 PM, Fabio Estevam wrote:
Hi Benoît,
On Tue, Feb 26, 2013 at 10:35 AM, Fabio Estevam festevam@gmail.com wrote:
Yes, after using the same IOMUX from FSL U-boot I get:
NAND: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd5 (Samsung NAND 2GiB 3,3) NAND bus width 16 instead 8 bit No NAND device found!!! 0 MiB
This should be fixed separetely and it is not related to your patch. I will submit a patch for this 16-bit detection issue
OK. Please update all boards using mxc_nand.
I was able to read and write to NAND, I have also tested to save env vars into NAND and it works fine.
Great! Thanks for testing.
So, after changing the IOMUX as per FSL U-boot
If I look at FSL's setup_nfc() vs. my setup_iomux_nand(): - The IOMUX setup is the same, with CS1 and DA0-7 left in their reset ALT0 mode. - The pad setups differ from the reset values in FSL's code, so I think that this is all that needs to be changed (i.e. adding the mxc_iomux_set_pad()). Can you confirm? - Are 'M4IF_GPR.MM = 0' and 'EIM_CSxGCR2[12] = 0' also required, or is this handled properly by your board through BOOT_CFG1[6]? I think that we should enforce this too by software for the same reason as for bus width.
you can add my: Tested-by: Fabio Estevam fabio.estevam@freescale.com
Will do, thanks again. So for 01-03, and 15 (with 0x32000). Do you agree?
Best regards, Benoît
On Tue, Feb 26, 2013 at 1:53 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
OK. Please update all boards using mxc_nand.
Yes, will send a patch soon.
I was able to read and write to NAND, I have also tested to save env vars into NAND and it works fine.
Great! Thanks for testing.
So, after changing the IOMUX as per FSL U-boot
If I look at FSL's setup_nfc() vs. my setup_iomux_nand():
- The IOMUX setup is the same, with CS1 and DA0-7 left in their reset ALT0 mode.
- The pad setups differ from the reset values in FSL's code, so I think that this is all that needs to be changed (i.e. adding the mxc_iomux_set_pad()). Can you confirm?
Yes, correct.
- Are 'M4IF_GPR.MM = 0' and 'EIM_CSxGCR2[12] = 0' also required, or is this handled properly by your board through BOOT_CFG1[6]? I think that we should enforce this too by software for the same reason as for bus width.
Yes, we need to enforce this by software. If I skip such settings, NAND is no longer functional on mx53ard.
you can add my: Tested-by: Fabio Estevam fabio.estevam@freescale.com
Will do, thanks again. So for 01-03, and 15 (with 0x32000). Do you agree?
Yes, correct.
Very good job you did, thanks!
The page number indicated in the debug trace of mxc_nand_read_oob_syndrome() did not match the page being worked on.
By the way, replace the GCC-specific __FUNCTION__ with __func__.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: None Changes in v5: - Replace __FUNCTION__ with __func__.
Changes in v4: - New patch.
Changes in v3: None Changes in v2: None
drivers/mtd/nand/mxc_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index cead757..249328e 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -450,7 +450,7 @@ static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Reading OOB area of page %u to oob %p\n", - __FUNCTION__, host->page_addr, buf); + __func__, page, buf);
chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page); for (i = 0; i < chip->ecc.steps; i++) {
The syndrome functions should use the page number passed as argument instead of the page number saved upon NAND_CMD_READ0.
This does not make any difference if the NAND_NO_AUTOINCR option is set, but otherwise this fixes accesses to the wrong pages.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: - New patch.
Changes in v3: None Changes in v2: None
drivers/mtd/nand/mxc_nand.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 249328e..001c2c0 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -504,7 +504,7 @@ static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd, int n;
_mxc_nand_enable_hwecc(mtd, 0); - chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) { host->col_addr = n * eccsize; @@ -548,7 +548,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd, uint8_t *oob = chip->oob_poi;
MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n", - host->page_addr, buf, oob); + page, buf, oob);
/* first read the data area and the available portion of OOB */ for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) { @@ -586,7 +586,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
/* Then switch ECC off and read the OOB area to get the ECC code */ _mxc_nand_enable_hwecc(mtd, 0); - chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr); + chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page); eccsteps = chip->ecc.steps; oob = chip->oob_poi + chip->ecc.prepad; for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
On 02/15/2013 02:54:12 PM, Benoît Thébaudeau wrote:
The syndrome functions should use the page number passed as argument instead of the page number saved upon NAND_CMD_READ0.
This does not make any difference if the NAND_NO_AUTOINCR option is set, but otherwise this fixes accesses to the wrong pages.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4:
- New patch.
Changes in v3: None Changes in v2: None
drivers/mtd/nand/mxc_nand.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 249328e..001c2c0 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -504,7 +504,7 @@ static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd, int n;
_mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) { host->col_addr = n * eccsize;
@@ -548,7 +548,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd, uint8_t *oob = chip->oob_poi;
MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
host->page_addr, buf, oob);
page, buf, oob);/* first read the data area and the available portion of OOB */ for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
@@ -586,7 +586,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
/* Then switch ECC off and read the OOB area to get the ECC code */ _mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize,
host->page_addr);
- chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page); eccsteps = chip->ecc.steps; oob = chip->oob_poi + chip->ecc.prepad; for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
The debug print in mxc_nand_read_oob_syndrome() also needs to be fixed.
-Scott
Hi Scott,
On Tuesday, February 19, 2013 1:30:23 AM, Scott Wood wrote:
On 02/15/2013 02:54:12 PM, Benoît Thébaudeau wrote:
The syndrome functions should use the page number passed as argument instead of the page number saved upon NAND_CMD_READ0.
This does not make any difference if the NAND_NO_AUTOINCR option is set, but otherwise this fixes accesses to the wrong pages.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4:
- New patch.
Changes in v3: None Changes in v2: None
drivers/mtd/nand/mxc_nand.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 249328e..001c2c0 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -504,7 +504,7 @@ static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd, int n;
_mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) { host->col_addr = n * eccsize;
@@ -548,7 +548,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd, uint8_t *oob = chip->oob_poi;
MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
host->page_addr, buf, oob);
page, buf, oob);/* first read the data area and the available portion of OOB */ for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
@@ -586,7 +586,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
/* Then switch ECC off and read the OOB area to get the ECC code */ _mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize,
host->page_addr);
- chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page); eccsteps = chip->ecc.steps; oob = chip->oob_poi + chip->ecc.prepad; for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
The debug print in mxc_nand_read_oob_syndrome() also needs to be fixed.
Yes, but this is done by 05/19.
Best regards, Benoît
_TEXT_BASE must be set to CONFIG_SPL_TEXT_BASE for generic SPL, and to CONFIG_SYS_TEXT_BASE for non-SPL builds.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: - New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm1136/start.S | 4 ++++ arch/arm/cpu/arm1176/start.S | 8 ++++++++ arch/arm/cpu/arm720t/start.S | 2 +- arch/arm/cpu/arm920t/start.S | 4 ++++ arch/arm/cpu/arm925t/start.S | 4 ++++ arch/arm/cpu/arm926ejs/start.S | 2 +- arch/arm/cpu/arm946es/start.S | 4 ++++ arch/arm/cpu/arm_intcm/start.S | 6 +++++- arch/arm/cpu/armv7/start.S | 4 ++++ arch/arm/cpu/ixp/start.S | 4 ++++ arch/arm/cpu/pxa/start.S | 2 +- arch/arm/cpu/s3c44b0/start.S | 4 ++++ arch/arm/cpu/sa1100/start.S | 4 ++++ 13 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index a067b8a..4053e86 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -88,7 +88,11 @@ _end_vect:
.globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif
/* * These are defined in the board-specific linker script. diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 40df4b1..d11386a 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -98,7 +98,15 @@ _end_vect:
.globl _TEXT_BASE _TEXT_BASE: +#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ .word CONFIG_SYS_TEXT_BASE +#else +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else + .word CONFIG_SYS_TEXT_BASE +#endif +#endif
/* * Below variable is very important because we use MMU in U-Boot. diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 771d386..83722aa 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -85,7 +85,7 @@ _pad: .word 0x12345678 /* now 16*4=64 */
.globl _TEXT_BASE _TEXT_BASE: -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_SYS_TEXT_BASE diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 511d21d..f4f14e1 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -73,7 +73,11 @@ _fiq: .word fiq
.globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif
/* * These are defined in the board-specific linker script. diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index e8d6d71..95a0de7 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -79,7 +79,11 @@ _fiq: .word fiq
.globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif
/* * These are defined in the board-specific linker script. diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 66a8b65..39f9a2e 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -123,7 +123,7 @@ _TEXT_BASE: #ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ .word CONFIG_SYS_TEXT_BASE #else -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_SYS_TEXT_BASE diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index a7a98a4..0d57294 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -89,7 +89,11 @@ _vectors_end:
.globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif
/* * These are defined in the board-specific linker script. diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index c189849..f5e5381 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -85,7 +85,11 @@ _fiq:
.globl _TEXT_BASE _TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* address of _start in the linked image */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else + .word CONFIG_SYS_TEXT_BASE +#endif
/* * These are defined in the board-specific linker script. diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index dcc1f83..5490cee 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -81,7 +81,11 @@ _end_vect:
.globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif
/* * These are defined in the board-specific linker script. diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index efb5a40..11e3efa 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -98,7 +98,11 @@ _fiq: .word fiq
.globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif
/* * These are defined in the board-specific linker script. diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index e71803e..a276ee0 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -102,7 +102,7 @@ _end_vect:
.globl _TEXT_BASE _TEXT_BASE: -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_SYS_TEXT_BASE diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index 4528c91..974ca1b 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -64,7 +64,11 @@ _start: b reset
.globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif
/* * These are defined in the board-specific linker script. diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 3144299..88769e3 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -74,7 +74,11 @@ _fiq: .word fiq
.globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif
/* * These are defined in the board-specific linker script.
Commit e05e5de7fae5bec79617e113916dac6631251156 made ARM's relocate_code() return to its caller, but it did not update its declaration accordingly.
Fixing this function declaration fixes dropped C code following calls to relocate_code().
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: - New patch, extracted from "nand: mxc: Switch NAND SPL to generic SPL".
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
include/common.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/common.h b/include/common.h index 4ad17ea..691e279 100644 --- a/include/common.h +++ b/include/common.h @@ -515,7 +515,11 @@ int dcache_status (void); void dcache_enable (void); void dcache_disable(void); void mmu_disable(void); -void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn)); +void relocate_code(ulong, gd_t *, ulong) +#if !defined(CONFIG_ARM) +__attribute__ ((noreturn)) +#endif +; ulong get_endaddr (void); void trap_init (ulong); #if defined (CONFIG_4xx) || \
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: - New patch, extracted from "nand: mxc: Switch NAND SPL to generic SPL".
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm1136/start.S | 2 -- 1 file changed, 2 deletions(-)
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 4053e86..b5931f8 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -239,8 +239,6 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop - bx lr - #endif
relocate_done:
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: - New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm1136/start.S | 1 - arch/arm/cpu/arm1176/start.S | 1 - arch/arm/cpu/arm720t/start.S | 1 - arch/arm/cpu/arm920t/start.S | 1 - arch/arm/cpu/arm925t/start.S | 1 - arch/arm/cpu/arm926ejs/start.S | 2 -- arch/arm/cpu/arm946es/start.S | 1 - arch/arm/cpu/arm_intcm/start.S | 1 - arch/arm/cpu/armv7/start.S | 1 - arch/arm/cpu/ixp/start.S | 1 - arch/arm/cpu/pxa/start.S | 1 - arch/arm/cpu/s3c44b0/start.S | 1 - arch/arm/cpu/sa1100/start.S | 1 - 13 files changed, 14 deletions(-)
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index b5931f8..9554807 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -188,7 +188,6 @@ relocate_code:
adr r0, _start cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index d11386a..9617249 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -251,7 +251,6 @@ relocate_code:
adr r0, _start cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 83722aa..d2d8b53 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -166,7 +166,6 @@ relocate_code:
adr r0, _start cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index f4f14e1..683cf55 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -205,7 +205,6 @@ relocate_code:
adr r0, _start cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 95a0de7..5e81bdf 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -195,7 +195,6 @@ relocate_code:
adr r0, _start cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 39f9a2e..93916af 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -211,9 +211,7 @@ relocate_code: mov r6, r2 /* save addr of destination */
adr r0, _start - sub r9, r6, r0 /* r9 <- relocation offset */ cmp r0, r6 - moveq r9, #0 /* no relocation. offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 0d57294..6ecf7ec 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -170,7 +170,6 @@ relocate_code:
adr r0, _start cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index f5e5381..fcfd367 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -166,7 +166,6 @@ relocate_code:
adr r0, _start cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 5490cee..784c363 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -178,7 +178,6 @@ ENTRY(relocate_code)
adr r0, _start cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index 11e3efa..be8fcac 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -268,7 +268,6 @@ relocate_code:
adr r0, _start cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index a276ee0..fa7d4ab 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -190,7 +190,6 @@ relocate_code:
adr r0, _start cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index 974ca1b..757eadc 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -151,7 +151,6 @@ relocate_code:
adr r0, _start cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 88769e3..6480ac4 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -155,7 +155,6 @@ relocate_code:
adr r0, _start cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs
Use __image_copy_end instead of __bss_start for the end of the image to relocate. This is the same as commit 033ca72, but applied to all ARM start.S.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: - New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm1176/start.S | 6 +++++- arch/arm/cpu/arm720t/start.S | 6 +++++- arch/arm/cpu/arm920t/ep93xx/u-boot.lds | 3 +++ arch/arm/cpu/arm920t/start.S | 6 +++++- arch/arm/cpu/arm925t/start.S | 6 +++++- arch/arm/cpu/arm926ejs/start.S | 6 +++++- arch/arm/cpu/arm946es/start.S | 6 +++++- arch/arm/cpu/arm_intcm/start.S | 6 +++++- arch/arm/cpu/ixp/start.S | 6 +++++- arch/arm/cpu/ixp/u-boot.lds | 2 ++ arch/arm/cpu/pxa/start.S | 6 +++++- arch/arm/cpu/s3c44b0/start.S | 6 +++++- arch/arm/cpu/sa1100/start.S | 6 +++++- board/actux1/u-boot.lds | 3 +++ board/actux2/u-boot.lds | 3 +++ board/actux3/u-boot.lds | 3 +++ board/davinci/da8xxevm/u-boot-spl-hawk.lds | 1 + board/dvlhost/u-boot.lds | 3 +++ board/samsung/smdk6400/u-boot-nand.lds | 4 ++++ board/vpac270/u-boot-spl.lds | 2 ++ nand_spl/board/karo/tx25/u-boot.lds | 2 ++ nand_spl/board/samsung/smdk6400/u-boot.lds | 2 ++ 22 files changed, 83 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 9617249..e7d2737 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -127,6 +127,10 @@ _TEXT_PHY_BASE: _bss_start_ofs: .word __bss_start - _start
+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -253,7 +257,7 @@ relocate_code: cmp r0, r6 beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */
copy_loop: diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index d2d8b53..440aff5 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -101,6 +101,10 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start
+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -168,7 +172,7 @@ relocate_code: cmp r0, r6 beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */
copy_loop: diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds index 008ae89..62315de 100644 --- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds +++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds @@ -55,6 +55,9 @@ SECTIONS }
. = ALIGN(4); + + __image_copy_end = .; + __bss_start = .; .bss : { *(.bss) } __bss_end__ = .; diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 683cf55..60b6a80 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -89,6 +89,10 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start
+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -207,7 +211,7 @@ relocate_code: cmp r0, r6 beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */
copy_loop: diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 5e81bdf..6d5c9de 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -95,6 +95,10 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start
+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -197,7 +201,7 @@ relocate_code: cmp r0, r6 beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */
copy_loop: diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 93916af..70551ec 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -140,6 +140,10 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start
+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -214,7 +218,7 @@ relocate_code: cmp r0, r6 beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */
copy_loop: diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 6ecf7ec..8a245e0 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -105,6 +105,10 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start
+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -172,7 +176,7 @@ relocate_code: cmp r0, r6 beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */
copy_loop: diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index fcfd367..9e1a34e 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -101,6 +101,10 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start
+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -168,7 +172,7 @@ relocate_code: cmp r0, r6 beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */
copy_loop: diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index be8fcac..96cc014 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -114,6 +114,10 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start
+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -270,7 +274,7 @@ relocate_code: cmp r0, r6 beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */
copy_loop: diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds index 81d954f..d9bb5da 100644 --- a/arch/arm/cpu/ixp/u-boot.lds +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -54,6 +54,8 @@ SECTIONS
. = ALIGN(4);
+ __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index fa7d4ab..f555851 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -118,6 +118,10 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start
+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -192,7 +196,7 @@ relocate_code: cmp r0, r6 beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */
copy_loop: diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index 757eadc..e34e387 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -80,6 +80,10 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start
+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -153,7 +157,7 @@ relocate_code: cmp r0, r6 beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */
copy_loop: diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 6480ac4..fb58977 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -90,6 +90,10 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start
+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -157,7 +161,7 @@ relocate_code: cmp r0, r6 beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */
copy_loop: diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index c41eed0..34ed90d 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -61,6 +61,9 @@ SECTIONS }
. = ALIGN (4); + + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index 8409984..8337457 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -61,6 +61,9 @@ SECTIONS }
. = ALIGN (4); + + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index a3bd02b..a72a666 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -61,6 +61,9 @@ SECTIONS }
. = ALIGN (4); + + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds index 86dc172..174955e 100644 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -63,6 +63,7 @@ SECTIONS }
. = ALIGN(4); + __image_copy_end = .; __rel_dyn_start = .; __rel_dyn_end = .; __dynsym_start = .; diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds index 1bd1700..9c14daa 100644 --- a/board/dvlhost/u-boot.lds +++ b/board/dvlhost/u-boot.lds @@ -61,6 +61,9 @@ SECTIONS }
. = ALIGN (4); + + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/board/samsung/smdk6400/u-boot-nand.lds b/board/samsung/smdk6400/u-boot-nand.lds index fbb442a..2c3a60b 100644 --- a/board/samsung/smdk6400/u-boot-nand.lds +++ b/board/samsung/smdk6400/u-boot-nand.lds @@ -53,6 +53,10 @@ SECTIONS #include <u-boot.lst> }
+ . = ALIGN(4); + + __image_copy_end = .; + . = align(4); .mmudata : { *(.mmudata) }
diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 20161a4..e344436 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -63,6 +63,8 @@ SECTIONS
. = ALIGN(4);
+ __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/nand_spl/board/karo/tx25/u-boot.lds b/nand_spl/board/karo/tx25/u-boot.lds index ee36131..95ea8ac 100644 --- a/nand_spl/board/karo/tx25/u-boot.lds +++ b/nand_spl/board/karo/tx25/u-boot.lds @@ -54,6 +54,8 @@ SECTIONS
. = ALIGN(4);
+ __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/nand_spl/board/samsung/smdk6400/u-boot.lds b/nand_spl/board/samsung/smdk6400/u-boot.lds index 2ed6466..293ae02 100644 --- a/nand_spl/board/samsung/smdk6400/u-boot.lds +++ b/nand_spl/board/samsung/smdk6400/u-boot.lds @@ -58,6 +58,8 @@ SECTIONS
. = ALIGN(4);
+ __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*)
Hi Benoît,
On Fri, 15 Feb 2013 21:54:17 +0100, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Use __image_copy_end instead of __bss_start for the end of the image to relocate. This is the same as commit 033ca72, but applied to all ARM start.S.
What is the benefit of this? I find it more logical for BSS-related code to use a BSS-related symbol than an image-copy related symbol.
Amicalement,
Hi Albert,
On Saturday, February 16, 2013 7:47:13 PM, Albert ARIBAUD wrote:
Hi Benoît,
On Fri, 15 Feb 2013 21:54:17 +0100, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Use __image_copy_end instead of __bss_start for the end of the image to relocate. This is the same as commit 033ca72, but applied to all ARM start.S.
What is the benefit of this? I find it more logical for BSS-related code to use a BSS-related symbol than an image-copy related symbol.
I don't see why you are talking about BSS-related code. This piece of code is just supposed to copy the text and rodata from the source image to its destination location, before optionally relocating its symbols. BSS has nothing to do with this, so I find this image-copy symbol more appropriate here.
But besides the naming, the benefit is also that some linker scripts put some stuff (e.g. MMU tables used early before jumping to relocated code, or relocation info) between this __image_copy_end and __bss_start, that does not have to be copied or relocated, so this patch saves a useless data copy in that case.
Best regards, Benoît
Hi Benoît,
On Sat, 16 Feb 2013 20:54:01 +0100 (CET), Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Hi Albert,
On Saturday, February 16, 2013 7:47:13 PM, Albert ARIBAUD wrote:
Hi Benoît,
On Fri, 15 Feb 2013 21:54:17 +0100, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Use __image_copy_end instead of __bss_start for the end of the image to relocate. This is the same as commit 033ca72, but applied to all ARM start.S.
What is the benefit of this? I find it more logical for BSS-related code to use a BSS-related symbol than an image-copy related symbol.
I don't see why you are talking about BSS-related code. This piece of code is just supposed to copy the text and rodata from the source image to its destination location, before optionally relocating its symbols. BSS has nothing to do with this, so I find this image-copy symbol more appropriate here.
But besides the naming, the benefit is also that some linker scripts put some stuff (e.g. MMU tables used early before jumping to relocated code, or relocation info) between this __image_copy_end and __bss_start, that does not have to be copied or relocated, so this patch saves a useless data copy in that case.
Apologies -- this is indeed copy-related, not BSS-related, code, and thus the image-copy related symbol is apt, and your additional note makes it all the more valid.
Best regards, Benoît
Amicalement,
The purpose of .globl is to export symbols for ld, not to declare external symbols.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: - New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/lib/crt0.S | 21 --------------------- 1 file changed, 21 deletions(-)
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 4f60958..6946cbc 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -67,27 +67,6 @@ */
/* - * declare nand_boot() or board_init_r() to jump to at end of crt0 - */ - -#if defined(CONFIG_NAND_SPL) - -.globl nand_boot - -#elif ! defined(CONFIG_SPL_BUILD) - -.globl board_init_r - -#endif - -/* - * start and end of BSS - */ - -.globl __bss_start -.globl __bss_end__ - -/* * entry point of crt0 sequence */
PAD_TO is not a generic SPL configuration option, so use CONFIG_SPL_MAX_SIZE instead.
We want to use --pad-to with a size, but this option expects an address, so use u-boot-spl.bin instead of u-boot-spl as the input file in order to get addresses starting at 0.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: - Use u-boot-spl.bin instead of u-boot-spl in order to avoid having to use --change-addresses.
Changes in v6: - Fix size passed to --pad-to thanks to --change-addresses.
Changes in v5: None Changes in v4: - New patch.
Changes in v3: None Changes in v2: None
Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile index a8c7b7b..317dffc 100644 --- a/Makefile +++ b/Makefile @@ -486,7 +486,8 @@ $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_MAX_SIZE) \ + -I binary -O binary $< $(obj)spl/u-boot-spl-pad.bin cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@ rm $(obj)spl/u-boot-spl-pad.bin
Hi Poonam, Andy,
On Friday, February 15, 2013 9:54:19 PM, Benoît Thébaudeau wrote:
PAD_TO is not a generic SPL configuration option, so use CONFIG_SPL_MAX_SIZE instead.
We want to use --pad-to with a size, but this option expects an address, so use u-boot-spl.bin instead of u-boot-spl as the input file in order to get addresses starting at 0.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Changes in v7:
- Use u-boot-spl.bin instead of u-boot-spl in order to avoid having to use --change-addresses.
Changes in v6:
- Fix size passed to --pad-to thanks to --change-addresses.
Changes in v5: None Changes in v4:
- New patch.
Changes in v3: None Changes in v2: None
Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile index a8c7b7b..317dffc 100644 --- a/Makefile +++ b/Makefile @@ -486,7 +486,8 @@ $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl$(obj)spl/u-boot-spl-pad.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_MAX_SIZE) \-I binary -O binary $< $(obj)spl/u-boot-spl-pad.bin
I would like to let you know what is going on, and to get your feedback for this patch.
include/configs/p1_p2_rdb_pc.h seems to be the only current user of u-boot-with-spl.bin, triggered for example by the P2020RDB-PC_NAND config.
Before this patch, PAD_TO was used, but there is no such definition for this board for generic SPL, so this board seems broken, all the more none of the various values defined for CONFIG_SYS_TEXT_BASE relatively to CONFIG_SPL_TEXT_BASE would be compatible with an image built by appending U-Boot to the generic SPL. Can you confirm?
This patch won't fix this board, but I want to make sure that it won't be an issue for you now or later.
Best regards, Benoît
On Sunday, February 17, 2013 5:16:49 PM, Benoît Thébaudeau wrote:
Hi Poonam, Andy,
On Friday, February 15, 2013 9:54:19 PM, Benoît Thébaudeau wrote:
PAD_TO is not a generic SPL configuration option, so use CONFIG_SPL_MAX_SIZE instead.
We want to use --pad-to with a size, but this option expects an address, so use u-boot-spl.bin instead of u-boot-spl as the input file in order to get addresses starting at 0.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Changes in v7:
- Use u-boot-spl.bin instead of u-boot-spl in order to avoid having to use --change-addresses.
Changes in v6:
- Fix size passed to --pad-to thanks to --change-addresses.
Changes in v5: None Changes in v4:
- New patch.
Changes in v3: None Changes in v2: None
Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile index a8c7b7b..317dffc 100644 --- a/Makefile +++ b/Makefile @@ -486,7 +486,8 @@ $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary$(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_MAX_SIZE) \-I binary -O binary $< $(obj)spl/u-boot-spl-pad.binI would like to let you know what is going on, and to get your feedback for this patch.
include/configs/p1_p2_rdb_pc.h seems to be the only current user of u-boot-with-spl.bin, triggered for example by the P2020RDB-PC_NAND config.
Before this patch, PAD_TO was used, but there is no such definition for this board for generic SPL, so this board seems broken, all the more none of the various values defined for CONFIG_SYS_TEXT_BASE relatively to CONFIG_SPL_TEXT_BASE would be compatible with an image built by appending U-Boot to the generic SPL. Can you confirm?
This patch won't fix this board, but I want to make sure that it won't be an issue for you now or later.
I'm also wondering why there is both generic SPL for NAND and legacy "NAND SPL" for p1_p2_rdb, all the more the "NAND SPL" version does not seem to be used in boards.cfg.
Best regards, Benoît
On 02/18/2013 06:28:15 AM, Benoît Thébaudeau wrote:
I'm also wondering why there is both generic SPL for NAND and legacy "NAND SPL" for p1_p2_rdb, all the more the "NAND SPL" version does not seem to be used in boards.cfg.
"p1_p2_rdb_pc" and "P1_P2_RDB" are different targets (unfortunately). The former is for newer boards and has been converted to the new SPL. The latter is for older boards, which I do not have access to and have had a hard time getting information about (which would be required to merge the two targets). Perhaps P1_P2_RDB should just be removed.
-Scott
On Sun, Feb 17, 2013 at 05:16:49PM +0100, Beno??t Th??baudeau wrote:
Hi Poonam, Andy,
On Friday, February 15, 2013 9:54:19 PM, Beno??t Th??baudeau wrote:
PAD_TO is not a generic SPL configuration option, so use CONFIG_SPL_MAX_SIZE instead.
We want to use --pad-to with a size, but this option expects an address, so use u-boot-spl.bin instead of u-boot-spl as the input file in order to get addresses starting at 0.
Signed-off-by: Beno??t Th??baudeau benoit.thebaudeau@advansee.com
Changes in v7:
- Use u-boot-spl.bin instead of u-boot-spl in order to avoid having to use --change-addresses.
Changes in v6:
- Fix size passed to --pad-to thanks to --change-addresses.
Changes in v5: None Changes in v4:
- New patch.
Changes in v3: None Changes in v2: None
Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile index a8c7b7b..317dffc 100644 --- a/Makefile +++ b/Makefile @@ -486,7 +486,8 @@ $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl$(obj)spl/u-boot-spl-pad.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_MAX_SIZE) \-I binary -O binary $< $(obj)spl/u-boot-spl-pad.binI would like to let you know what is going on, and to get your feedback for this patch.
include/configs/p1_p2_rdb_pc.h seems to be the only current user of u-boot-with-spl.bin, triggered for example by the P2020RDB-PC_NAND config.
cam_enc_4xx also uses this target. Heiko? It looks like this change should be safe there as well.
Before this patch, PAD_TO was used, but there is no such definition for this board for generic SPL, so this board seems broken, all the more none of the various values defined for CONFIG_SYS_TEXT_BASE relatively to CONFIG_SPL_TEXT_BASE would be compatible with an image built by appending U-Boot to the generic SPL. Can you confirm?
This patch won't fix this board, but I want to make sure that it won't be an issue for you now or later.
On Monday, February 18, 2013 5:50:59 PM, Tom Rini wrote:
On Sun, Feb 17, 2013 at 05:16:49PM +0100, Beno??t Th??baudeau wrote:
Hi Poonam, Andy,
On Friday, February 15, 2013 9:54:19 PM, Beno??t Th??baudeau wrote:
PAD_TO is not a generic SPL configuration option, so use CONFIG_SPL_MAX_SIZE instead.
We want to use --pad-to with a size, but this option expects an address, so use u-boot-spl.bin instead of u-boot-spl as the input file in order to get addresses starting at 0.
Signed-off-by: Beno??t Th??baudeau benoit.thebaudeau@advansee.com
Changes in v7:
- Use u-boot-spl.bin instead of u-boot-spl in order to avoid having to
use --change-addresses.
Changes in v6:
- Fix size passed to --pad-to thanks to --change-addresses.
Changes in v5: None Changes in v4:
- New patch.
Changes in v3: None Changes in v2: None
Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile index a8c7b7b..317dffc 100644 --- a/Makefile +++ b/Makefile @@ -486,7 +486,8 @@ $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary$(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_MAX_SIZE) \-I binary -O binary $< $(obj)spl/u-boot-spl-pad.binI would like to let you know what is going on, and to get your feedback for this patch.
include/configs/p1_p2_rdb_pc.h seems to be the only current user of u-boot-with-spl.bin, triggered for example by the P2020RDB-PC_NAND config.
cam_enc_4xx also uses this target. Heiko? It looks like this change should be safe there as well.
And MPC8313ERDB too.
But I've just seen that commit 74752ba did something for that in u-boot/master, and this commit is not in u-boot-imx/master on which I based this series. Why is u-boot-imx/master not sync'ed with u-boot/master? How am I supposed to handle patch sets depending on several custodian repositories?
Commit 74752ba performs a '--pad-to=$(or $(CONFIG_SPL_PAD_TO),0)' on u-boot-spl. I could use this CONFIG_SPL_PAD_TO for this series too, but is it really necessary to have both CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE? In other words, is there any case for which CONFIG_SPL_PAD_TO could be different from CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE for a valid reason?
Before this patch, PAD_TO was used, but there is no such definition for this board for generic SPL, so this board seems broken, all the more none of the various values defined for CONFIG_SYS_TEXT_BASE relatively to CONFIG_SPL_TEXT_BASE would be compatible with an image built by appending U-Boot to the generic SPL. Can you confirm?
This patch won't fix this board, but I want to make sure that it won't be an issue for you now or later.
Best regards, Benoît
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1
On 02/18/2013 12:26 PM, Benoît Thébaudeau wrote:
[snip]
But I've just seen that commit 74752ba did something for that in u-boot/master, and this commit is not in u-boot-imx/master on which I based this series. Why is u-boot-imx/master not sync'ed with u-boot/master? How am I supposed to handle patch sets depending on several custodian repositories?
I'm not sure why u-boot-imx is out of sync at the moment. My rule of thumb is to start working on u-boot/master and cherry-pick out things I need from other places into a -test branch.
I know the kernel folks have to deal with a lot of this as well, but I think it ends up being a developer choice on what best fits their needs when they need N different series to be applied for their starting point.
Commit 74752ba performs a '--pad-to=$(or $(CONFIG_SPL_PAD_TO),0)' on u-boot-spl. I could use this CONFIG_SPL_PAD_TO for this series too, but is it really necessary to have both CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE? In other words, is there any case for which CONFIG_SPL_PAD_TO could be different from CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE for a valid reason?
I was wondering along those lines. I don't _think_ we need both CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE, but we can't combine CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE as on TI platforms we start quite well above zero (0x402F0400 on am33xx, etc). That said, I guess we do need CONFIG_SPL_PAD_TO so that some platforms can do: #define CONFIG_SPL_PAD_TO (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE) and others just #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
- -- Tom
On Monday, February 18, 2013 6:27:50 PM, Tom Rini wrote:
Commit 74752ba performs a '--pad-to=$(or $(CONFIG_SPL_PAD_TO),0)' on u-boot-spl. I could use this CONFIG_SPL_PAD_TO for this series too, but is it really necessary to have both CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE? In other words, is there any case for which CONFIG_SPL_PAD_TO could be different from CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE for a valid reason?
I was wondering along those lines. I don't _think_ we need both CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE, but we can't combine CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE as on TI platforms we start quite well above zero (0x402F0400 on am33xx, etc). That said, I guess we do need CONFIG_SPL_PAD_TO so that some platforms can do: #define CONFIG_SPL_PAD_TO (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE) and others just #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
If we did like my patch here, i.e. use objcopy with u-boot-spl.bin instead of u-boot-spl, objcopy would always get a fake 0x0 address at the beginning of the .bin, so CONFIG_SPL_MAX_SIZE could be used with --pad-to, and CONFIG_SPL_PAD_TO would be useless.
The only question is if we may need to have an empty gap between the SPL and U-Boot within the resulting image. I don't think so since that would mean that the target memory device has an area that is not really available at the location of this gap.
Best regards, Benoît
On 02/18/2013 12:00:52 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 6:27:50 PM, Tom Rini wrote:
Commit 74752ba performs a '--pad-to=$(or $(CONFIG_SPL_PAD_TO),0)' on u-boot-spl. I could use this CONFIG_SPL_PAD_TO for this series too, but is it really necessary to have both CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE? In other words, is there any case for which CONFIG_SPL_PAD_TO could be different from CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE for a valid reason?
They're logically different things.
I was wondering along those lines. I don't _think_ we need both CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE, but we can't combine CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE as on TI platforms we start quite well above zero (0x402F0400 on am33xx, etc). That
said, I
guess we do need CONFIG_SPL_PAD_TO so that some platforms can do: #define CONFIG_SPL_PAD_TO (CONFIG_SPL_TEXT_BASE +
CONFIG_SPL_MAX_SIZE)
and others just #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
If we did like my patch here, i.e. use objcopy with u-boot-spl.bin instead of u-boot-spl, objcopy would always get a fake 0x0 address at the beginning of the .bin, so CONFIG_SPL_MAX_SIZE could be used with --pad-to, and CONFIG_SPL_PAD_TO would be useless.
The only question is if we may need to have an empty gap between the SPL and U-Boot within the resulting image. I don't think so since that would mean that the target memory device has an area that is not really available at the location of this gap.
Why not allow that possibility? Maybe it's easier for the SPL to load from a particular offset (e.g. NAND starting at the beginning of a block)?
-Scott
On Monday, February 18, 2013 7:02:49 PM, Scott Wood wrote:
On 02/18/2013 12:00:52 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 6:27:50 PM, Tom Rini wrote:
Commit 74752ba performs a '--pad-to=$(or $(CONFIG_SPL_PAD_TO),0)' on u-boot-spl. I could use this CONFIG_SPL_PAD_TO for this series too, but is it really necessary to have both CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE? In other words, is there any case for which CONFIG_SPL_PAD_TO could be different from CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE for a valid reason?
They're logically different things.
I was wondering along those lines. I don't _think_ we need both CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE, but we can't combine CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE as on TI platforms we start quite well above zero (0x402F0400 on am33xx, etc). That
said, I
guess we do need CONFIG_SPL_PAD_TO so that some platforms can do: #define CONFIG_SPL_PAD_TO (CONFIG_SPL_TEXT_BASE +
CONFIG_SPL_MAX_SIZE)
and others just #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
If we did like my patch here, i.e. use objcopy with u-boot-spl.bin instead of u-boot-spl, objcopy would always get a fake 0x0 address at the beginning of the .bin, so CONFIG_SPL_MAX_SIZE could be used with --pad-to, and CONFIG_SPL_PAD_TO would be useless.
The only question is if we may need to have an empty gap between the SPL and U-Boot within the resulting image. I don't think so since that would mean that the target memory device has an area that is not really available at the location of this gap.
Why not allow that possibility?
To save a config setting (there are already many for SPL) if this is not strictly required, but also for the reason below.
Maybe it's easier for the SPL to load from a particular offset (e.g. NAND starting at the beginning of a block)?
CONFIG_SPL_MAX_SIZE would be closer to a NAND mapping in that case (e.g. size of 1 NAND Flash block) than CONFIG_SPL_PAD_TO (address within RAM that should be considered relatively to CONFIG_SPL_TEXT_BASE to get the NAND offset).
Also, CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE depend on each other: If both can be defined, you may change one forgetting the other one, which could e.g. result in an overlapping of SPL and U-Boot that won't show up at build time (with CONFIG_SPL_MAX_SIZE = 0x1000 and CONFIG_SPL_PAD_TO = CONFIG_SPL_TEXT_BASE + 0x800, the SPL would build fine, and objcopy wouldn't complain).
Best regards, Benoît
On 02/18/2013 12:22:58 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 7:02:49 PM, Scott Wood wrote:
On 02/18/2013 12:00:52 PM, Benoît Thébaudeau wrote:
The only question is if we may need to have an empty gap between
the
SPL and U-Boot within the resulting image. I don't think so since that
would
mean that the target memory device has an area that is not really available
at
the location of this gap.
Why not allow that possibility?
To save a config setting (there are already many for SPL) if this is not strictly required, but also for the reason below.
Maybe it's easier for the SPL to load from a particular offset (e.g. NAND starting at the beginning of a block)?
CONFIG_SPL_MAX_SIZE would be closer to a NAND mapping in that case (e.g. size of 1 NAND Flash block) than CONFIG_SPL_PAD_TO (address within RAM that should be considered relatively to CONFIG_SPL_TEXT_BASE to get the NAND offset).
CONFIG_SPL_PAD_TO is for the placement of the payload -- and it's not a RAM address. Currently it is a link address (or zero if the linker script handles padding, or padding is not required for other reasons). With your patch it it is a file offset, IIUC.
CONFIG_SPL_MAX_SIZE is what it says -- the maximum size that the SPL may be, ideally to be enforced by the linker script.
They are different. An SPL wanting the payload to begin as a block boundary does not mean the hardware is suddenly capable of loading an entire block of SPL.
Also, CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE depend on each other: If both can be defined, you may change one forgetting the other one, which could e.g. result in an overlapping of SPL and U-Boot that won't show up at build time (with CONFIG_SPL_MAX_SIZE = 0x1000 and CONFIG_SPL_PAD_TO = CONFIG_SPL_TEXT_BASE
- 0x800, the SPL would build fine, and objcopy wouldn't complain).
So add a check that CONFIG_SPL_PAD_TO >= CONFIG_SPL_MAX_SIZE (assuming the new interpretation of CONFIG_SPL_PAD_TO as a file offset), and let CONFIG_SPL_PAD_TO default to CONFIG_SPL_MAX_SIZE if not set.
-Scott
On Monday, February 18, 2013 7:24:51 PM, Scott Wood wrote:
On 02/18/2013 12:22:58 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 7:02:49 PM, Scott Wood wrote:
On 02/18/2013 12:00:52 PM, Benoît Thébaudeau wrote:
The only question is if we may need to have an empty gap between
the
SPL and U-Boot within the resulting image. I don't think so since that
would
mean that the target memory device has an area that is not really available
at
the location of this gap.
Why not allow that possibility?
To save a config setting (there are already many for SPL) if this is not strictly required, but also for the reason below.
Maybe it's easier for the SPL to load from a particular offset (e.g. NAND starting at the beginning of a block)?
CONFIG_SPL_MAX_SIZE would be closer to a NAND mapping in that case (e.g. size of 1 NAND Flash block) than CONFIG_SPL_PAD_TO (address within RAM that should be considered relatively to CONFIG_SPL_TEXT_BASE to get the NAND offset).
CONFIG_SPL_PAD_TO is for the placement of the payload
Correct.
-- and it's not a RAM address.
It doesn't have to be, but it may be for some configs.
Currently it is a link address (or zero if the linker script handles padding, or padding is not required for other reasons).
Correct.
With your patch it it is a file offset, IIUC.
With my patch, it is nothing at all since only CONFIG_SPL_MAX_SIZE is used.
CONFIG_SPL_MAX_SIZE is what it says -- the maximum size that the SPL may be, ideally to be enforced by the linker script.
Correct.
They are different. An SPL wanting the payload to begin as a block boundary does not mean the hardware is suddenly capable of loading an entire block of SPL.
Sure, but my question is: Why would you want to have a 2-kiB SPL followed by a 126-kiB gap before the payload? Why couldn't you place the payload on the 1st page boundary after the SPL?
If there are hardware constraints or something that make CONFIG_SPL_PAD_TO useful in some cases, then let's use it, but otherwise, why keep it?
And if we keep it, do we change it to an image offset, or do we keep it as a link address?
Also, CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE depend on each other: If both can be defined, you may change one forgetting the other one, which could e.g. result in an overlapping of SPL and U-Boot that won't show up at build time (with CONFIG_SPL_MAX_SIZE = 0x1000 and CONFIG_SPL_PAD_TO = CONFIG_SPL_TEXT_BASE
- 0x800, the SPL would build fine, and objcopy wouldn't complain).
So add a check that CONFIG_SPL_PAD_TO >= CONFIG_SPL_MAX_SIZE (assuming the new interpretation of CONFIG_SPL_PAD_TO as a file offset), and let CONFIG_SPL_PAD_TO default to CONFIG_SPL_MAX_SIZE if not set.
That would make sense. The current default value of 0 for CONFIG_SPL_PAD_TO does not make sense since it means that the SPL can't know where the payload is located within the image.
Best regards, Benoît
On 02/18/2013 12:52:51 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 7:24:51 PM, Scott Wood wrote:
On 02/18/2013 12:22:58 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 7:02:49 PM, Scott Wood wrote:
On 02/18/2013 12:00:52 PM, Benoît Thébaudeau wrote:
The only question is if we may need to have an empty gap
between
the
SPL and U-Boot within the resulting image. I don't think so since that
would
mean that the target memory device has an area that is not really
available
at
the location of this gap.
Why not allow that possibility?
To save a config setting (there are already many for SPL) if this
is
not strictly required, but also for the reason below.
Maybe it's easier for the SPL to load from a particular offset (e.g. NAND starting at the beginning
of a
block)?
CONFIG_SPL_MAX_SIZE would be closer to a NAND mapping in that case (e.g. size of 1 NAND Flash block) than CONFIG_SPL_PAD_TO (address within RAM
that
should be considered relatively to CONFIG_SPL_TEXT_BASE to get the NAND
offset).
CONFIG_SPL_PAD_TO is for the placement of the payload
Correct.
-- and it's not a RAM address.
It doesn't have to be, but it may be for some configs.
Right. My point is it shouldn't be defined as a RAM address.
Currently it is a link address (or zero if the linker script handles padding, or padding is not required for other
reasons).
Correct.
With your patch it it is a file offset, IIUC.
With my patch, it is nothing at all since only CONFIG_SPL_MAX_SIZE is used.
Sorry, I just meant with your change to how objcopy is invoked. What you pass into objcopy is a file offset.
CONFIG_SPL_MAX_SIZE is what it says -- the maximum size that the SPL may be, ideally to be enforced by the linker script.
Correct.
They are different. An SPL wanting the payload to begin as a block boundary does not mean the hardware is suddenly capable of loading
an
entire block of SPL.
Sure, but my question is: Why would you want to have a 2-kiB SPL followed by a 126-kiB gap before the payload? Why couldn't you place the payload on the 1st page boundary after the SPL?
You can, and we usually do. But size-limited SPLs may want to simplify (e.g. bad block detection needs some special logic to handle beginning inside a block), and it may not always be 126 KiB.
E.g. MPC8313ERDB uses small-page NAND, so it's only 12KiB that gets wasted. It currently has MAX_SIZE of 4KiB but PAD_TO of base plus 16KiB.
If there are hardware constraints or something that make CONFIG_SPL_PAD_TO useful in some cases, then let's use it, but otherwise, why keep it?
It's easier to mainain orthogonality (and use defaults for simplicity) than to restore it after the fact if we need it later.
And if we keep it, do we change it to an image offset, or do we keep it as a link address?
Changing to an image offset sounds good.
Also, CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE depend on each
other:
If both can be defined, you may change one forgetting the other one, which could e.g. result in an overlapping of SPL and U-Boot that won't show up at build time (with CONFIG_SPL_MAX_SIZE = 0x1000 and CONFIG_SPL_PAD_TO = CONFIG_SPL_TEXT_BASE
- 0x800, the SPL would build fine, and objcopy wouldn't complain).
So add a check that CONFIG_SPL_PAD_TO >= CONFIG_SPL_MAX_SIZE
(assuming
the new interpretation of CONFIG_SPL_PAD_TO as a file offset), and
let
CONFIG_SPL_PAD_TO default to CONFIG_SPL_MAX_SIZE if not set.
That would make sense. The current default value of 0 for CONFIG_SPL_PAD_TO does not make sense since it means that the SPL can't know where the payload is located within the image.
CONFIG_SPL_PAD_TO is not the mechanism that is used for finding the payload. On mpc85xx it is unnecessary because the SPL will always be fixed size, because the reset vector goes at the end. It's also possible that some SPLs could use linker symbols to find the end of the SPL, if they want to pack more tightly.
-Scott
Hi Scott,
On Monday, February 18, 2013 8:11:22 PM, Scott Wood wrote:
On 02/18/2013 12:52:51 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 7:24:51 PM, Scott Wood wrote:
On 02/18/2013 12:22:58 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 7:02:49 PM, Scott Wood wrote:
On 02/18/2013 12:00:52 PM, Benoît Thébaudeau wrote:
The only question is if we may need to have an empty gap
between
the
SPL and U-Boot within the resulting image. I don't think so since that
would
mean that the target memory device has an area that is not really
available
at
the location of this gap.
Why not allow that possibility?
To save a config setting (there are already many for SPL) if this
is
not strictly required, but also for the reason below.
Maybe it's easier for the SPL to load from a particular offset (e.g. NAND starting at the beginning
of a
block)?
CONFIG_SPL_MAX_SIZE would be closer to a NAND mapping in that case (e.g. size of 1 NAND Flash block) than CONFIG_SPL_PAD_TO (address within RAM
that
should be considered relatively to CONFIG_SPL_TEXT_BASE to get the NAND
offset).
CONFIG_SPL_PAD_TO is for the placement of the payload
Correct.
-- and it's not a RAM address.
It doesn't have to be, but it may be for some configs.
Right. My point is it shouldn't be defined as a RAM address.
Currently it is a link address (or zero if the linker script handles padding, or padding is not required for other
reasons).
Correct.
With your patch it it is a file offset, IIUC.
With my patch, it is nothing at all since only CONFIG_SPL_MAX_SIZE is used.
Sorry, I just meant with your change to how objcopy is invoked. What you pass into objcopy is a file offset.
CONFIG_SPL_MAX_SIZE is what it says -- the maximum size that the SPL may be, ideally to be enforced by the linker script.
Correct.
They are different. An SPL wanting the payload to begin as a block boundary does not mean the hardware is suddenly capable of loading
an
entire block of SPL.
Sure, but my question is: Why would you want to have a 2-kiB SPL followed by a 126-kiB gap before the payload? Why couldn't you place the payload on the 1st page boundary after the SPL?
You can, and we usually do. But size-limited SPLs may want to simplify (e.g. bad block detection needs some special logic to handle beginning inside a block), and it may not always be 126 KiB.
E.g. MPC8313ERDB uses small-page NAND, so it's only 12KiB that gets wasted. It currently has MAX_SIZE of 4KiB but PAD_TO of base plus 16KiB.
If there are hardware constraints or something that make CONFIG_SPL_PAD_TO useful in some cases, then let's use it, but otherwise, why keep it?
It's easier to mainain orthogonality (and use defaults for simplicity) than to restore it after the fact if we need it later.
And if we keep it, do we change it to an image offset, or do we keep it as a link address?
Changing to an image offset sounds good.
Also, CONFIG_SPL_PAD_TO and CONFIG_SPL_MAX_SIZE depend on each
other:
If both can be defined, you may change one forgetting the other one, which could e.g. result in an overlapping of SPL and U-Boot that won't show up at build time (with CONFIG_SPL_MAX_SIZE = 0x1000 and CONFIG_SPL_PAD_TO = CONFIG_SPL_TEXT_BASE
- 0x800, the SPL would build fine, and objcopy wouldn't complain).
So add a check that CONFIG_SPL_PAD_TO >= CONFIG_SPL_MAX_SIZE
(assuming
the new interpretation of CONFIG_SPL_PAD_TO as a file offset), and
let
CONFIG_SPL_PAD_TO default to CONFIG_SPL_MAX_SIZE if not set.
That would make sense. The current default value of 0 for CONFIG_SPL_PAD_TO does not make sense since it means that the SPL can't know where the payload is located within the image.
CONFIG_SPL_PAD_TO is not the mechanism that is used for finding the payload. On mpc85xx it is unnecessary because the SPL will always be fixed size, because the reset vector goes at the end. It's also possible that some SPLs could use linker symbols to find the end of the SPL, if they want to pack more tightly.
Thanks for all the clarifications.
So I will make a v8 with CONFIG_SPL_PAD_TO as an image offset, and use it to generate u-boot-with-spl.bin. But first, I will wait for more feedback on v7 (Fabio should give his test results this week), and for Stefano to re-sync u-boot-imx/master with u-boot/master.
Best regards, Benoît
Hi Benoît,
On Mon, Feb 18, 2013 at 4:30 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
So I will make a v8 with CONFIG_SPL_PAD_TO as an image offset, and use it to generate u-boot-with-spl.bin. But first, I will wait for more feedback on v7 (Fabio should give his test results this week), and for Stefano to re-sync u-boot-imx/master with u-boot/master.
I didn't forget about the testing and it is on my todo list. I wasn't able to test it yet and hope to be able to do it soon.
Thanks,
Fabio Estevam
On Friday, February 22, 2013 6:36:45 PM, Fabio Estevam wrote:
Hi Benoît,
On Mon, Feb 18, 2013 at 4:30 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
So I will make a v8 with CONFIG_SPL_PAD_TO as an image offset, and use it to generate u-boot-with-spl.bin. But first, I will wait for more feedback on v7 (Fabio should give his test results this week), and for Stefano to re-sync u-boot-imx/master with u-boot/master.
I didn't forget about the testing and it is on my todo list. I wasn't able to test it yet and hope to be able to do it soon.
OK, thanks for the update.
Best regards, Benoît
On 02/17/2013 10:16:49 AM, Benoît Thébaudeau wrote:
Hi Poonam, Andy,
On Friday, February 15, 2013 9:54:19 PM, Benoît Thébaudeau wrote:
PAD_TO is not a generic SPL configuration option, so use
CONFIG_SPL_MAX_SIZE
instead.
We want to use --pad-to with a size, but this option expects an
address, so
use u-boot-spl.bin instead of u-boot-spl as the input file in order to
get
addresses starting at 0.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Changes in v7:
- Use u-boot-spl.bin instead of u-boot-spl in order to avoid
having to use
--change-addresses.
Changes in v6:
- Fix size passed to --pad-to thanks to --change-addresses.
Changes in v5: None Changes in v4:
- New patch.
Changes in v3: None Changes in v2: None
Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile index a8c7b7b..317dffc 100644 --- a/Makefile +++ b/Makefile @@ -486,7 +486,8 @@ $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin
$(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary$(obj)spl/u-boot-spl
$(obj)spl/u-boot-spl-pad.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_MAX_SIZE)\
-I binary -O binary $<$(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@ rm $(obj)spl/u-boot-spl-pad.binI would like to let you know what is going on, and to get your feedback for this patch.
include/configs/p1_p2_rdb_pc.h seems to be the only current user of u-boot-with-spl.bin, triggered for example by the P2020RDB-PC_NAND config.
Before this patch, PAD_TO was used, but there is no such definition for this board for generic SPL, so this board seems broken,
"--pad-to=" with no argument behaves the same as "--pad-to=0", though since it's undocumented we now avoid relying on that behavior as you observed in a followup post.
all the more none of the various values defined for CONFIG_SYS_TEXT_BASE relatively to CONFIG_SPL_TEXT_BASE would be compatible with an image built by appending U-Boot to the generic SPL. Can you confirm?
I don't follow. CONFIG_SYS_TEXT_BASE is for where the payload gets loaded to, and has nothing to do with its position in the SPL-concat image, nor with the address that the SPL starts running at.
-Scott
On Monday, February 18, 2013 8:37:29 PM, Scott Wood wrote:
On 02/17/2013 10:16:49 AM, Benoît Thébaudeau wrote:
Hi Poonam, Andy,
On Friday, February 15, 2013 9:54:19 PM, Benoît Thébaudeau wrote:
PAD_TO is not a generic SPL configuration option, so use
CONFIG_SPL_MAX_SIZE
instead.
We want to use --pad-to with a size, but this option expects an
address, so
use u-boot-spl.bin instead of u-boot-spl as the input file in order to
get
addresses starting at 0.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Changes in v7:
- Use u-boot-spl.bin instead of u-boot-spl in order to avoid
having to use
--change-addresses.
Changes in v6:
- Fix size passed to --pad-to thanks to --change-addresses.
Changes in v5: None Changes in v4:
- New patch.
Changes in v3: None Changes in v2: None
Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile index a8c7b7b..317dffc 100644 --- a/Makefile +++ b/Makefile @@ -486,7 +486,8 @@ $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin
$(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary$(obj)spl/u-boot-spl
$(obj)spl/u-boot-spl-pad.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_MAX_SIZE)\
-I binary -O binary $<$(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@ rm $(obj)spl/u-boot-spl-pad.binI would like to let you know what is going on, and to get your feedback for this patch.
include/configs/p1_p2_rdb_pc.h seems to be the only current user of u-boot-with-spl.bin, triggered for example by the P2020RDB-PC_NAND config.
Before this patch, PAD_TO was used, but there is no such definition for this board for generic SPL, so this board seems broken,
"--pad-to=" with no argument behaves the same as "--pad-to=0", though since it's undocumented we now avoid relying on that behavior as you observed in a followup post.
OK.
all the more none of the various values defined for CONFIG_SYS_TEXT_BASE relatively to CONFIG_SPL_TEXT_BASE would be compatible with an image built by appending U-Boot to the generic SPL. Can you confirm?
I don't follow. CONFIG_SYS_TEXT_BASE is for where the payload gets loaded to, and has nothing to do with its position in the SPL-concat image, nor with the address that the SPL starts running at.
Right, sorry, I meant CONFIG_SYS_NAND_U_BOOT_OFFS. It is 0, which is not compatible with the payload being appended to the SPL in the programmed image.
Best regards, Benoît
On 02/18/2013 01:52:10 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 8:37:29 PM, Scott Wood wrote:
On 02/17/2013 10:16:49 AM, Benoît Thébaudeau wrote:
Before this patch, PAD_TO was used, but there is no such
definition
for this board for generic SPL, so this board seems broken,
"--pad-to=" with no argument behaves the same as "--pad-to=0",
though
since it's undocumented we now avoid relying on that behavior as you observed in a followup post.
OK.
all the more none of the various values defined for CONFIG_SYS_TEXT_BASE relatively to CONFIG_SPL_TEXT_BASE would be compatible with an image built by appending U-Boot to the generic SPL. Can you confirm?
I don't follow. CONFIG_SYS_TEXT_BASE is for where the payload gets loaded to, and has nothing to do with its position in the SPL-concat image, nor with the address that the SPL starts running at.
Right, sorry, I meant CONFIG_SYS_NAND_U_BOOT_OFFS. It is 0, which is not compatible with the payload being appended to the SPL in the programmed image.
That just means we load the whole thing, including SPL, so that we're always loading from the start of the block. Note the difference between CONFIG_SYS_NAND_U_BOOT_DST and CONFIG_SYS_NAND_U_BOOT_START.
-Scott
On Monday, February 18, 2013 8:47:28 PM, Scott Wood wrote:
On 02/18/2013 01:52:10 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 8:37:29 PM, Scott Wood wrote:
On 02/17/2013 10:16:49 AM, Benoît Thébaudeau wrote:
Before this patch, PAD_TO was used, but there is no such
definition
for this board for generic SPL, so this board seems broken,
"--pad-to=" with no argument behaves the same as "--pad-to=0",
though
since it's undocumented we now avoid relying on that behavior as you observed in a followup post.
OK.
all the more none of the various values defined for CONFIG_SYS_TEXT_BASE relatively to CONFIG_SPL_TEXT_BASE would be compatible with an image built by appending U-Boot to the generic SPL. Can you confirm?
I don't follow. CONFIG_SYS_TEXT_BASE is for where the payload gets loaded to, and has nothing to do with its position in the SPL-concat image, nor with the address that the SPL starts running at.
Right, sorry, I meant CONFIG_SYS_NAND_U_BOOT_OFFS. It is 0, which is not compatible with the payload being appended to the SPL in the programmed image.
That just means we load the whole thing, including SPL, so that we're always loading from the start of the block. Note the difference between CONFIG_SYS_NAND_U_BOOT_DST and CONFIG_SYS_NAND_U_BOOT_START.
OK. Hmm, this difference is CONFIG_SPL_MAX_SIZE, but CONFIG_SPL_PAD_TO is not defined, so the payload is right after the SPL in the image and the SPL jumps to somewhere in the middle of the payload?
Best regards, Benoît
On 02/18/2013 02:01:59 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 8:47:28 PM, Scott Wood wrote:
On 02/18/2013 01:52:10 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 8:37:29 PM, Scott Wood wrote:
On 02/17/2013 10:16:49 AM, Benoît Thébaudeau wrote:
all the more none of the various values defined for CONFIG_SYS_TEXT_BASE relatively to CONFIG_SPL_TEXT_BASE would be compatible with an image built
by
appending U-Boot to the generic SPL. Can you confirm?
I don't follow. CONFIG_SYS_TEXT_BASE is for where the payload
gets
loaded to, and has nothing to do with its position in the
SPL-concat
image, nor with the address that the SPL starts running at.
Right, sorry, I meant CONFIG_SYS_NAND_U_BOOT_OFFS. It is 0, which
is
not compatible with the payload being appended to the SPL in the programmed image.
That just means we load the whole thing, including SPL, so that
we're
always loading from the start of the block. Note the difference between CONFIG_SYS_NAND_U_BOOT_DST and CONFIG_SYS_NAND_U_BOOT_START.
OK. Hmm, this difference is CONFIG_SPL_MAX_SIZE, but CONFIG_SPL_PAD_TO is not defined, so the payload is right after the SPL in the image and the SPL jumps to somewhere in the middle of the payload?
It jumps to the beginning of the payload. As mentioned elsewhere in the thread, mpc85xx NAND SPL is always fixed size (done in the linker script) because the reset vector comes at the end. Thus, max size equals actual size without needing --pad-to.
-Scott
On Monday, February 18, 2013 9:06:30 PM, Scott Wood wrote:
On 02/18/2013 02:01:59 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 8:47:28 PM, Scott Wood wrote:
On 02/18/2013 01:52:10 PM, Benoît Thébaudeau wrote:
On Monday, February 18, 2013 8:37:29 PM, Scott Wood wrote:
On 02/17/2013 10:16:49 AM, Benoît Thébaudeau wrote:
all the more none of the various values defined for CONFIG_SYS_TEXT_BASE relatively to CONFIG_SPL_TEXT_BASE would be compatible with an image built
by
appending U-Boot to the generic SPL. Can you confirm?
I don't follow. CONFIG_SYS_TEXT_BASE is for where the payload
gets
loaded to, and has nothing to do with its position in the
SPL-concat
image, nor with the address that the SPL starts running at.
Right, sorry, I meant CONFIG_SYS_NAND_U_BOOT_OFFS. It is 0, which
is
not compatible with the payload being appended to the SPL in the programmed image.
That just means we load the whole thing, including SPL, so that
we're
always loading from the start of the block. Note the difference between CONFIG_SYS_NAND_U_BOOT_DST and CONFIG_SYS_NAND_U_BOOT_START.
OK. Hmm, this difference is CONFIG_SPL_MAX_SIZE, but CONFIG_SPL_PAD_TO is not defined, so the payload is right after the SPL in the image and the SPL jumps to somewhere in the middle of the payload?
It jumps to the beginning of the payload. As mentioned elsewhere in the thread, mpc85xx NAND SPL is always fixed size (done in the linker script) because the reset vector comes at the end. Thus, max size equals actual size without needing --pad-to.
OK, clear.
Benoît
Automatically build the 'u-boot.imx' (i.e. imx header + u-boot.bin) and 'SPL' (i.e. imx header + u-boot-spl.bin) make targets for all imx processors supporting this header, so for arm926ejs, arm1136 and armv7. Some combinations were missing.
At the same time, fix the build of SPL targets not supporting the imx header on arm1136. For arm1136, the 'SPL' make target was forced to build in all cases if CONFIG_SPL_BUILD was defined, even for non-imx platforms or imx setups without an imx header.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: - New patch, extracted from "nand: mxc: Switch NAND SPL to generic SPL".
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm1136/config.mk | 7 +++++++ arch/arm/cpu/arm926ejs/config.mk | 8 ++++++-- arch/arm/cpu/armv7/config.mk | 6 ++++++ 3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk index 9092d91..797d122 100644 --- a/arch/arm/cpu/arm1136/config.mk +++ b/arch/arm/cpu/arm1136/config.mk @@ -31,6 +31,13 @@ PLATFORM_CPPFLAGS += -march=armv5 # ========================================================================= PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) + +ifneq ($(CONFIG_IMX_CONFIG),) +ifdef CONFIG_SPL ifdef CONFIG_SPL_BUILD ALL-y += $(OBJTREE)/SPL endif +else +ALL-y += $(obj)u-boot.imx +endif +endif diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index 6a3a1bb..f0e31d1 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -33,7 +33,11 @@ PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-mali PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),) - +ifdef CONFIG_SPL +ifdef CONFIG_SPL_BUILD +ALL-y += $(OBJTREE)/SPL +endif +else ALL-y += $(obj)u-boot.imx - +endif endif diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index 9c3e2f3..56b8053 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -40,5 +40,11 @@ PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,) PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
ifneq ($(CONFIG_IMX_CONFIG),) +ifdef CONFIG_SPL +ifdef CONFIG_SPL_BUILD +ALL-y += $(OBJTREE)/SPL +endif +else ALL-y += $(obj)u-boot.imx endif +endif
This also fixes support for mx31pdk and tx25, which had been broken by commit e05e5de7fae5bec79617e113916dac6631251156.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: - Automate 'u-boot.imx' and 'SPL' make targets for all imx processors. - Move board_init_f() to <board>.c. - Get rid of board SPL linker scripts. - Define CONFIG_SYS_NAND_U_BOOT_OFFS as CONFIG_SPL_MAX_SIZE rather than duplicating the constant value. - Define CONFIG_SYS_NAND_U_BOOT_DST as CONFIG_SYS_TEXT_BASE rather than duplicating the constant value. - Pass 0 as the 1st argument to relocate_code() since it's unused. - Fix stack pointers. - Rebase on latest u-boot-imx/master. - Move unrelated changes to separate patches.
Changes in v5: - Remove spaces between function name and open parenthesis. - Fix mx31pdk and tx25 Makefile-s and SPL linker scripts. - Remove the useless definition of CONFIG_SPL_LDSCRIPT. - Fix the call to nand_boot().
Changes in v4: - New patch.
Changes in v3: None Changes in v2: None
arch/arm/cpu/arm926ejs/start.S | 3 +- board/freescale/mx31pdk/Makefile | 3 + board/freescale/mx31pdk/config.mk | 5 -- board/freescale/mx31pdk/mx31pdk.c | 8 ++ board/karo/tx25/Makefile | 4 +- board/karo/tx25/config.mk | 5 -- board/karo/tx25/tx25.c | 8 ++ boards.cfg | 2 +- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/mxc_nand.c | 10 +-- include/fsl_nfc.h => drivers/mtd/nand/mxc_nand.h | 10 +-- .../mtd/nand/mxc_nand_spl.c | 26 ++---- include/configs/mx31pdk.h | 17 +++- include/configs/tx25.h | 22 +++-- nand_spl/board/freescale/mx31pdk/Makefile | 68 --------------- nand_spl/board/freescale/mx31pdk/u-boot.lds | 87 ------------------- nand_spl/board/karo/tx25/Makefile | 89 -------------------- nand_spl/board/karo/tx25/config.mk | 1 - nand_spl/board/karo/tx25/u-boot.lds | 87 ------------------- 19 files changed, 72 insertions(+), 384 deletions(-) delete mode 100644 board/freescale/mx31pdk/config.mk delete mode 100644 board/karo/tx25/config.mk rename include/fsl_nfc.h => drivers/mtd/nand/mxc_nand.h (98%) rename nand_spl/nand_boot_fsl_nfc.c => drivers/mtd/nand/mxc_nand_spl.c (92%) delete mode 100644 nand_spl/board/freescale/mx31pdk/Makefile delete mode 100644 nand_spl/board/freescale/mx31pdk/u-boot.lds delete mode 100644 nand_spl/board/karo/tx25/Makefile delete mode 100644 nand_spl/board/karo/tx25/config.mk delete mode 100644 nand_spl/board/karo/tx25/u-boot.lds
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 70551ec..1db1152 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -200,7 +200,6 @@ reset:
/*------------------------------------------------------------------------------*/
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL) /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -272,6 +271,8 @@ relocate_done:
bx lr
+#ifndef CONFIG_SPL_BUILD + _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: diff --git a/board/freescale/mx31pdk/Makefile b/board/freescale/mx31pdk/Makefile index 5b7cafd..b910722 100644 --- a/board/freescale/mx31pdk/Makefile +++ b/board/freescale/mx31pdk/Makefile @@ -27,6 +27,9 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
+ifdef CONFIG_SPL_BUILD +SOBJS := lowlevel_init.o +endif COBJS := mx31pdk.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/freescale/mx31pdk/config.mk b/board/freescale/mx31pdk/config.mk deleted file mode 100644 index de2c642..0000000 --- a/board/freescale/mx31pdk/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -ifdef CONFIG_NAND_SPL -CONFIG_SYS_TEXT_BASE = 0x87ec0000 -else -CONFIG_SYS_TEXT_BASE = 0x87f00000 -endif diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 895396c..df5d407 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -36,6 +36,14 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong bootflag) +{ + relocate_code(0, NULL, CONFIG_SPL_TEXT_BASE); + asm volatile("ldr pc, =nand_boot\n"); +} +#endif + int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ diff --git a/board/karo/tx25/Makefile b/board/karo/tx25/Makefile index 9617fa5..c26bf36 100644 --- a/board/karo/tx25/Makefile +++ b/board/karo/tx25/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-COBJS := tx25.o +ifdef CONFIG_SPL_BUILD SOBJS := lowlevel_init.o +endif +COBJS := tx25.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/karo/tx25/config.mk b/board/karo/tx25/config.mk deleted file mode 100644 index 18b2883..0000000 --- a/board/karo/tx25/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -ifdef CONFIG_NAND_SPL -CONFIG_SYS_TEXT_BASE = 0x810c0000 -else -CONFIG_SYS_TEXT_BASE = 0x81200000 -endif diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 362f00a..6058fbf 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -33,6 +33,14 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong bootflag) +{ + relocate_code(0, NULL, CONFIG_SPL_TEXT_BASE); + asm volatile("ldr pc, =nand_boot\n"); +} +#endif + #ifdef CONFIG_FEC_MXC #define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7) #define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9) diff --git a/boards.cfg b/boards.cfg index 7d03620..2649c88 100644 --- a/boards.cfg +++ b/boards.cfg @@ -45,7 +45,7 @@ imx31_phycore arm arm1136 - - imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET qong arm arm1136 - davedenx mx31 mx31ads arm arm1136 - freescale mx31 -mx31pdk arm arm1136 - freescale mx31 mx31pdk:NAND_U_BOOT +mx31pdk arm arm1136 - freescale mx31 tt01 arm arm1136 - hale mx31 imx31_litekit arm arm1136 - logicpd mx31 flea3 arm arm1136 - CarMediaLab mx35 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index c77c0c4..bcb7161 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -82,6 +82,7 @@ COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o else # minimal SPL drivers
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o +COBJS-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
endif # drivers endif # nand diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 001c2c0..159e3b4 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -26,7 +26,7 @@ defined(CONFIG_MX51) || defined(CONFIG_MX53) #include <asm/arch/imx-regs.h> #endif -#include <fsl_nfc.h> +#include "mxc_nand.h"
#define DRIVER_NAME "mxc_nand"
@@ -36,9 +36,9 @@ struct mxc_nand_host { struct mtd_info mtd; struct nand_chip *nand;
- struct fsl_nfc_regs __iomem *regs; + struct mxc_nand_regs __iomem *regs; #ifdef MXC_NFC_V3_2 - struct fsl_nfc_ip_regs __iomem *ip_regs; + struct mxc_nand_ip_regs __iomem *ip_regs; #endif int spare_only; int status_request; @@ -1254,10 +1254,10 @@ int board_nand_init(struct nand_chip *this) this->read_buf = mxc_nand_read_buf; this->verify_buf = mxc_nand_verify_buf;
- host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; + host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; #ifdef MXC_NFC_V3_2 host->ip_regs = - (struct fsl_nfc_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE; + (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE; #endif host->clk_act = 1;
diff --git a/include/fsl_nfc.h b/drivers/mtd/nand/mxc_nand.h similarity index 98% rename from include/fsl_nfc.h rename to drivers/mtd/nand/mxc_nand.h index 48a6448..308ff8d 100644 --- a/include/fsl_nfc.h +++ b/drivers/mtd/nand/mxc_nand.h @@ -20,8 +20,8 @@ * MA 02111-1307 USA */
-#ifndef __FSL_NFC_H -#define __FSL_NFC_H +#ifndef __MXC_NAND_H +#define __MXC_NAND_H
/* * Register map and bit definitions for the Freescale NAND Flash Controller @@ -73,7 +73,7 @@ #define NAND_MXC_REG_OFFSET 0x1e00 #endif
-struct fsl_nfc_regs { +struct mxc_nand_regs { u8 main_area[NAND_MXC_NR_BUFS][0x200]; u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE]; /* @@ -131,7 +131,7 @@ struct fsl_nfc_regs { };
#ifdef MXC_NFC_V3_2 -struct fsl_nfc_ip_regs { +struct mxc_nand_ip_regs { u32 wrprot; u32 wrprot_unlock_blkaddr[8]; u32 config2; @@ -222,4 +222,4 @@ struct fsl_nfc_ip_regs { #define writenfc writel #endif
-#endif /* __FSL_NFC_H */ +#endif /* __MXC_NAND_H */ diff --git a/nand_spl/nand_boot_fsl_nfc.c b/drivers/mtd/nand/mxc_nand_spl.c similarity index 92% rename from nand_spl/nand_boot_fsl_nfc.c rename to drivers/mtd/nand/mxc_nand_spl.c index 1096727..09f23c3 100644 --- a/nand_spl/nand_boot_fsl_nfc.c +++ b/drivers/mtd/nand/mxc_nand_spl.c @@ -28,13 +28,13 @@ #include <nand.h> #include <asm/arch/imx-regs.h> #include <asm/io.h> -#include <fsl_nfc.h> +#include "mxc_nand.h"
#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) -static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR; +static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR; #elif defined(MXC_NFC_V3_2) -static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR_AXI; -static struct fsl_nfc_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR; +static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR_AXI; +static struct mxc_nand_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR; #endif
static void nfc_wait_ready(void) @@ -68,7 +68,7 @@ static void nfc_nand_init(void)
tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK | NFC_V3_CONFIG2_PS_MASK)) | - NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_SPARE_SIZE / 2) | + NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_OOBSIZE / 2) | NFC_V3_CONFIG2_INT_MSK | NFC_V3_CONFIG2_ECC_EN | NFC_V3_CONFIG2_ONE_CYCLE; if (CONFIG_SYS_NAND_PAGE_SIZE == 4096) @@ -81,7 +81,7 @@ static void nfc_nand_init(void) * if spare size is larger that 16 bytes per 512 byte hunk * then use 8 symbol correction instead of 4 */ - if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16) + if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16) tmp |= NFC_V3_CONFIG2_ECC_MODE_8; else tmp &= ~NFC_V3_CONFIG2_ECC_MODE_8; @@ -102,7 +102,7 @@ static void nfc_nand_init(void) int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; int config1;
- writenfc(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size); + writenfc(CONFIG_SYS_NAND_OOBSIZE / 2, &nfc->spare_area_size);
/* unlocking RAM Buff */ writenfc(0x2, &nfc->config); @@ -115,7 +115,7 @@ static void nfc_nand_init(void) * if spare size is larger that 16 bytes per 512 byte hunk * then use 8 symbol correction instead of 4 */ - if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16) + if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16) config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4; else config1 |= NFC_V2_CONFIG1_ECC_MODE_4; @@ -204,7 +204,7 @@ static int nfc_nand_check_ecc(void) #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) u32 ecc_status = readl(&nfc->ecc_status_result); int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; - int err_limit = CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16 ? 8 : 4; + int err_limit = CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16 ? 8 : 4; int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512;
do { @@ -332,14 +332,6 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) return 0; }
-#if defined(CONFIG_ARM) -void board_init_f (ulong bootflag) -{ - relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, - CONFIG_SYS_TEXT_BASE); -} -#endif - /* * The main entry for NAND booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 34e4295..d80a43e 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -45,7 +45,16 @@
#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SPL +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot.lds" +#define CONFIG_SPL_MAX_SIZE 2048 +#define CONFIG_SPL_NAND_SUPPORT + +#define CONFIG_SPL_TEXT_BASE 0x87ec0000 +#define CONFIG_SYS_TEXT_BASE 0x87f00000 + +#ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT #endif
@@ -163,7 +172,7 @@ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) + CONFIG_SYS_INIT_RAM_SIZE)
/*----------------------------------------------------------------------- * FLASH and environment organization @@ -189,10 +198,10 @@ /* NAND configuration for the NAND_SPL */
/* Start copying real U-boot from the second page */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_MAX_SIZE #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 /* Load U-Boot to this address */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 diff --git a/include/configs/tx25.h b/include/configs/tx25.h index 80194d8..df69beb 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -21,6 +21,7 @@ #ifndef __CONFIG_H #define __CONFIG_H
+#include <asm/arch/imx-regs.h>
/* * KARO TX25 board - SoC Configuration @@ -31,8 +32,14 @@
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
-/* NAND BOOT is the only boot method */ -#define CONFIG_NAND_U_BOOT +#define CONFIG_SPL +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot.lds" +#define CONFIG_SPL_MAX_SIZE 2048 +#define CONFIG_SPL_NAND_SUPPORT + +#define CONFIG_SPL_TEXT_BASE 0x810c0000 +#define CONFIG_SYS_TEXT_BASE 0x81200000
#ifndef MACH_TYPE_TX25 #define MACH_TYPE_TX25 2177 @@ -40,16 +47,16 @@
#define CONFIG_MACH_TYPE MACH_TYPE_TX25
-#ifdef CONFIG_NAND_SPL +#ifdef CONFIG_SPL_BUILD /* Start copying real U-boot from the second page */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_MAX_SIZE #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x81200000) +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_SPARE_SIZE 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024) @@ -173,7 +180,6 @@
/* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (IMX_RAM_BASE + IMX_RAM_SIZE)
#endif /* __CONFIG_H */ diff --git a/nand_spl/board/freescale/mx31pdk/Makefile b/nand_spl/board/freescale/mx31pdk/Makefile deleted file mode 100644 index fd0dfc1..0000000 --- a/nand_spl/board/freescale/mx31pdk/Makefile +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_NAND_SPL = y -PAD_TO := 2048 - -include $(TOPDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL - -SOBJS = start.o crt0.o lowlevel_init.o -COBJS = nand_boot_fsl_nfc.o - -SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c -SRCS += $(SRCTREE)/arch/arm/cpu/arm1136/start.S -SRCS += $(SRCTREE)/arch/arm/lib/crt0.S -SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $@ - -# The following line expands into whole rule which generates $(LSTSCRIPT), -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) -$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ - -ansi -D__ASSEMBLY__ -P - <$< >$@ - -######################################################################### - -$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm1136/%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/nand_spl/%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/freescale/mx31pdk/u-boot.lds b/nand_spl/board/freescale/mx31pdk/u-boot.lds deleted file mode 100644 index a26110f..0000000 --- a/nand_spl/board/freescale/mx31pdk/u-boot.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2009 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - start.o (.text) - lowlevel_init.o (.text) - nand_boot_fsl_nfc.o (.text) - *(.text) - . = 2K; - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = ALIGN(4); - .u_boot_list : { - #include <u-boot.lst> - } - - . = ALIGN(4); - - __image_copy_end = .; - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.bss*) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/nand_spl/board/karo/tx25/Makefile b/nand_spl/board/karo/tx25/Makefile deleted file mode 100644 index 82489d2..0000000 --- a/nand_spl/board/karo/tx25/Makefile +++ /dev/null @@ -1,89 +0,0 @@ -# -# (C) Copyright 2009 DENX Software Engineering -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundatio; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -CONFIG_NAND_SPL = y - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL - -SOBJS = start.o crt0.o lowlevel_init.o -COBJS = nand_boot_fsl_nfc.o - -SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c -SRCS += $(SRCTREE)/arch/arm/cpu/arm926ejs/start.S -SRCS += $(SRCTREE)/arch/arm/lib/crt0.S -SRCS += $(SRCTREE)/board/karo/tx25/lowlevel_init.S -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $@ - -# The following line expands into whole rule which generates $(LSTSCRIPT), -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) -$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ - -ansi -D__ASSEMBLY__ -P - <$< >$@ - -######################################################################### - -$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm926ejs/%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/board/karo/tx25/%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/nand_spl/%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/karo/tx25/config.mk b/nand_spl/board/karo/tx25/config.mk deleted file mode 100644 index 68afbf1..0000000 --- a/nand_spl/board/karo/tx25/config.mk +++ /dev/null @@ -1 +0,0 @@ -PAD_TO := 2048 diff --git a/nand_spl/board/karo/tx25/u-boot.lds b/nand_spl/board/karo/tx25/u-boot.lds deleted file mode 100644 index 95ea8ac..0000000 --- a/nand_spl/board/karo/tx25/u-boot.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2009 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - start.o (.text) - lowlevel_init.o (.text) - nand_boot_fsl_nfc.o (.text) - *(.text) - . = 2K; - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = ALIGN(4); - .u_boot_list : { - #include <u-boot.lst> - } - - . = ALIGN(4); - - __image_copy_end = .; - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.bss*) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -}
Hi Benoît,
On Fri, Feb 15, 2013 at 6:54 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
This also fixes support for mx31pdk and tx25, which had been broken by commit e05e5de7fae5bec79617e113916dac6631251156.
Just tested your patch series on a mx31pdk, but unfortunately it does not fix mx31pdk boot.
I will start looking at it, but any suggestion is welcome.
Regards,
Fabio Estevam
On Fri, Feb 22, 2013 at 4:14 PM, Fabio Estevam festevam@gmail.com wrote:
Just tested your patch series on a mx31pdk, but unfortunately it does not fix mx31pdk boot.
I will start looking at it, but any suggestion is welcome.
Ok, just changed to a proper toolchain and the result is a bit better now:
U-Boot 2013.01 (Feb 22 2013 - 16:25:48)
CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK DRAM: 128 MiB
(hangs here).
Hi Fabio,
On Friday, February 22, 2013 8:30:36 PM, Fabio Estevam wrote:
On Fri, Feb 22, 2013 at 4:14 PM, Fabio Estevam festevam@gmail.com wrote:
Just tested your patch series on a mx31pdk, but unfortunately it does not fix mx31pdk boot.
I will start looking at it, but any suggestion is welcome.
Ok, just changed to a proper toolchain and the result is a bit better now:
U-Boot 2013.01 (Feb 22 2013 - 16:25:48)
CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK DRAM: 128 MiB
(hangs here).
It looks very much like the issue that Marek had on i.MX53 (which self-resolved for an unknown reason).
Try to enable the debug trace to see if anything else is printed after display_dram_config(). I would especially be interested in: debug("relocation Offset is: %08lx\n", gd->reloc_off); debug("monitor flash len: %08lX\n", monitor_flash_len);
We should also check if CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE don't overlap with something depending on code size. That's especially true for CONFIG_SYS_TEXT_BASE.
After that, JTAG if no clue left... ;(
Best regards, Benoît
On 2/22/2013 1:09 PM, Benoît Thébaudeau wrote:
Hi Fabio,
On Friday, February 22, 2013 8:30:36 PM, Fabio Estevam wrote:
On Fri, Feb 22, 2013 at 4:14 PM, Fabio Estevam festevam@gmail.com wrote:
Just tested your patch series on a mx31pdk, but unfortunately it does not fix mx31pdk boot.
I will start looking at it, but any suggestion is welcome.
Ok, just changed to a proper toolchain and the result is a bit better now:
U-Boot 2013.01 (Feb 22 2013 - 16:25:48)
CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK DRAM: 128 MiB
(hangs here).
It looks very much like the issue that Marek had on i.MX53 (which self-resolved for an unknown reason).
Try to enable the debug trace to see if anything else is printed after display_dram_config(). I would especially be interested in: debug("relocation Offset is: %08lx\n", gd->reloc_off); debug("monitor flash len: %08lX\n", monitor_flash_len);
We should also check if CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE don't overlap with something depending on code size. That's especially true for CONFIG_SYS_TEXT_BASE.
After that, JTAG if no clue left... ;(
Best regards, Benoît
It does look familiar, can you try changing imximage.c
*header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 512);
to
*header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 4096);
(or whatever your nand sector size is) and see if it makes a difference?
Hi Troy,
On Fri, Feb 22, 2013 at 5:55 PM, Troy Kisky troy.kisky@boundarydevices.com wrote:
It does look familiar, can you try changing imximage.c
*header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 512);
to
*header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 4096);
(or whatever your nand sector size is) and see if it makes a difference?
Thanks for the suggestion, but mx31 does not run imximage tool.
Dear Troy Kisky,
On 2/22/2013 1:09 PM, Benoît Thébaudeau wrote:
Hi Fabio,
On Friday, February 22, 2013 8:30:36 PM, Fabio Estevam wrote:
On Fri, Feb 22, 2013 at 4:14 PM, Fabio Estevam festevam@gmail.com wrote:
Just tested your patch series on a mx31pdk, but unfortunately it does not fix mx31pdk boot.
I will start looking at it, but any suggestion is welcome.
Ok, just changed to a proper toolchain and the result is a bit better now:
U-Boot 2013.01 (Feb 22 2013 - 16:25:48)
CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK DRAM: 128 MiB
(hangs here).
It looks very much like the issue that Marek had on i.MX53 (which self-resolved for an unknown reason).
Try to enable the debug trace to see if anything else is printed after
display_dram_config(). I would especially be interested in: debug("relocation Offset is: %08lx\n", gd->reloc_off); debug("monitor flash len: %08lX\n", monitor_flash_len);
We should also check if CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE don't overlap with something depending on code size. That's especially true for CONFIG_SYS_TEXT_BASE.
After that, JTAG if no clue left... ;(
Best regards, Benoît
It does look familiar, can you try changing imximage.c
*header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 512);
to
*header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 4096);
(or whatever your nand sector size is) and see if it makes a difference?
This patch is needed for NAND boot on mx53. I still dont have the patches quite ready, but we can omit SPL on mx53 ;-)
Best regards, Marek Vasut
Hi Benoît,
On Fri, Feb 22, 2013 at 5:09 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
It looks very much like the issue that Marek had on i.MX53 (which self-resolved for an unknown reason).
Try to enable the debug trace to see if anything else is printed after display_dram_config(). I would especially be interested in: debug("relocation Offset is: %08lx\n", gd->reloc_off); debug("monitor flash len: %08lX\n", monitor_flash_len);
Here is the output:
U-Boot 2013.01 (Feb 22 2013 - 18:00:50)
U-Boot code: 87F00000 -> 87F2C184 BSS: -> 87F311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 000be000
Hi Fabio,
On Friday, February 22, 2013 10:06:42 PM, Fabio Estevam wrote:
Hi Benoît,
On Fri, Feb 22, 2013 at 5:09 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
It looks very much like the issue that Marek had on i.MX53 (which self-resolved for an unknown reason).
Try to enable the debug trace to see if anything else is printed after display_dram_config(). I would especially be interested in: debug("relocation Offset is: %08lx\n", gd->reloc_off); debug("monitor flash len: %08lX\n", monitor_flash_len);
Here is the output:
U-Boot 2013.01 (Feb 22 2013 - 18:00:50)
U-Boot code: 87F00000 -> 87F2C184 BSS: -> 87F311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 000be000
CONFIG_SYS_TEXT_BASE seems fine according to this trace. But anyway, can you test with this change in mx31pdk.h? #define CONFIG_SPL_TEXT_BASE 0x84000000 #define CONFIG_SYS_TEXT_BASE 0x83000000
Can you try to revert 10/19, only for arm1136/start.S (1 line to restore)? There is an issue in this patch that I have already fixed in my v8.
Best regards, Benoît
On Fri, Feb 22, 2013 at 6:13 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
CONFIG_SYS_TEXT_BASE seems fine according to this trace. But anyway, can you test with this change in mx31pdk.h? #define CONFIG_SPL_TEXT_BASE 0x84000000 #define CONFIG_SYS_TEXT_BASE 0x83000000
Can you try to revert 10/19, only for arm1136/start.S (1 line to restore)? There is an issue in this patch that I have already fixed in my v8.
Just tried with the above changes:
U-Boot code: 83000000 -> 8302C184 BSS: -> 830311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 04fbe000
Hi Fabio,
On Friday, February 22, 2013 10:26:47 PM, Fabio Estevam wrote:
On Fri, Feb 22, 2013 at 6:13 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
CONFIG_SYS_TEXT_BASE seems fine according to this trace. But anyway, can you test with this change in mx31pdk.h? #define CONFIG_SPL_TEXT_BASE 0x84000000 #define CONFIG_SYS_TEXT_BASE 0x83000000
Can you try to revert 10/19, only for arm1136/start.S (1 line to restore)? There is an issue in this patch that I have already fixed in my v8.
Just tried with the above changes:
U-Boot code: 83000000 -> 8302C184 BSS: -> 830311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 04fbe000
I have no other clue for now. Can you try asm step by step in relocate_code()? :(
Best regards, Benoît
On 2/22/2013 2:13 PM, Benoît Thébaudeau wrote:
Hi Fabio,
On Friday, February 22, 2013 10:06:42 PM, Fabio Estevam wrote:
Hi Benoît,
On Fri, Feb 22, 2013 at 5:09 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
It looks very much like the issue that Marek had on i.MX53 (which self-resolved for an unknown reason).
Try to enable the debug trace to see if anything else is printed after display_dram_config(). I would especially be interested in: debug("relocation Offset is: %08lx\n", gd->reloc_off); debug("monitor flash len: %08lX\n", monitor_flash_len);
Here is the output:
U-Boot 2013.01 (Feb 22 2013 - 18:00:50)
U-Boot code: 87F00000 -> 87F2C184 BSS: -> 87F311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 000be000
CONFIG_SYS_TEXT_BASE seems fine according to this trace. But anyway, can you test with this change in mx31pdk.h? #define CONFIG_SPL_TEXT_BASE 0x84000000 #define CONFIG_SYS_TEXT_BASE 0x83000000
Can you try to revert 10/19, only for arm1136/start.S (1 line to restore)? There is an issue in this patch that I have already fixed in my v8.
Best regards, Benoît _______________________________________________
How about changing
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x32000
is see monitor len: 311B4 above is over 0x30000
Please excuse me if they are unrelated.
Troy
Hi Troy,
On Friday, February 22, 2013 10:30:21 PM, Troy Kisky wrote:
On 2/22/2013 2:13 PM, Benoît Thébaudeau wrote:
Hi Fabio,
On Friday, February 22, 2013 10:06:42 PM, Fabio Estevam wrote:
Hi Benoît,
On Fri, Feb 22, 2013 at 5:09 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
It looks very much like the issue that Marek had on i.MX53 (which self-resolved for an unknown reason).
Try to enable the debug trace to see if anything else is printed after display_dram_config(). I would especially be interested in: debug("relocation Offset is: %08lx\n", gd->reloc_off); debug("monitor flash len: %08lX\n", monitor_flash_len);
Here is the output:
U-Boot 2013.01 (Feb 22 2013 - 18:00:50)
U-Boot code: 87F00000 -> 87F2C184 BSS: -> 87F311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 000be000
CONFIG_SYS_TEXT_BASE seems fine according to this trace. But anyway, can you test with this change in mx31pdk.h? #define CONFIG_SPL_TEXT_BASE 0x84000000 #define CONFIG_SYS_TEXT_BASE 0x83000000
Can you try to revert 10/19, only for arm1136/start.S (1 line to restore)? There is an issue in this patch that I have already fixed in my v8.
Best regards, Benoît _______________________________________________
How about changing
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x32000
is see monitor len: 311B4 above is over 0x30000
Please excuse me if they are unrelated.
That could be it. Thanks! Fabio, please try.
Best regards, Benoît
On Friday, February 22, 2013 10:27:57 PM, Benoît Thébaudeau wrote:
Hi Troy,
On Friday, February 22, 2013 10:30:21 PM, Troy Kisky wrote:
On 2/22/2013 2:13 PM, Benoît Thébaudeau wrote:
Hi Fabio,
On Friday, February 22, 2013 10:06:42 PM, Fabio Estevam wrote:
Hi Benoît,
On Fri, Feb 22, 2013 at 5:09 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
It looks very much like the issue that Marek had on i.MX53 (which self-resolved for an unknown reason).
Try to enable the debug trace to see if anything else is printed after display_dram_config(). I would especially be interested in: debug("relocation Offset is: %08lx\n", gd->reloc_off); debug("monitor flash len: %08lX\n", monitor_flash_len);
Here is the output:
U-Boot 2013.01 (Feb 22 2013 - 18:00:50)
U-Boot code: 87F00000 -> 87F2C184 BSS: -> 87F311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 000be000
CONFIG_SYS_TEXT_BASE seems fine according to this trace. But anyway, can you test with this change in mx31pdk.h? #define CONFIG_SPL_TEXT_BASE 0x84000000 #define CONFIG_SYS_TEXT_BASE 0x83000000
Can you try to revert 10/19, only for arm1136/start.S (1 line to restore)? There is an issue in this patch that I have already fixed in my v8.
Best regards, Benoît _______________________________________________
How about changing
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x32000
is see monitor len: 311B4 above is over 0x30000
Please excuse me if they are unrelated.
That could be it. Thanks! Fabio, please try.
But Fabio, how have you been able to program u-boot-with-spl.bin if it overlaps the next MTD partition, unless you destroyed what follows or CONFIG_SYS_NAND_U_BOOT_SIZE does not match your NAND images layout?
Best regards, Benoît
On Friday, February 22, 2013 10:31:13 PM, Benoît Thébaudeau wrote:
On Friday, February 22, 2013 10:27:57 PM, Benoît Thébaudeau wrote:
Hi Troy,
On Friday, February 22, 2013 10:30:21 PM, Troy Kisky wrote:
On 2/22/2013 2:13 PM, Benoît Thébaudeau wrote:
Hi Fabio,
On Friday, February 22, 2013 10:06:42 PM, Fabio Estevam wrote:
Hi Benoît,
On Fri, Feb 22, 2013 at 5:09 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
It looks very much like the issue that Marek had on i.MX53 (which self-resolved for an unknown reason).
Try to enable the debug trace to see if anything else is printed after display_dram_config(). I would especially be interested in: debug("relocation Offset is: %08lx\n", gd->reloc_off); debug("monitor flash len: %08lX\n", monitor_flash_len);
Here is the output:
U-Boot 2013.01 (Feb 22 2013 - 18:00:50)
U-Boot code: 87F00000 -> 87F2C184 BSS: -> 87F311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 000be000
CONFIG_SYS_TEXT_BASE seems fine according to this trace. But anyway, can you test with this change in mx31pdk.h? #define CONFIG_SPL_TEXT_BASE 0x84000000 #define CONFIG_SYS_TEXT_BASE 0x83000000
Can you try to revert 10/19, only for arm1136/start.S (1 line to restore)? There is an issue in this patch that I have already fixed in my v8.
Best regards, Benoît _______________________________________________
How about changing
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x32000
is see monitor len: 311B4 above is over 0x30000
Please excuse me if they are unrelated.
That could be it. Thanks! Fabio, please try.
But Fabio, how have you been able to program u-boot-with-spl.bin if it overlaps the next MTD partition, unless you destroyed what follows or CONFIG_SYS_NAND_U_BOOT_SIZE does not match your NAND images layout?
u-boot.bin is also a little bit larger than 0x30000 with my compiler, so there is definitely an issue with CONFIG_SYS_NAND_U_BOOT_SIZE. If it really has to fit in 0x30000 in your NAND, then try -ffunction-section, -fdata-sections and -Wl,--gc-sections in the board config.mk.
Best regards, Benoît
On Fri, Feb 22, 2013 at 6:31 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
But Fabio, how have you been able to program u-boot-with-spl.bin if it overlaps the next MTD partition, unless you destroyed what follows or CONFIG_SYS_NAND_U_BOOT_SIZE does not match your NAND images layout?
Yes, I program u-boot-with-spl.bin into offset 0 of NAND flash and I have no other MTD partition currently on my NAND.
Thanks,
Fabio Estevam
On Fri, Feb 22, 2013 at 6:30 PM, Troy Kisky troy.kisky@boundarydevices.com wrote:
On 2/22/2013 2:13 PM, Benoît Thébaudeau wrote:
Hi Fabio,
On Friday, February 22, 2013 10:06:42 PM, Fabio Estevam wrote:
Hi Benoît,
On Fri, Feb 22, 2013 at 5:09 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
It looks very much like the issue that Marek had on i.MX53 (which self-resolved for an unknown reason).
Try to enable the debug trace to see if anything else is printed after display_dram_config(). I would especially be interested in: debug("relocation Offset is: %08lx\n", gd->reloc_off); debug("monitor flash len: %08lX\n", monitor_flash_len);
Here is the output:
U-Boot 2013.01 (Feb 22 2013 - 18:00:50)
U-Boot code: 87F00000 -> 87F2C184 BSS: -> 87F311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 000be000
CONFIG_SYS_TEXT_BASE seems fine according to this trace. But anyway, can you test with this change in mx31pdk.h? #define CONFIG_SPL_TEXT_BASE 0x84000000 #define CONFIG_SYS_TEXT_BASE 0x83000000
Can you try to revert 10/19, only for arm1136/start.S (1 line to restore)? There is an issue in this patch that I have already fixed in my v8.
Best regards, Benoît _______________________________________________
How about changing
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x32000
is see monitor len: 311B4 above is over 0x30000
Thanks, Troy. When I tried increasing from 0x30000 it did not boot anymore. Still checking.
Thanks!
On Fri, Feb 22, 2013 at 6:51 PM, Fabio Estevam festevam@gmail.com wrote:
On Fri, Feb 22, 2013 at 6:30 PM, Troy Kisky troy.kisky@boundarydevices.com wrote:
On 2/22/2013 2:13 PM, Benoît Thébaudeau wrote:
Hi Fabio,
On Friday, February 22, 2013 10:06:42 PM, Fabio Estevam wrote:
Hi Benoît,
On Fri, Feb 22, 2013 at 5:09 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
It looks very much like the issue that Marek had on i.MX53 (which self-resolved for an unknown reason).
Try to enable the debug trace to see if anything else is printed after display_dram_config(). I would especially be interested in: debug("relocation Offset is: %08lx\n", gd->reloc_off); debug("monitor flash len: %08lX\n", monitor_flash_len);
Here is the output:
U-Boot 2013.01 (Feb 22 2013 - 18:00:50)
U-Boot code: 87F00000 -> 87F2C184 BSS: -> 87F311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: POR Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 000be000
CONFIG_SYS_TEXT_BASE seems fine according to this trace. But anyway, can you test with this change in mx31pdk.h? #define CONFIG_SPL_TEXT_BASE 0x84000000 #define CONFIG_SYS_TEXT_BASE 0x83000000
Can you try to revert 10/19, only for arm1136/start.S (1 line to restore)? There is an issue in this patch that I have already fixed in my v8.
Best regards, Benoît _______________________________________________
How about changing
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x32000
is see monitor len: 311B4 above is over 0x30000
Thanks, Troy. When I tried increasing from 0x30000 it did not boot anymore. Still checking.
Sorry, I flashed it incorrectly.
Now, after changing it to 0x32000 I can see the boot progresses a bit:
U-Boot code: 87F00000 -> 87F2C184 BSS: -> 87F311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: WDOG Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 000be000 monitor flash len: 00030F7C Now running in RAM - U-Boot at: 87fbe000 NAND: 256 MiB
On Fri, Feb 22, 2013 at 7:02 PM, Fabio Estevam festevam@gmail.com wrote:
U-Boot code: 87F00000 -> 87F2C184 BSS: -> 87F311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: WDOG Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 000be000 monitor flash len: 00030F7C Now running in RAM - U-Boot at: 87fbe000 NAND: 256 MiB
and after this it does not hang, it keeps resetting forever.
On Fri, Feb 22, 2013 at 7:03 PM, Fabio Estevam festevam@gmail.com wrote:
On Fri, Feb 22, 2013 at 7:02 PM, Fabio Estevam festevam@gmail.com wrote:
U-Boot code: 87F00000 -> 87F2C184 BSS: -> 87F311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: WDOG Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 000be000 monitor flash len: 00030F7C Now running in RAM - U-Boot at: 87fbe000 NAND: 256 MiB
and after this it does not hang, it keeps resetting forever.
I disabled watchdog and now I can reach U-boot prompt :-) Thanks Benoit and Troy!
Will fix the watchdog later.
Hi Fabio,
On Friday, February 22, 2013 11:08:14 PM, Fabio Estevam wrote:
On Fri, Feb 22, 2013 at 7:03 PM, Fabio Estevam festevam@gmail.com wrote:
On Fri, Feb 22, 2013 at 7:02 PM, Fabio Estevam festevam@gmail.com wrote:
U-Boot code: 87F00000 -> 87F2C184 BSS: -> 87F311B4 CPU: Freescale i.MX31 rev 2.0 at 532 MHz. Reset cause: WDOG Board: MX31PDK monitor len: 000311B4 ramsize: 08000000 TLB table from 87ff0000 to 87ff4000 Top of RAM usable for U-Boot at: 87ff0000 Reserving 196k for U-Boot at: 87fbe000 Reserving 640k for malloc() at: 87f1e000 Reserving 32 Bytes for Board Info at: 87f1dfe0 Reserving 128 Bytes for Global Data at: 87f1df60 New Stack Pointer is: 87f1df50 RAM Configuration: Bank #0: 80000000 128 MiB relocation Offset is: 000be000 monitor flash len: 00030F7C Now running in RAM - U-Boot at: 87fbe000 NAND: 256 MiB
and after this it does not hang, it keeps resetting forever.
I disabled watchdog and now I can reach U-boot prompt :-) Thanks Benoit and Troy!
Will fix the watchdog later.
Great! So can you confirm that for my series, all I have to change is: #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x32000 ?
Did you also have a chance to test nand commands on mx53ard?
Thanks for all your tests.
Best regards, Benoît
On Fri, Feb 22, 2013 at 7:42 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Great! So can you confirm that for my series, all I have to change is: #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x32000
Yes, correct. This is the only change you need to do in your series.
Did you also have a chance to test nand commands on mx53ard?
Not yet, will try this early next week.
Thanks for providing SPL NAND support for imx!
Regards,
Fabio Estevam
Dear Fabio Estevam,
On Fri, Feb 22, 2013 at 7:42 PM, Benoît Thébaudeau
benoit.thebaudeau@advansee.com wrote:
Great! So can you confirm that for my series, all I have to change is: #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x32000
Yes, correct. This is the only change you need to do in your series.
Did you also have a chance to test nand commands on mx53ard?
Not yet, will try this early next week.
Thanks for providing SPL NAND support for imx!
We won't need SPL on mx53, I pretty much have patches for mx53 NAND boot without SPL ready, just need some polishment.
Best regards, Marek Vasut
Dear Marek Vasut,
On Saturday, February 23, 2013 12:11:47 AM, Marek Vasut wrote:
Dear Fabio Estevam,
On Fri, Feb 22, 2013 at 7:42 PM, Benoît Thébaudeau
benoit.thebaudeau@advansee.com wrote:
Great! So can you confirm that for my series, all I have to change is: #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x32000
Yes, correct. This is the only change you need to do in your series.
Did you also have a chance to test nand commands on mx53ard?
Not yet, will try this early next week.
Thanks for providing SPL NAND support for imx!
We won't need SPL on mx53, I pretty much have patches for mx53 NAND boot without SPL ready, just need some polishment.
Cool.
How did you omit the SPL? Are you using the FCB bad block feature to handle these? Have you tested that it still works if your image spans several NAND blocks among which are some bad blocks (with bad blocks having been skipped while programming the image)?
Best regards, Benoît
Dear Benoît Thébaudeau,
Dear Marek Vasut,
On Saturday, February 23, 2013 12:11:47 AM, Marek Vasut wrote:
Dear Fabio Estevam,
On Fri, Feb 22, 2013 at 7:42 PM, Benoît Thébaudeau
benoit.thebaudeau@advansee.com wrote:
Great! So can you confirm that for my series, all I have to change is: #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x32000
Yes, correct. This is the only change you need to do in your series.
Did you also have a chance to test nand commands on mx53ard?
Not yet, will try this early next week.
Thanks for providing SPL NAND support for imx!
We won't need SPL on mx53, I pretty much have patches for mx53 NAND boot without SPL ready, just need some polishment.
Cool.
How did you omit the SPL? Are you using the FCB bad block feature to handle these? Have you tested that it still works if your image spans several NAND blocks among which are some bad blocks (with bad blocks having been skipped while programming the image)?
My NAND is almost new by now, so I haven't.
Best regards, Marek Vasut
Dear Marek Vasut,
On Saturday, February 23, 2013 12:56:32 AM, Marek Vasut wrote:
Dear Benoît Thébaudeau,
Dear Marek Vasut,
On Saturday, February 23, 2013 12:11:47 AM, Marek Vasut wrote:
Dear Fabio Estevam,
On Fri, Feb 22, 2013 at 7:42 PM, Benoît Thébaudeau
benoit.thebaudeau@advansee.com wrote:
Great! So can you confirm that for my series, all I have to change is: #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x32000
Yes, correct. This is the only change you need to do in your series.
Did you also have a chance to test nand commands on mx53ard?
Not yet, will try this early next week.
Thanks for providing SPL NAND support for imx!
We won't need SPL on mx53, I pretty much have patches for mx53 NAND boot without SPL ready, just need some polishment.
Cool.
How did you omit the SPL? Are you using the FCB bad block feature to handle these? Have you tested that it still works if your image spans several NAND blocks among which are some bad blocks (with bad blocks having been skipped while programming the image)?
My NAND is almost new by now, so I haven't.
Sure, but you can still play with "nand markbad" (and with "nand scrub" for cleanup after your tests) with BBT disabled (in order to avoid any assumption regarding the possible handling of the BBT by the boot ROM since markbad only updates the BBT if it is enabled). So here is the procedure that you could follow: - Use "nand bad" to keep track of the initial true bad blocks (+ fake ones at the end of the NAND if you have enabled BBT). - Disable BBT if it was enabled (undefine CONFIG_SYS_NAND_USE_FLASH_BBT). - Use "nand markbad" to create some fake bad blocks (at least 1) at the location of your image. - Program your image skipping bad blocks. - Test your SPL-free boot. - Once done, use "nand scrub" to try to unmark bad blocks. - Use "nand markbad" to re-mark the true bad blocks as such. - Re-enable BBT in your code if you want to.
Best regards, Benoît
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: - New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm926ejs/start.S | 10 ---------- 1 file changed, 10 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 1db1152..60b0a67 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -120,15 +120,11 @@ _fiq:
.globl _TEXT_BASE _TEXT_BASE: -#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ - .word CONFIG_SYS_TEXT_BASE -#else #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_SYS_TEXT_BASE #endif -#endif
/* * These are defined in the board-specific linker script. @@ -152,12 +148,6 @@ _bss_end_ofs: _end_ofs: .word _end - _start
-#ifdef CONFIG_NAND_U_BOOT -.globl _end -_end: - .word __bss_end__ -#endif - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START
Hi Albert, Tom, Zhong,
On Friday, February 15, 2013 9:54:22 PM, Benoît Thébaudeau wrote:
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Changes in v7: None Changes in v6:
- New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm926ejs/start.S | 10 ---------- 1 file changed, 10 deletions(-)
I would like to get your feedback regarding the status of the Samsung SMDK6400 board: - It is not in boards.cfg, so, according to commit 1285a28, support for it should already have been removed a long time ago. It also seems to be the only board remaining in the main Makefile. - It uses the deprecated NAND SPL. - MAKEALL does not test its build, which has been broken for a while. - If it were removed or fixed, ARM1176's start.S' relocate_code() could be made identical to all the other implementations of this function, so all this duplicated code could be moved to a common location like crt0.S. Besides that, it would be possible to completely get rid of the legacy NAND SPL on ARM.
I have no intention of fixing this board, but dropping it and cleaning up ARM after that would be easy.
Best regards, Benoît
Hi Benoît,
On Sun, 17 Feb 2013 16:51:37 +0100 (CET), Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Hi Albert, Tom, Zhong,
On Friday, February 15, 2013 9:54:22 PM, Benoît Thébaudeau wrote:
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Changes in v7: None Changes in v6:
- New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm926ejs/start.S | 10 ---------- 1 file changed, 10 deletions(-)
I would like to get your feedback regarding the status of the Samsung SMDK6400 board:
- It is not in boards.cfg, so, according to commit 1285a28, support for it should already have been removed a long time ago. It also seems to be the only board remaining in the main Makefile.
- It uses the deprecated NAND SPL.
- MAKEALL does not test its build, which has been broken for a while.
- If it were removed or fixed, ARM1176's start.S' relocate_code() could be made identical to all the other implementations of this function, so all this duplicated code could be moved to a common location like crt0.S. Besides that, it would be possible to completely get rid of the legacy NAND SPL on ARM.
I have no intention of fixing this board, but dropping it and cleaning up ARM after that would be easy.
Cc:ing the board maintainers, as they should be the first ones to be asked whether they intend to bring the board into boards.cfg and fix it, or whether it should be dropped.
Best regards, Benoît
Amicalement,
Hi Albert,
On Sun, 17 Feb 2013 17:04:54 +0100, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
Hi Benoît,
On Sun, 17 Feb 2013 16:51:37 +0100 (CET), Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Hi Albert, Tom, Zhong,
On Friday, February 15, 2013 9:54:22 PM, Benoît Thébaudeau wrote:
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Changes in v7: None Changes in v6:
- New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm926ejs/start.S | 10 ---------- 1 file changed, 10 deletions(-)
I would like to get your feedback regarding the status of the Samsung SMDK6400 board:
- It is not in boards.cfg, so, according to commit 1285a28, support for it should already have been removed a long time ago. It also seems to be the only board remaining in the main Makefile.
- It uses the deprecated NAND SPL.
- MAKEALL does not test its build, which has been broken for a while.
- If it were removed or fixed, ARM1176's start.S' relocate_code() could be made identical to all the other implementations of this function, so all this duplicated code could be moved to a common location like crt0.S. Besides that, it would be possible to completely get rid of the legacy NAND SPL on ARM.
I have no intention of fixing this board, but dropping it and cleaning up ARM after that would be easy.
Cc:ing the board maintainers, as they should be the first ones to be asked whether they intend to bring the board into boards.cfg and fix it, or whether it should be dropped.
Scratch this: correct maintainer CC:ed now (how about changing the MAINTAINERS file format so that we can tell for sure without having to ceck the first entry?)
Best regards, Benoît
Amicalement,
Amicalement,
On Sunday, February 17, 2013 5:08:00 PM, Albert ARIBAUD wrote:
Hi Albert,
On Sun, 17 Feb 2013 17:04:54 +0100, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
Hi Benoît,
On Sun, 17 Feb 2013 16:51:37 +0100 (CET), Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Hi Albert, Tom, Zhong,
On Friday, February 15, 2013 9:54:22 PM, Benoît Thébaudeau wrote:
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Changes in v7: None Changes in v6:
- New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm926ejs/start.S | 10 ---------- 1 file changed, 10 deletions(-)
I would like to get your feedback regarding the status of the Samsung SMDK6400 board:
- It is not in boards.cfg, so, according to commit 1285a28, support for
it should already have been removed a long time ago. It also seems to be the only board remaining in the main Makefile.
- It uses the deprecated NAND SPL.
- MAKEALL does not test its build, which has been broken for a while.
- If it were removed or fixed, ARM1176's start.S' relocate_code() could
be made identical to all the other implementations of this function, so all this duplicated code could be moved to a common location like crt0.S. Besides that, it would be possible to completely get rid of the legacy NAND SPL on ARM.
I have no intention of fixing this board, but dropping it and cleaning up ARM after that would be easy.
Cc:ing the board maintainers, as they should be the first ones to be asked whether they intend to bring the board into boards.cfg and fix it, or whether it should be dropped.
Scratch this: correct maintainer CC:ed now
Yes, I had already Cc'ed Zhong.
(how about changing the MAINTAINERS file format so that we can tell for sure without having to ceck the first entry?)
That would be good. E.g., a colon could be added after the last e-mail address of each group of board maintainers, or the empty line between the e-mail addresses and the boards could be removed.
Best regards, Benoît
On Sunday, February 17, 2013 5:25:33 PM, Benoît Thébaudeau wrote:
On Sunday, February 17, 2013 5:08:00 PM, Albert ARIBAUD wrote:
Hi Albert,
On Sun, 17 Feb 2013 17:04:54 +0100, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
Hi Benoît,
On Sun, 17 Feb 2013 16:51:37 +0100 (CET), Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Hi Albert, Tom, Zhong,
On Friday, February 15, 2013 9:54:22 PM, Benoît Thébaudeau wrote:
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Changes in v7: None Changes in v6:
- New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm926ejs/start.S | 10 ---------- 1 file changed, 10 deletions(-)
I would like to get your feedback regarding the status of the Samsung SMDK6400 board:
- It is not in boards.cfg, so, according to commit 1285a28, support
for it should already have been removed a long time ago. It also seems to be the only board remaining in the main Makefile.
- It uses the deprecated NAND SPL.
- MAKEALL does not test its build, which has been broken for a while.
- If it were removed or fixed, ARM1176's start.S' relocate_code()
could be made identical to all the other implementations of this function, so all this duplicated code could be moved to a common location like crt0.S. Besides that, it would be possible to completely get rid of the legacy NAND SPL on ARM.
I have no intention of fixing this board, but dropping it and cleaning up ARM after that would be easy.
Cc:ing the board maintainers, as they should be the first ones to be asked whether they intend to bring the board into boards.cfg and fix it, or whether it should be dropped.
Scratch this: correct maintainer CC:ed now
Yes, I had already Cc'ed Zhong.
Adding Mike to Cc as he had been assigned the board migration job to boards.cfg, due for v2012.03. Perhaps he got some information from the SMDK6400 maintainer.
Best regards, Benoît
On Sun, Feb 17, 2013 at 04:51:37PM +0100, Beno??t Th??baudeau wrote:
Hi Albert, Tom, Zhong,
On Friday, February 15, 2013 9:54:22 PM, Beno??t Th??baudeau wrote:
Signed-off-by: Beno??t Th??baudeau benoit.thebaudeau@advansee.com
Changes in v7: None Changes in v6:
- New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm926ejs/start.S | 10 ---------- 1 file changed, 10 deletions(-)
I would like to get your feedback regarding the status of the Samsung SMDK6400 board:
- It is not in boards.cfg, so, according to commit 1285a28, support for it should already have been removed a long time ago. It also seems to be the only board remaining in the main Makefile.
- It uses the deprecated NAND SPL.
- MAKEALL does not test its build, which has been broken for a while.
- If it were removed or fixed, ARM1176's start.S' relocate_code() could be made identical to all the other implementations of this function, so all this duplicated code could be moved to a common location like crt0.S. Besides that, it would be possible to completely get rid of the legacy NAND SPL on ARM.
I have no intention of fixing this board, but dropping it and cleaning up ARM after that would be easy.
I'm in favor of removing and updating README.scrapyard, baring quick attention from the maintainer to update it to not being using the Makefile and fix the rest of the breakage.
Hi Tom,
On Monday, February 18, 2013 5:40:21 PM, Tom Rini wrote:
On Sun, Feb 17, 2013 at 04:51:37PM +0100, Beno??t Th??baudeau wrote:
Hi Albert, Tom, Zhong,
On Friday, February 15, 2013 9:54:22 PM, Beno??t Th??baudeau wrote:
Signed-off-by: Beno??t Th??baudeau benoit.thebaudeau@advansee.com
Changes in v7: None Changes in v6:
- New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm926ejs/start.S | 10 ---------- 1 file changed, 10 deletions(-)
I would like to get your feedback regarding the status of the Samsung SMDK6400 board:
- It is not in boards.cfg, so, according to commit 1285a28, support for it should already have been removed a long time ago. It also seems to be the only board remaining in the main Makefile.
- It uses the deprecated NAND SPL.
- MAKEALL does not test its build, which has been broken for a while.
- If it were removed or fixed, ARM1176's start.S' relocate_code() could be
made identical to all the other implementations of this function, so all this duplicated code could be moved to a common location like crt0.S. Besides that, it would be possible to completely get rid of the legacy NAND SPL on ARM.
I have no intention of fixing this board, but dropping it and cleaning up ARM after that would be easy.
I'm in favor of removing and updating README.scrapyard, baring quick attention from the maintainer to update it to not being using the Makefile and fix the rest of the breakage.
OK. The s3c64xx SoC and all the drivers coming with it then become unused. Should this be removed too? There may be out-of-tree users of this SoC.
Best regards, Benoît
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1
On 02/18/2013 03:39 PM, Benoît Thébaudeau wrote:
Hi Tom,
On Monday, February 18, 2013 5:40:21 PM, Tom Rini wrote:
On Sun, Feb 17, 2013 at 04:51:37PM +0100, Beno??t Th??baudeau wrote:
Hi Albert, Tom, Zhong,
On Friday, February 15, 2013 9:54:22 PM, Beno??t Th??baudeau wrote:
Signed-off-by: Beno??t Th??baudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: - New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm926ejs/start.S | 10 ---------- 1 file changed, 10 deletions(-)
I would like to get your feedback regarding the status of the Samsung SMDK6400 board: - It is not in boards.cfg, so, according to commit 1285a28, support for it should already have been removed a long time ago. It also seems to be the only board remaining in the main Makefile. - It uses the deprecated NAND SPL. - MAKEALL does not test its build, which has been broken for a while. - If it were removed or fixed, ARM1176's start.S' relocate_code() could be made identical to all the other implementations of this function, so all this duplicated code could be moved to a common location like crt0.S. Besides that, it would be possible to completely get rid of the legacy NAND SPL on ARM.
I have no intention of fixing this board, but dropping it and cleaning up ARM after that would be easy.
I'm in favor of removing and updating README.scrapyard, baring quick attention from the maintainer to update it to not being using the Makefile and fix the rest of the breakage.
OK. The s3c64xx SoC and all the drivers coming with it then become unused. Should this be removed too? There may be out-of-tree users of this SoC.
Yes, it's what the scrapyard is for. If an out-of-tree user exists they can either support the reference board (and bring it back from the dead) or their own board.
- -- Tom
Commit e05e5de7fae5bec79617e113916dac6631251156 made the 2 1st parameters of ARM's relocate_code() useless since it moved the code handling them to crt0.S. So, drop these parameters.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: None Changes in v6: - New patch.
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/arm1136/start.S | 4 +--- arch/arm/cpu/arm1176/start.S | 4 +--- arch/arm/cpu/arm720t/start.S | 4 +--- arch/arm/cpu/arm920t/start.S | 4 +--- arch/arm/cpu/arm925t/start.S | 4 +--- arch/arm/cpu/arm926ejs/start.S | 4 +--- arch/arm/cpu/arm946es/start.S | 4 +--- arch/arm/cpu/arm_intcm/start.S | 4 +--- arch/arm/cpu/armv7/start.S | 4 +--- arch/arm/cpu/ixp/start.S | 4 +--- arch/arm/cpu/pxa/start.S | 4 +--- arch/arm/cpu/s3c44b0/start.S | 4 +--- arch/arm/cpu/sa1100/start.S | 4 +--- arch/arm/lib/crt0.S | 8 +++----- board/freescale/mx31pdk/mx31pdk.c | 2 +- board/karo/tx25/tx25.c | 2 +- board/samsung/smdk6400/smdk6400_nand_spl.c | 3 +-- include/common.h | 8 ++++---- 18 files changed, 23 insertions(+), 52 deletions(-)
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 9554807..b2d8184 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -182,9 +182,7 @@ next: */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
adr r0, _start cmp r0, r6 diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index e7d2737..bb96ef8 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -249,9 +249,7 @@ skip_tcmdisable: */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
adr r0, _start cmp r0, r6 diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 440aff5..8555082 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -164,9 +164,7 @@ reset: */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
adr r0, _start cmp r0, r6 diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 60b6a80..c8d6907 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -203,9 +203,7 @@ copyex: */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
adr r0, _start cmp r0, r6 diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 6d5c9de..310c89e 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -193,9 +193,7 @@ poll1: */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
adr r0, _start cmp r0, r6 diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 60b0a67..ff82eeb 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -199,9 +199,7 @@ reset: */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
adr r0, _start cmp r0, r6 diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 8a245e0..78ecdff 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -168,9 +168,7 @@ reset: */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
adr r0, _start cmp r0, r6 diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index 9e1a34e..2fd1f05 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -164,9 +164,7 @@ reset: */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
adr r0, _start cmp r0, r6 diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 784c363..89dcd4c 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -172,9 +172,7 @@ reset: * */ ENTRY(relocate_code) - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
adr r0, _start cmp r0, r6 diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index 96cc014..a0692fe 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -266,9 +266,7 @@ reset: */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
adr r0, _start cmp r0, r6 diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index f555851..98c2cc0 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -181,9 +181,7 @@ reset: */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
/* Disable the Dcache RAM lock for stack now */ #ifdef CONFIG_CPU_PXA25X diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index e34e387..154ac25 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -149,9 +149,7 @@ reset: */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
adr r0, _start cmp r0, r6 diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index fb58977..507b628 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -153,9 +153,7 @@ reset: */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */
adr r0, _start cmp r0, r6 diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 6946cbc..252e8e9 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -97,8 +97,8 @@ _main:
/* * Set up intermediate environment (new sp and gd) and call - * relocate_code(addr_sp, gd, addr_moni). Trick here is that - * we'll return 'here' but relocated. + * relocate_code(addr_moni). Trick here is that we'll return + * 'here' but relocated. */
ldr sp, [r8, #GD_START_ADDR_SP] /* r8 = gd->start_addr_sp */ @@ -109,9 +109,7 @@ _main: adr lr, here ldr r0, [r8, #GD_RELOC_OFF] /* lr = gd->start_addr_sp */ add lr, lr, r0 - ldr r0, [r8, #GD_START_ADDR_SP] /* r0 = gd->start_addr_sp */ - mov r1, r8 /* r1 = gd */ - ldr r2, [r8, #GD_RELOCADDR] /* r2 = gd->relocaddr */ + ldr r0, [r8, #GD_RELOCADDR] /* r0 = gd->relocaddr */ b relocate_code here:
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index df5d407..0ec190d 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD void board_init_f(ulong bootflag) { - relocate_code(0, NULL, CONFIG_SPL_TEXT_BASE); + relocate_code(CONFIG_SPL_TEXT_BASE); asm volatile("ldr pc, =nand_boot\n"); } #endif diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 6058fbf..b0c3b53 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD void board_init_f(ulong bootflag) { - relocate_code(0, NULL, CONFIG_SPL_TEXT_BASE); + relocate_code(CONFIG_SPL_TEXT_BASE); asm volatile("ldr pc, =nand_boot\n"); } #endif diff --git a/board/samsung/smdk6400/smdk6400_nand_spl.c b/board/samsung/smdk6400/smdk6400_nand_spl.c index a023284..26a6146 100644 --- a/board/samsung/smdk6400/smdk6400_nand_spl.c +++ b/board/samsung/smdk6400/smdk6400_nand_spl.c @@ -32,6 +32,5 @@
void board_init_f(unsigned long bootflag) { - relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, - CONFIG_SYS_TEXT_BASE); + relocate_code(CONFIG_SYS_TEXT_BASE); } diff --git a/include/common.h b/include/common.h index 691e279..3d643a6 100644 --- a/include/common.h +++ b/include/common.h @@ -515,11 +515,11 @@ int dcache_status (void); void dcache_enable (void); void dcache_disable(void); void mmu_disable(void); -void relocate_code(ulong, gd_t *, ulong) -#if !defined(CONFIG_ARM) -__attribute__ ((noreturn)) +#if defined(CONFIG_ARM) +void relocate_code(ulong); +#else +void relocate_code(ulong, gd_t *, ulong) __attribute__ ((noreturn)); #endif -; ulong get_endaddr (void); void trap_init (ulong); #if defined (CONFIG_4xx) || \
This image combines the SPL with the i.MX header and U-Boot. This is a convenient way of having a single image to program on some boot devices.
The i.MX header has to be added to the SPL before appending U-Boot, so that the boot ROM loads only the SPL.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: - New patch.
Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
Makefile | 5 +++++ arch/arm/imx-common/Makefile | 11 +++++++++++ 2 files changed, 16 insertions(+)
diff --git a/Makefile b/Makefile index 317dffc..896266f 100644 --- a/Makefile +++ b/Makefile @@ -491,6 +491,10 @@ $(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@ rm $(obj)spl/u-boot-spl-pad.bin
+$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin + $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \ + $(OBJTREE)/u-boot-with-spl.imx + $(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \ -e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl @@ -862,6 +866,7 @@ clobber: tidy @rm -f $(obj)u-boot.kwb @rm -f $(obj)u-boot.pbl @rm -f $(obj)u-boot.imx + @rm -f $(obj)u-boot-with-spl.imx @rm -f $(obj)u-boot.ubl @rm -f $(obj)u-boot.ais @rm -f $(obj)u-boot.dtb diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 6309fcd..24bf822 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -54,6 +54,17 @@ $(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONF $(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \ -e $(CONFIG_SPL_TEXT_BASE) -d $< $@
+$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bin \ + $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_MAX_SIZE) -I binary \ + -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.bin + $(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \ + -e $(CONFIG_SPL_TEXT_BASE) -d $(OBJTREE)/spl/u-boot-spl-pad.bin \ + $(OBJTREE)/spl/u-boot-spl-pad.imx + rm $(OBJTREE)/spl/u-boot-spl-pad.bin + cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.bin > $@ + rm $(OBJTREE)/spl/u-boot-spl-pad.imx +
#########################################################################
This image adds a dummy 1024-byte header to u-boot-with-spl.imx in order to get an image that can be programmed on a NAND Flash page boundary.
This supports only i.MX25/35/51 so far, not i.MX53/6. For the latter, the dummy header will have to be replaced with a generated FCB header depending at least on the NAND Flash page size.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- Changes in v7: - New patch.
Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
Makefile | 5 +++++ arch/arm/imx-common/Makefile | 3 +++ 2 files changed, 8 insertions(+)
diff --git a/Makefile b/Makefile index 896266f..8bda59d 100644 --- a/Makefile +++ b/Makefile @@ -495,6 +495,10 @@ $(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \ $(OBJTREE)/u-boot-with-spl.imx
+$(obj)u-boot-with-nand-spl.imx: $(obj)u-boot-with-spl.imx + $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \ + $(OBJTREE)/u-boot-with-nand-spl.imx + $(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \ -e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl @@ -867,6 +871,7 @@ clobber: tidy @rm -f $(obj)u-boot.pbl @rm -f $(obj)u-boot.imx @rm -f $(obj)u-boot-with-spl.imx + @rm -f $(obj)u-boot-with-nand-spl.imx @rm -f $(obj)u-boot.ubl @rm -f $(obj)u-boot.ais @rm -f $(obj)u-boot.dtb diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 24bf822..835040f 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -65,6 +65,9 @@ $(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot. cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.bin > $@ rm $(OBJTREE)/spl/u-boot-spl-pad.imx
+$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/u-boot-with-spl.imx + dd bs=1024 count=1 if=/dev/zero 2>/dev/null | cat - $< > $@ +
#########################################################################
participants (7)
-
Albert ARIBAUD -
Benoît Thébaudeau -
Fabio Estevam -
Marek Vasut -
Scott Wood -
Tom Rini -
Troy Kisky