[PATCH 0/3] Support for Qualcomm sm8150 SoC
This series picks up the work from Volodymyr Babchuk ([v2] Add support for Qualcomm SA8155-ADP board). clk and pinctrl drivers are adjusted to work similarly to existing qcom drivers. I could only test this using android boot chainloading.
This is my first patch ever using mailing lists, so hopefully nothing is missing.
Julius Lehmann (3): clk: qcom: add driver for SM8150 SoC pinctrl: qcom: add driver for SM8150 SoC config: qcom: add sm8150 to qcom_defconfig
configs/qcom_defconfig | 2 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-sm8150.c | 298 ++++++++++++++++++++++++++ drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8150.c | 119 ++++++++++ 7 files changed, 438 insertions(+) create mode 100644 drivers/clk/qcom/clock-sm8150.c create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c
Add clock, reset and power domain driver for SM8150. Driver code is based on the similar U-Boot drivers. All constants are taken from the corresponding Linux driver.
This driver supports clock rate setting only debug UART, RGMII/Ethernet modules and USB controller.
Co-authored-by: Volodymyr Babchuk volodymyr_babchuk@epam.com Signed-off-by: Julius Lehmann lehmanju@devpi.de ---
drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-sm8150.c | 298 ++++++++++++++++++++++++++++++++ 3 files changed, 308 insertions(+) create mode 100644 drivers/clk/qcom/clock-sm8150.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 45d63c6d6d..4ac50f25f4 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -69,6 +69,7 @@ config CLK_QCOM_SM8250 help Say Y here to enable support for the Global Clock Controller on the Snapdragon SM8250 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block.
config CLK_QCOM_SM8550 bool "Qualcomm SM8550 GCC" @@ -86,6 +87,14 @@ config CLK_QCOM_SM8650 on the Snapdragon SM8650 SoC. This driver supports the clocks and resets exposed by the GCC hardware block.
+config CLK_QCOM_SM8150 + bool "Qualcomm SM8150 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon 8150 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + endmenu
endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index dec20e4b59..e1ab3f9bdd 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o obj-$(CONFIG_CLK_QCOM_SM8650) += clock-sm8650.o +obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o diff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c new file mode 100644 index 0000000000..83c8bc335c --- /dev/null +++ b/drivers/clk/qcom/clock-sm8150.c @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm SM8150 + * + * Volodymyr Babchuk volodymyr_babchuk@epam.com + * Copyright (c) 2024 EPAM Systems. + * + * (C) Copyright 2024 Julius Lehmann lehmanju@devpi.de + * + * Based on U-Boot driver for SM8250. Constants are taken from the Linux driver. + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,gcc-sm8150.h> + +#include "clock-qcom.h" + +#define EMAC_RGMII_CLK_CMD_RCGR 0x601c +#define QUPV3_WRAP0_S0_CLK_CMD_RCGR 0x18148 +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf01c +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf034 +#define USB30_SEC_MASTER_CLK_CMD_RCGR 0x1001c +#define USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR 0x10034 + +static struct pll_vote_clk gpll7_vote_clk = { + .status = 0x1a000, + .status_bit = BIT(31), + .ena_vote = 0x52000, + .vote_bit = BIT(7), +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), + F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375), + F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75), + F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625), + F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0), + F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75), + { } +}; + +static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { + F(2500000, CFG_CLK_SRC_CXO, 1, 25, 192), + F(5000000, CFG_CLK_SRC_CXO, 1, 25, 96), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), + F(125000000, CFG_CLK_SRC_GPLL7, 4, 0, 0), + F(250000000, CFG_CLK_SRC_GPLL7, 2, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { + F(33333333, CFG_CLK_SRC_GPLL0_EVEN, 9, 0, 0), + F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0), + F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0), + F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(20000000, CFG_CLK_SRC_GPLL0_EVEN, 15, 0, 0), + F(60000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 0, 0), + { } +}; + +static ulong sm8150_clk_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + switch (clk->id) { + case GCC_QUPV3_WRAP1_S4_CLK: /* UART2 aka debug-uart */ + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S0_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_EMAC_RGMII_CLK: + freq = qcom_find_freq(ftbl_gcc_emac_rgmii_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, EMAC_RGMII_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_PRIM_MASTER_CLK: + freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_PRIM_MOCK_UTMI_CLK: + freq = qcom_find_freq(ftbl_gcc_usb30_prim_mock_utmi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: + freq = qcom_find_freq(ftbl_gcc_usb30_prim_mock_utmi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_SEC_MASTER_CLK: + freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MASTER_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_SEC_MOCK_UTMI_CLK: + freq = qcom_find_freq(ftbl_gcc_usb30_prim_mock_utmi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB3_SEC_PHY_AUX_CLK_SRC: + freq = qcom_find_freq(ftbl_gcc_usb30_prim_mock_utmi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + default: + return 0; + } +} + +static const struct gate_clk sm8150_clks[] = { + GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf07c, 0x00000001), + GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x1007c, 0x00000001), + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf078, 0x00000001), + GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x10078, 0x00000001), + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, 0x00000400), + GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, 0x00000800), + GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, 0x00001000), + GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x5200c, 0x00002000), + GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x5200c, 0x00004000), + GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x5200c, 0x00008000), + GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x5200c, 0x00400000), + GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x5200c, 0x00800000), + GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x5200c, 0x02000000), + GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, 0x04000000), + GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, 0x08000000), + GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x5200c, 0x00000040), + GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x5200c, 0x00000080), + GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x5200c, 0x00100000), + GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x5200c, 0x00200000), + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, 0x00000001), + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, 0x00000001), + GATE_CLK(GCC_SDCC4_AHB_CLK, 0x16008, 0x00000001), + GATE_CLK(GCC_SDCC4_APPS_CLK, 0x16004, 0x00000001), + GATE_CLK(GCC_UFS_CARD_AHB_CLK, 0x75010, 0x00000001), + GATE_CLK(GCC_UFS_CARD_AXI_CLK, 0x7500c, 0x00000001), + GATE_CLK(GCC_UFS_CARD_CLKREF_CLK, 0x8c004, 0x00000001), + GATE_CLK(GCC_UFS_CARD_ICE_CORE_CLK, 0x75058, 0x00000001), + GATE_CLK(GCC_UFS_CARD_PHY_AUX_CLK, 0x7508c, 0x00000001), + GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_0_CLK, 0x75018, 0x00000001), + GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK, 0x750a8, 0x00000001), + GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK, 0x75014, 0x00000001), + GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK, 0x75054, 0x00000001), + GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, 0x00000001), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77010, 0x00000001), + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x7700c, 0x00000001), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77058, 0x00000001), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7708c, 0x00000001), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77018, 0x00000001), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770a8, 0x00000001), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77014, 0x00000001), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77054, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x0f00c, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x0f014, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x0f010, 0x00000001), + GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x1000c, 0x00000001), + GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x10014, 0x00000001), + GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x10010, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c008, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x0f04c, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x0f050, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x0f054, 0x00000001), + GATE_CLK(GCC_USB3_SEC_CLKREF_CLK, 0x8c028, 0x00000001), + GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x1004c, 0x00000001), + GATE_CLK(GCC_USB3_SEC_PHY_PIPE_CLK, 0x10054, 0x00000001), + GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x10050, 0x00000001), + GATE_CLK(GCC_EMAC_AXI_CLK, 0x06010, 0x00000001), + GATE_CLK(GCC_EMAC_SLV_AHB_CLK, 0x06014, 0x00000001), + GATE_CLK(GCC_EMAC_PTP_CLK, 0x06034, 0x00000001), + GATE_CLK(GCC_EMAC_RGMII_CLK, 0x06018, 0x00000001), +}; + +static int sm8150_clk_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %s\n", __func__, sm8150_clks[clk->id].name); + + switch (clk->id) { + case GCC_EMAC_RGMII_CLK: + clk_enable_gpll0(priv->base, &gpll7_vote_clk); + case GCC_AGGRE_USB3_PRIM_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); + fallthrough; + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + break; + case GCC_AGGRE_USB3_SEC_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_SEC_MASTER_CLK); + fallthrough; + case GCC_USB30_SEC_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK); + break; + }; + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map sm8150_gcc_resets[] = { + [GCC_EMAC_BCR] = { 0x6000 }, + [GCC_GPU_BCR] = { 0x71000 }, + [GCC_MMSS_BCR] = { 0xb000 }, + [GCC_NPU_BCR] = { 0x4d000 }, + [GCC_PCIE_0_BCR] = { 0x6b000 }, + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, + [GCC_PCIE_1_BCR] = { 0x8d000 }, + [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, + [GCC_PCIE_PHY_BCR] = { 0x6f000 }, + [GCC_PDM_BCR] = { 0x33000 }, + [GCC_PRNG_BCR] = { 0x34000 }, + [GCC_QSPI_BCR] = { 0x24008 }, + [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, + [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, + [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, + [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC4_BCR] = { 0x16000 }, + [GCC_TSIF_BCR] = { 0x36000 }, + [GCC_UFS_CARD_BCR] = { 0x75000 }, + [GCC_UFS_PHY_BCR] = { 0x77000 }, + [GCC_USB30_PRIM_BCR] = { 0xf000 }, + [GCC_USB30_SEC_BCR] = { 0x10000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, +}; + +static const struct qcom_power_map sm8150_gcc_power_domains[] = { + [EMAC_GDSC] = { 0x6004 }, + [PCIE_0_GDSC] = { 0x6b004 }, + [PCIE_1_GDSC] = { 0x8d004 }, + [UFS_CARD_GDSC] = { 0x75004 }, + [UFS_PHY_GDSC] = { 0x77004 }, + [USB30_PRIM_GDSC] = { 0xf004 }, + [USB30_SEC_GDSC] = { 0x10004 }, +}; + +static struct msm_clk_data sm8150_clk_data = { + .resets = sm8150_gcc_resets, + .num_resets = ARRAY_SIZE(sm8150_gcc_resets), + .clks = sm8150_clks, + .num_clks = ARRAY_SIZE(sm8150_clks), + .power_domains = sm8150_gcc_power_domains, + .num_power_domains = ARRAY_SIZE(sm8150_gcc_power_domains), + + .enable = sm8150_clk_enable, + .set_rate = sm8150_clk_set_rate, +}; + +static const struct udevice_id gcc_sm8150_of_match[] = { + { + .compatible = "qcom,gcc-sm8150", + .data = (ulong)&sm8150_clk_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_sm8150) = { + .name = "gcc_sm8150", + .id = UCLASS_NOP, + .of_match = gcc_sm8150_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +};
+static ulong sm8150_clk_set_rate(struct clk *clk, ulong rate) +{
- struct msm_clk_priv *priv = dev_get_priv(clk->dev);
- const struct freq_tbl *freq;
- switch (clk->id) {
- case GCC_QUPV3_WRAP1_S4_CLK: /* UART2 aka debug-uart */
freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S0_CLK_CMD_RCGR,freq->pre_div, freq->m, freq->n, freq->src, 16);return freq->freq;- case GCC_EMAC_RGMII_CLK:
freq = qcom_find_freq(ftbl_gcc_emac_rgmii_clk_src, rate);clk_rcg_set_rate_mnd(priv->base, EMAC_RGMII_CLK_CMD_RCGR,freq->pre_div, freq->m, freq->n, freq->src, 8);return freq->freq;- case GCC_USB30_PRIM_MASTER_CLK:
freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,freq->pre_div, freq->m, freq->n, freq->src, 8);return freq->freq;- case GCC_USB30_PRIM_MOCK_UTMI_CLK:
freq = qcom_find_freq(ftbl_gcc_usb30_prim_mock_utmi_clk_src, rate);clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR,freq->pre_div, freq->m, freq->n, freq->src, 8);return freq->freq;- case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
freq = qcom_find_freq(ftbl_gcc_usb30_prim_mock_utmi_clk_src, rate);clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR,
this doesn't seem right, should probably be a different CMD_RCGR
freq->pre_div, freq->m, freq->n, freq->src, 8);return freq->freq;- case GCC_USB30_SEC_MASTER_CLK:
freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MASTER_CLK_CMD_RCGR,freq->pre_div, freq->m, freq->n, freq->src, 8);return freq->freq;- case GCC_USB30_SEC_MOCK_UTMI_CLK:
freq = qcom_find_freq(ftbl_gcc_usb30_prim_mock_utmi_clk_src, rate);clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR,freq->pre_div, freq->m, freq->n, freq->src, 8);return freq->freq;- case GCC_USB3_SEC_PHY_AUX_CLK_SRC:
freq = qcom_find_freq(ftbl_gcc_usb30_prim_mock_utmi_clk_src, rate);clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR,
same here
freq->pre_div, freq->m, freq->n, freq->src, 8);return freq->freq;- default:
return 0;- }
+}
Add pinctrl and GPIO driver for SM8150. Driver code is based on the similar U-Boot drivers. All constants are taken from the corresponding Linux driver. This drivers differs from the similar U-Boot drivers, because SM8150 SoC have different function IDs for the same functions on different pins.
Co-authored-by: Volodymyr Babchuk volodymyr_babchuk@epam.com Signed-off-by: Julius Lehmann lehmanju@devpi.de ---
drivers/pinctrl/qcom/Kconfig | 8 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8150.c | 119 ++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index b326fa8514..501939f783 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -74,6 +74,14 @@ config PINCTRL_QCOM_SM8650 select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC, + as well as the associated GPIO driver. + +config PINCTRL_QCOM_SM8150 + bool "Qualcomm SM8150 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM8150 SoC, + as well as the associated GPIO driver.
endmenu
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4f1d96787b..cc3660a576 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_QCOM_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o +obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c new file mode 100644 index 0000000000..c3af3448f6 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Qualcomm SM8150 pinctrl and GPIO driver + * + * Volodymyr Babchuk volodymyr_babchuk@epam.com + * Copyright (c) 2024 EPAM Systems. + * + * (C) Copyright 2024 Julius Lehmann lehmanju@devpi.de + * + * Based on similar U-Boot drivers. Constants were taken from the Linux driver + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define WEST 0x00100000 +#define EAST 0x00500000 +#define NORTH 0x00900000 +#define SOUTH 0x00D00000 + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { { "qup2", 1 }, + { "gpio", 0 }, + { "sdc4", 0 } }; + +static const unsigned int sm8150_pin_offsets[] = { + [0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH, + [4] = SOUTH, [5] = SOUTH, [6] = SOUTH, [7] = SOUTH, + [8] = NORTH, [9] = NORTH, [10] = NORTH, [11] = NORTH, + [12] = NORTH, [13] = NORTH, [14] = NORTH, [15] = NORTH, + [16] = NORTH, [17] = NORTH, [18] = NORTH, [19] = NORTH, + [20] = NORTH, [21] = EAST, [22] = EAST, [23] = EAST, + [24] = EAST, [25] = EAST, [26] = EAST, [27] = EAST, + [28] = EAST, [29] = EAST, [30] = EAST, [31] = NORTH, + [32] = NORTH, [33] = NORTH, [34] = NORTH, [35] = NORTH, + [36] = NORTH, [37] = NORTH, [38] = SOUTH, [39] = NORTH, + [40] = NORTH, [41] = NORTH, [42] = NORTH, [43] = EAST, + [44] = EAST, [45] = EAST, [46] = EAST, [47] = EAST, + [48] = EAST, [49] = EAST, [50] = EAST, [51] = SOUTH, + [52] = SOUTH, [53] = SOUTH, [54] = SOUTH, [55] = SOUTH, + [56] = SOUTH, [57] = SOUTH, [58] = SOUTH, [59] = SOUTH, + [60] = SOUTH, [61] = SOUTH, [62] = SOUTH, [63] = SOUTH, + [64] = SOUTH, [65] = SOUTH, [66] = SOUTH, [67] = SOUTH, + [68] = SOUTH, [69] = SOUTH, [70] = SOUTH, [71] = SOUTH, + [72] = SOUTH, [73] = SOUTH, [74] = SOUTH, [75] = SOUTH, + [76] = SOUTH, [77] = SOUTH, [78] = SOUTH, [79] = SOUTH, + [80] = SOUTH, [81] = SOUTH, [82] = SOUTH, [83] = NORTH, + [84] = NORTH, [85] = NORTH, [86] = NORTH, [87] = EAST, + [88] = NORTH, [89] = NORTH, [90] = NORTH, [91] = NORTH, + [92] = NORTH, [93] = NORTH, [94] = NORTH, [95] = NORTH, + [96] = NORTH, [97] = NORTH, [98] = SOUTH, [99] = SOUTH, + [100] = SOUTH, [101] = SOUTH, [102] = NORTH, [103] = NORTH, + [104] = NORTH, [105] = WEST, [106] = WEST, [107] = WEST, + [108] = WEST, [109] = WEST, [110] = WEST, [111] = WEST, + [112] = WEST, [113] = WEST, [114] = SOUTH, [115] = SOUTH, + [116] = SOUTH, [117] = SOUTH, [118] = SOUTH, [119] = SOUTH, + [120] = SOUTH, [121] = SOUTH, [122] = SOUTH, [123] = SOUTH, + [124] = SOUTH, [125] = WEST, [126] = SOUTH, [127] = SOUTH, + [128] = SOUTH, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH, + [132] = SOUTH, [133] = SOUTH, [134] = SOUTH, [135] = SOUTH, + [136] = SOUTH, [137] = SOUTH, [138] = SOUTH, [139] = SOUTH, + [140] = SOUTH, [141] = SOUTH, [142] = SOUTH, [143] = SOUTH, + [144] = SOUTH, [145] = SOUTH, [146] = SOUTH, [147] = SOUTH, + [148] = SOUTH, [149] = SOUTH, [150] = SOUTH, [151] = SOUTH, + [152] = SOUTH, [153] = SOUTH, [154] = SOUTH, [155] = WEST, + [156] = WEST, [157] = WEST, [158] = WEST, [159] = WEST, + [160] = WEST, [161] = WEST, [162] = WEST, [163] = WEST, + [164] = WEST, [165] = WEST, [166] = WEST, [167] = WEST, + [168] = WEST, [169] = NORTH, [170] = NORTH, [171] = NORTH, + [172] = NORTH, [173] = NORTH, [174] = NORTH, + // special pins + [175] = 0, [176] = 0, [177] = 0, [178] = 0, +}; + +static const char *sm8150_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm8150_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + return pin_name; +} + +static unsigned int sm8150_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data sm8150_data = { + .pin_data = { + .pin_offsets = sm8150_pin_offsets, + .pin_count = ARRAY_SIZE(sm8150_pin_offsets), + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm8150_get_function_name, + .get_function_mux = sm8150_get_function_mux, + .get_pin_name = sm8150_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,sm8150-pinctrl", .data = (ulong)&sm8150_data }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(pinctrl_sm8150) = { + .name = "pinctrl_sm8150", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +};
Hi Julius,
Thanks for the patch!
On 09/09/2024 17:53, Julius Lehmann wrote:
Add pinctrl and GPIO driver for SM8150. Driver code is based on the similar U-Boot drivers. All constants are taken from the corresponding Linux driver. This drivers differs from the similar U-Boot drivers, because SM8150 SoC have different function IDs for the same functions on different pins.
Co-authored-by: Volodymyr Babchuk volodymyr_babchuk@epam.com Signed-off-by: Julius Lehmann lehmanju@devpi.de
drivers/pinctrl/qcom/Kconfig | 8 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8150.c | 119 ++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index b326fa8514..501939f783 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -74,6 +74,14 @@ config PINCTRL_QCOM_SM8650 select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC,
as well as the associated GPIO driver.+config PINCTRL_QCOM_SM8150
- bool "Qualcomm SM8150 GCC"
- select PINCTRL_QCOM
- help
Say Y here to enable support for pinctrl on the Snapdragon SM8150 SoC,as well as the associated GPIO driver.endmenu
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4f1d96787b..cc3660a576 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_QCOM_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o +obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c new file mode 100644 index 0000000000..c3af3448f6 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: BSD-3-Clause +/*
- Qualcomm SM8150 pinctrl and GPIO driver
- Volodymyr Babchuk volodymyr_babchuk@epam.com
- Copyright (c) 2024 EPAM Systems.
- (C) Copyright 2024 Julius Lehmann lehmanju@devpi.de
- Based on similar U-Boot drivers. Constants were taken from the Linux driver
- */
+#include <dm.h>
+#include "pinctrl-qcom.h"
+#define WEST 0x00100000 +#define EAST 0x00500000 +#define NORTH 0x00900000 +#define SOUTH 0x00D00000
+#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const struct pinctrl_function msm_pinctrl_functions[] = { { "qup2", 1 },
{ "gpio", 0 },{ "sdc4", 0 } };+static const unsigned int sm8150_pin_offsets[] = {
- [0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH,
- [4] = SOUTH, [5] = SOUTH, [6] = SOUTH, [7] = SOUTH,
- [8] = NORTH, [9] = NORTH, [10] = NORTH, [11] = NORTH,
- [12] = NORTH, [13] = NORTH, [14] = NORTH, [15] = NORTH,
- [16] = NORTH, [17] = NORTH, [18] = NORTH, [19] = NORTH,
- [20] = NORTH, [21] = EAST, [22] = EAST, [23] = EAST,
- [24] = EAST, [25] = EAST, [26] = EAST, [27] = EAST,
- [28] = EAST, [29] = EAST, [30] = EAST, [31] = NORTH,
- [32] = NORTH, [33] = NORTH, [34] = NORTH, [35] = NORTH,
- [36] = NORTH, [37] = NORTH, [38] = SOUTH, [39] = NORTH,
- [40] = NORTH, [41] = NORTH, [42] = NORTH, [43] = EAST,
- [44] = EAST, [45] = EAST, [46] = EAST, [47] = EAST,
- [48] = EAST, [49] = EAST, [50] = EAST, [51] = SOUTH,
- [52] = SOUTH, [53] = SOUTH, [54] = SOUTH, [55] = SOUTH,
- [56] = SOUTH, [57] = SOUTH, [58] = SOUTH, [59] = SOUTH,
- [60] = SOUTH, [61] = SOUTH, [62] = SOUTH, [63] = SOUTH,
- [64] = SOUTH, [65] = SOUTH, [66] = SOUTH, [67] = SOUTH,
- [68] = SOUTH, [69] = SOUTH, [70] = SOUTH, [71] = SOUTH,
- [72] = SOUTH, [73] = SOUTH, [74] = SOUTH, [75] = SOUTH,
- [76] = SOUTH, [77] = SOUTH, [78] = SOUTH, [79] = SOUTH,
- [80] = SOUTH, [81] = SOUTH, [82] = SOUTH, [83] = NORTH,
- [84] = NORTH, [85] = NORTH, [86] = NORTH, [87] = EAST,
- [88] = NORTH, [89] = NORTH, [90] = NORTH, [91] = NORTH,
- [92] = NORTH, [93] = NORTH, [94] = NORTH, [95] = NORTH,
- [96] = NORTH, [97] = NORTH, [98] = SOUTH, [99] = SOUTH,
- [100] = SOUTH, [101] = SOUTH, [102] = NORTH, [103] = NORTH,
- [104] = NORTH, [105] = WEST, [106] = WEST, [107] = WEST,
- [108] = WEST, [109] = WEST, [110] = WEST, [111] = WEST,
- [112] = WEST, [113] = WEST, [114] = SOUTH, [115] = SOUTH,
- [116] = SOUTH, [117] = SOUTH, [118] = SOUTH, [119] = SOUTH,
- [120] = SOUTH, [121] = SOUTH, [122] = SOUTH, [123] = SOUTH,
- [124] = SOUTH, [125] = WEST, [126] = SOUTH, [127] = SOUTH,
- [128] = SOUTH, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH,
- [132] = SOUTH, [133] = SOUTH, [134] = SOUTH, [135] = SOUTH,
- [136] = SOUTH, [137] = SOUTH, [138] = SOUTH, [139] = SOUTH,
- [140] = SOUTH, [141] = SOUTH, [142] = SOUTH, [143] = SOUTH,
- [144] = SOUTH, [145] = SOUTH, [146] = SOUTH, [147] = SOUTH,
- [148] = SOUTH, [149] = SOUTH, [150] = SOUTH, [151] = SOUTH,
- [152] = SOUTH, [153] = SOUTH, [154] = SOUTH, [155] = WEST,
- [156] = WEST, [157] = WEST, [158] = WEST, [159] = WEST,
- [160] = WEST, [161] = WEST, [162] = WEST, [163] = WEST,
- [164] = WEST, [165] = WEST, [166] = WEST, [167] = WEST,
- [168] = WEST, [169] = NORTH, [170] = NORTH, [171] = NORTH,
- [172] = NORTH, [173] = NORTH, [174] = NORTH,
- // special pins
- [175] = 0, [176] = 0, [177] = 0, [178] = 0,
We have better support for special pins now, you can remove these 0 entries and set .special_pins_start = 175 in pin_data below.
Kind regards,
+};
+static const char *sm8150_get_function_name(struct udevice *dev,
unsigned int selector)+{
- return msm_pinctrl_functions[selector].name;
+}
+static const char *sm8150_get_pin_name(struct udevice *dev,
unsigned int selector)+{
- snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
- return pin_name;
+}
+static unsigned int sm8150_get_function_mux(__maybe_unused unsigned int pin,
unsigned int selector)+{
- return msm_pinctrl_functions[selector].val;
+}
+static struct msm_pinctrl_data sm8150_data = {
- .pin_data = {
.pin_offsets = sm8150_pin_offsets,.pin_count = ARRAY_SIZE(sm8150_pin_offsets),- },
- .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
- .get_function_name = sm8150_get_function_name,
- .get_function_mux = sm8150_get_function_mux,
- .get_pin_name = sm8150_get_pin_name,
+};
+static const struct udevice_id msm_pinctrl_ids[] = {
- { .compatible = "qcom,sm8150-pinctrl", .data = (ulong)&sm8150_data },
- { /* Sentinel */ }
+};
+U_BOOT_DRIVER(pinctrl_sm8150) = {
- .name = "pinctrl_sm8150",
- .id = UCLASS_NOP,
- .of_match = msm_pinctrl_ids,
- .ops = &msm_pinctrl_ops,
- .bind = msm_pinctrl_bind,
+};
On 10/09/2024 14:05, Caleb Connolly wrote:
Hi Julius,
Thanks for the patch!
On 09/09/2024 17:53, Julius Lehmann wrote:
Add pinctrl and GPIO driver for SM8150. Driver code is based on the similar U-Boot drivers. All constants are taken from the corresponding Linux driver. This drivers differs from the similar U-Boot drivers, because SM8150 SoC have different function IDs for the same functions on different pins.
Co-authored-by: Volodymyr Babchuk volodymyr_babchuk@epam.com Signed-off-by: Julius Lehmann lehmanju@devpi.de
drivers/pinctrl/qcom/Kconfig | 8 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8150.c | 119 ++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index b326fa8514..501939f783 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -74,6 +74,14 @@ config PINCTRL_QCOM_SM8650 select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC,
as well as the associated GPIO driver.+config PINCTRL_QCOM_SM8150
bool "Qualcomm SM8150 GCC"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the Snapdragon SM8150 SoC,as well as the associated GPIO driver.endmenu
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4f1d96787b..cc3660a576 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_QCOM_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o +obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c new file mode 100644 index 0000000000..c3af3448f6 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: BSD-3-Clause +/*
- Qualcomm SM8150 pinctrl and GPIO driver
- Volodymyr Babchuk volodymyr_babchuk@epam.com
- Copyright (c) 2024 EPAM Systems.
- (C) Copyright 2024 Julius Lehmann lehmanju@devpi.de
- Based on similar U-Boot drivers. Constants were taken from the Linux driver
- */
+#include <dm.h>
+#include "pinctrl-qcom.h"
+#define WEST 0x00100000 +#define EAST 0x00500000 +#define NORTH 0x00900000 +#define SOUTH 0x00D00000
+#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const struct pinctrl_function msm_pinctrl_functions[] = { { "qup2", 1 },
{ "gpio", 0 },{ "sdc4", 0 } };+static const unsigned int sm8150_pin_offsets[] = {
- [0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH,
- [4] = SOUTH, [5] = SOUTH, [6] = SOUTH, [7] = SOUTH,
- [8] = NORTH, [9] = NORTH, [10] = NORTH, [11] = NORTH,
- [12] = NORTH, [13] = NORTH, [14] = NORTH, [15] = NORTH,
- [16] = NORTH, [17] = NORTH, [18] = NORTH, [19] = NORTH,
- [20] = NORTH, [21] = EAST, [22] = EAST, [23] = EAST,
- [24] = EAST, [25] = EAST, [26] = EAST, [27] = EAST,
- [28] = EAST, [29] = EAST, [30] = EAST, [31] = NORTH,
- [32] = NORTH, [33] = NORTH, [34] = NORTH, [35] = NORTH,
- [36] = NORTH, [37] = NORTH, [38] = SOUTH, [39] = NORTH,
- [40] = NORTH, [41] = NORTH, [42] = NORTH, [43] = EAST,
- [44] = EAST, [45] = EAST, [46] = EAST, [47] = EAST,
- [48] = EAST, [49] = EAST, [50] = EAST, [51] = SOUTH,
- [52] = SOUTH, [53] = SOUTH, [54] = SOUTH, [55] = SOUTH,
- [56] = SOUTH, [57] = SOUTH, [58] = SOUTH, [59] = SOUTH,
- [60] = SOUTH, [61] = SOUTH, [62] = SOUTH, [63] = SOUTH,
- [64] = SOUTH, [65] = SOUTH, [66] = SOUTH, [67] = SOUTH,
- [68] = SOUTH, [69] = SOUTH, [70] = SOUTH, [71] = SOUTH,
- [72] = SOUTH, [73] = SOUTH, [74] = SOUTH, [75] = SOUTH,
- [76] = SOUTH, [77] = SOUTH, [78] = SOUTH, [79] = SOUTH,
- [80] = SOUTH, [81] = SOUTH, [82] = SOUTH, [83] = NORTH,
- [84] = NORTH, [85] = NORTH, [86] = NORTH, [87] = EAST,
- [88] = NORTH, [89] = NORTH, [90] = NORTH, [91] = NORTH,
- [92] = NORTH, [93] = NORTH, [94] = NORTH, [95] = NORTH,
- [96] = NORTH, [97] = NORTH, [98] = SOUTH, [99] = SOUTH,
- [100] = SOUTH, [101] = SOUTH, [102] = NORTH, [103] = NORTH,
- [104] = NORTH, [105] = WEST, [106] = WEST, [107] = WEST,
- [108] = WEST, [109] = WEST, [110] = WEST, [111] = WEST,
- [112] = WEST, [113] = WEST, [114] = SOUTH, [115] = SOUTH,
- [116] = SOUTH, [117] = SOUTH, [118] = SOUTH, [119] = SOUTH,
- [120] = SOUTH, [121] = SOUTH, [122] = SOUTH, [123] = SOUTH,
- [124] = SOUTH, [125] = WEST, [126] = SOUTH, [127] = SOUTH,
- [128] = SOUTH, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH,
- [132] = SOUTH, [133] = SOUTH, [134] = SOUTH, [135] = SOUTH,
- [136] = SOUTH, [137] = SOUTH, [138] = SOUTH, [139] = SOUTH,
- [140] = SOUTH, [141] = SOUTH, [142] = SOUTH, [143] = SOUTH,
- [144] = SOUTH, [145] = SOUTH, [146] = SOUTH, [147] = SOUTH,
- [148] = SOUTH, [149] = SOUTH, [150] = SOUTH, [151] = SOUTH,
- [152] = SOUTH, [153] = SOUTH, [154] = SOUTH, [155] = WEST,
- [156] = WEST, [157] = WEST, [158] = WEST, [159] = WEST,
- [160] = WEST, [161] = WEST, [162] = WEST, [163] = WEST,
- [164] = WEST, [165] = WEST, [166] = WEST, [167] = WEST,
- [168] = WEST, [169] = NORTH, [170] = NORTH, [171] = NORTH,
- [172] = NORTH, [173] = NORTH, [174] = NORTH,
- // special pins
- [175] = 0, [176] = 0, [177] = 0, [178] = 0,
We have better support for special pins now, you can remove these 0 entries and set .special_pins_start = 175 in pin_data below.
You can look at the sm8250 patch at https://lore.kernel.org/all/20240910-topic-sm8x50-msm-gpio-special-pins-sm82...
Kind regards,
+};
+static const char *sm8150_get_function_name(struct udevice *dev,
unsigned int selector)+{
- return msm_pinctrl_functions[selector].name;
+}
+static const char *sm8150_get_pin_name(struct udevice *dev,
unsigned int selector)+{
- snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
- return pin_name;
+}
+static unsigned int sm8150_get_function_mux(__maybe_unused unsigned int pin,
unsigned int selector)+{
- return msm_pinctrl_functions[selector].val;
+}
+static struct msm_pinctrl_data sm8150_data = {
- .pin_data = {
.pin_offsets = sm8150_pin_offsets,.pin_count = ARRAY_SIZE(sm8150_pin_offsets),- },
- .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
- .get_function_name = sm8150_get_function_name,
- .get_function_mux = sm8150_get_function_mux,
- .get_pin_name = sm8150_get_pin_name,
+};
+static const struct udevice_id msm_pinctrl_ids[] = {
- { .compatible = "qcom,sm8150-pinctrl", .data = (ulong)&sm8150_data },
- { /* Sentinel */ }
+};
+U_BOOT_DRIVER(pinctrl_sm8150) = {
- .name = "pinctrl_sm8150",
- .id = UCLASS_NOP,
- .of_match = msm_pinctrl_ids,
- .ops = &msm_pinctrl_ops,
- .bind = msm_pinctrl_bind,
+};
Hi Neil and Caleb,
thank you for taking a look at my patch.
On 10.09.24 14:07, Neil Armstrong wrote:
On 10/09/2024 14:05, Caleb Connolly wrote:
Hi Julius,
Thanks for the patch!
On 09/09/2024 17:53, Julius Lehmann wrote:
Add pinctrl and GPIO driver for SM8150. Driver code is based on the similar U-Boot drivers. All constants are taken from the corresponding Linux driver. This drivers differs from the similar U-Boot drivers, because SM8150 SoC have different function IDs for the same functions on different pins.
Co-authored-by: Volodymyr Babchuk volodymyr_babchuk@epam.com Signed-off-by: Julius Lehmann lehmanju@devpi.de
drivers/pinctrl/qcom/Kconfig | 8 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8150.c | 119 ++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index b326fa8514..501939f783 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -74,6 +74,14 @@ config PINCTRL_QCOM_SM8650 select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC, + as well as the associated GPIO driver.
+config PINCTRL_QCOM_SM8150 + bool "Qualcomm SM8150 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM8150 SoC, + as well as the associated GPIO driver. endmenu diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4f1d96787b..cc3660a576 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_QCOM_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o +obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c new file mode 100644 index 0000000000..c3af3448f6 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: BSD-3-Clause +/*
- Qualcomm SM8150 pinctrl and GPIO driver
- Volodymyr Babchuk volodymyr_babchuk@epam.com
- Copyright (c) 2024 EPAM Systems.
- (C) Copyright 2024 Julius Lehmann lehmanju@devpi.de
- Based on similar U-Boot drivers. Constants were taken from the
Linux driver
- */
+#include <dm.h>
+#include "pinctrl-qcom.h"
+#define WEST 0x00100000 +#define EAST 0x00500000 +#define NORTH 0x00900000 +#define SOUTH 0x00D00000
+#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const struct pinctrl_function msm_pinctrl_functions[] = { { "qup2", 1 }, + { "gpio", 0 }, + { "sdc4", 0 } };
+static const unsigned int sm8150_pin_offsets[] = { + [0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH, + [4] = SOUTH, [5] = SOUTH, [6] = SOUTH, [7] = SOUTH, + [8] = NORTH, [9] = NORTH, [10] = NORTH, [11] = NORTH, + [12] = NORTH, [13] = NORTH, [14] = NORTH, [15] = NORTH, + [16] = NORTH, [17] = NORTH, [18] = NORTH, [19] = NORTH, + [20] = NORTH, [21] = EAST, [22] = EAST, [23] = EAST, + [24] = EAST, [25] = EAST, [26] = EAST, [27] = EAST, + [28] = EAST, [29] = EAST, [30] = EAST, [31] = NORTH, + [32] = NORTH, [33] = NORTH, [34] = NORTH, [35] = NORTH, + [36] = NORTH, [37] = NORTH, [38] = SOUTH, [39] = NORTH, + [40] = NORTH, [41] = NORTH, [42] = NORTH, [43] = EAST, + [44] = EAST, [45] = EAST, [46] = EAST, [47] = EAST, + [48] = EAST, [49] = EAST, [50] = EAST, [51] = SOUTH, + [52] = SOUTH, [53] = SOUTH, [54] = SOUTH, [55] = SOUTH, + [56] = SOUTH, [57] = SOUTH, [58] = SOUTH, [59] = SOUTH, + [60] = SOUTH, [61] = SOUTH, [62] = SOUTH, [63] = SOUTH, + [64] = SOUTH, [65] = SOUTH, [66] = SOUTH, [67] = SOUTH, + [68] = SOUTH, [69] = SOUTH, [70] = SOUTH, [71] = SOUTH, + [72] = SOUTH, [73] = SOUTH, [74] = SOUTH, [75] = SOUTH, + [76] = SOUTH, [77] = SOUTH, [78] = SOUTH, [79] = SOUTH, + [80] = SOUTH, [81] = SOUTH, [82] = SOUTH, [83] = NORTH, + [84] = NORTH, [85] = NORTH, [86] = NORTH, [87] = EAST, + [88] = NORTH, [89] = NORTH, [90] = NORTH, [91] = NORTH, + [92] = NORTH, [93] = NORTH, [94] = NORTH, [95] = NORTH, + [96] = NORTH, [97] = NORTH, [98] = SOUTH, [99] = SOUTH, + [100] = SOUTH, [101] = SOUTH, [102] = NORTH, [103] = NORTH, + [104] = NORTH, [105] = WEST, [106] = WEST, [107] = WEST, + [108] = WEST, [109] = WEST, [110] = WEST, [111] = WEST, + [112] = WEST, [113] = WEST, [114] = SOUTH, [115] = SOUTH, + [116] = SOUTH, [117] = SOUTH, [118] = SOUTH, [119] = SOUTH, + [120] = SOUTH, [121] = SOUTH, [122] = SOUTH, [123] = SOUTH, + [124] = SOUTH, [125] = WEST, [126] = SOUTH, [127] = SOUTH, + [128] = SOUTH, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH, + [132] = SOUTH, [133] = SOUTH, [134] = SOUTH, [135] = SOUTH, + [136] = SOUTH, [137] = SOUTH, [138] = SOUTH, [139] = SOUTH, + [140] = SOUTH, [141] = SOUTH, [142] = SOUTH, [143] = SOUTH, + [144] = SOUTH, [145] = SOUTH, [146] = SOUTH, [147] = SOUTH, + [148] = SOUTH, [149] = SOUTH, [150] = SOUTH, [151] = SOUTH, + [152] = SOUTH, [153] = SOUTH, [154] = SOUTH, [155] = WEST, + [156] = WEST, [157] = WEST, [158] = WEST, [159] = WEST, + [160] = WEST, [161] = WEST, [162] = WEST, [163] = WEST, + [164] = WEST, [165] = WEST, [166] = WEST, [167] = WEST, + [168] = WEST, [169] = NORTH, [170] = NORTH, [171] = NORTH, + [172] = NORTH, [173] = NORTH, [174] = NORTH, + // special pins + [175] = 0, [176] = 0, [177] = 0, [178] = 0,
We have better support for special pins now, you can remove these 0 entries and set .special_pins_start = 175 in pin_data below.
You can look at the sm8250 patch at https://lore.kernel.org/all/20240910-topic-sm8x50-msm-gpio-special-pins-sm82...
I took a look at sm8550/sm8660 and noticed that the pin_offsets array is completely missing. Is it not required at all (if special_pins_start and special_pins_data are used)?
For v2 I will also try to integrate UFS and SDC pin functions, just like in sm8550/sm8660.
Kind regards,
+};
+static const char *sm8150_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +}
+static const char *sm8150_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + return pin_name; +}
+static unsigned int sm8150_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +}
+static struct msm_pinctrl_data sm8150_data = { + .pin_data = { + .pin_offsets = sm8150_pin_offsets, + .pin_count = ARRAY_SIZE(sm8150_pin_offsets), + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm8150_get_function_name, + .get_function_mux = sm8150_get_function_mux, + .get_pin_name = sm8150_get_pin_name, +};
+static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,sm8150-pinctrl", .data = (ulong)&sm8150_data }, + { /* Sentinel */ } +};
+U_BOOT_DRIVER(pinctrl_sm8150) = { + .name = "pinctrl_sm8150", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +};
On 10/09/2024 18:01, Julius Lehmann wrote:
Hi Neil and Caleb,
thank you for taking a look at my patch.
On 10.09.24 14:07, Neil Armstrong wrote:
On 10/09/2024 14:05, Caleb Connolly wrote:
Hi Julius,
Thanks for the patch!
On 09/09/2024 17:53, Julius Lehmann wrote:
Add pinctrl and GPIO driver for SM8150. Driver code is based on the similar U-Boot drivers. All constants are taken from the corresponding Linux driver. This drivers differs from the similar U-Boot drivers, because SM8150 SoC have different function IDs for the same functions on different pins.
Co-authored-by: Volodymyr Babchuk volodymyr_babchuk@epam.com Signed-off-by: Julius Lehmann lehmanju@devpi.de
drivers/pinctrl/qcom/Kconfig | 8 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8150.c | 119 ++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index b326fa8514..501939f783 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -74,6 +74,14 @@ config PINCTRL_QCOM_SM8650 select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC, + as well as the associated GPIO driver.
+config PINCTRL_QCOM_SM8150 + bool "Qualcomm SM8150 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM8150 SoC, + as well as the associated GPIO driver. endmenu diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4f1d96787b..cc3660a576 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_QCOM_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o +obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c new file mode 100644 index 0000000000..c3af3448f6 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: BSD-3-Clause +/*
- Qualcomm SM8150 pinctrl and GPIO driver
- Volodymyr Babchuk volodymyr_babchuk@epam.com
- Copyright (c) 2024 EPAM Systems.
- (C) Copyright 2024 Julius Lehmann lehmanju@devpi.de
- Based on similar U-Boot drivers. Constants were taken from the Linux driver
- */
+#include <dm.h>
+#include "pinctrl-qcom.h"
+#define WEST 0x00100000 +#define EAST 0x00500000 +#define NORTH 0x00900000 +#define SOUTH 0x00D00000
+#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const struct pinctrl_function msm_pinctrl_functions[] = { { "qup2", 1 }, + { "gpio", 0 }, + { "sdc4", 0 } };
+static const unsigned int sm8150_pin_offsets[] = { + [0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH, + [4] = SOUTH, [5] = SOUTH, [6] = SOUTH, [7] = SOUTH, + [8] = NORTH, [9] = NORTH, [10] = NORTH, [11] = NORTH, + [12] = NORTH, [13] = NORTH, [14] = NORTH, [15] = NORTH, + [16] = NORTH, [17] = NORTH, [18] = NORTH, [19] = NORTH, + [20] = NORTH, [21] = EAST, [22] = EAST, [23] = EAST, + [24] = EAST, [25] = EAST, [26] = EAST, [27] = EAST, + [28] = EAST, [29] = EAST, [30] = EAST, [31] = NORTH, + [32] = NORTH, [33] = NORTH, [34] = NORTH, [35] = NORTH, + [36] = NORTH, [37] = NORTH, [38] = SOUTH, [39] = NORTH, + [40] = NORTH, [41] = NORTH, [42] = NORTH, [43] = EAST, + [44] = EAST, [45] = EAST, [46] = EAST, [47] = EAST, + [48] = EAST, [49] = EAST, [50] = EAST, [51] = SOUTH, + [52] = SOUTH, [53] = SOUTH, [54] = SOUTH, [55] = SOUTH, + [56] = SOUTH, [57] = SOUTH, [58] = SOUTH, [59] = SOUTH, + [60] = SOUTH, [61] = SOUTH, [62] = SOUTH, [63] = SOUTH, + [64] = SOUTH, [65] = SOUTH, [66] = SOUTH, [67] = SOUTH, + [68] = SOUTH, [69] = SOUTH, [70] = SOUTH, [71] = SOUTH, + [72] = SOUTH, [73] = SOUTH, [74] = SOUTH, [75] = SOUTH, + [76] = SOUTH, [77] = SOUTH, [78] = SOUTH, [79] = SOUTH, + [80] = SOUTH, [81] = SOUTH, [82] = SOUTH, [83] = NORTH, + [84] = NORTH, [85] = NORTH, [86] = NORTH, [87] = EAST, + [88] = NORTH, [89] = NORTH, [90] = NORTH, [91] = NORTH, + [92] = NORTH, [93] = NORTH, [94] = NORTH, [95] = NORTH, + [96] = NORTH, [97] = NORTH, [98] = SOUTH, [99] = SOUTH, + [100] = SOUTH, [101] = SOUTH, [102] = NORTH, [103] = NORTH, + [104] = NORTH, [105] = WEST, [106] = WEST, [107] = WEST, + [108] = WEST, [109] = WEST, [110] = WEST, [111] = WEST, + [112] = WEST, [113] = WEST, [114] = SOUTH, [115] = SOUTH, + [116] = SOUTH, [117] = SOUTH, [118] = SOUTH, [119] = SOUTH, + [120] = SOUTH, [121] = SOUTH, [122] = SOUTH, [123] = SOUTH, + [124] = SOUTH, [125] = WEST, [126] = SOUTH, [127] = SOUTH, + [128] = SOUTH, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH, + [132] = SOUTH, [133] = SOUTH, [134] = SOUTH, [135] = SOUTH, + [136] = SOUTH, [137] = SOUTH, [138] = SOUTH, [139] = SOUTH, + [140] = SOUTH, [141] = SOUTH, [142] = SOUTH, [143] = SOUTH, + [144] = SOUTH, [145] = SOUTH, [146] = SOUTH, [147] = SOUTH, + [148] = SOUTH, [149] = SOUTH, [150] = SOUTH, [151] = SOUTH, + [152] = SOUTH, [153] = SOUTH, [154] = SOUTH, [155] = WEST, + [156] = WEST, [157] = WEST, [158] = WEST, [159] = WEST, + [160] = WEST, [161] = WEST, [162] = WEST, [163] = WEST, + [164] = WEST, [165] = WEST, [166] = WEST, [167] = WEST, + [168] = WEST, [169] = NORTH, [170] = NORTH, [171] = NORTH, + [172] = NORTH, [173] = NORTH, [174] = NORTH, + // special pins + [175] = 0, [176] = 0, [177] = 0, [178] = 0,
We have better support for special pins now, you can remove these 0 entries and set .special_pins_start = 175 in pin_data below.
You can look at the sm8250 patch at https://lore.kernel.org/all/20240910-topic-sm8x50-msm-gpio-special-pins-sm82...
I took a look at sm8550/sm8660 and noticed that the pin_offsets array is completely missing. Is it not required at all (if special_pins_start and special_pins_data are used)?
Yeah for newer platforms, the offsets are not required at all.
For v2 I will also try to integrate UFS and SDC pin functions, just like in sm8550/sm8660.
Kind regards,
+};
+static const char *sm8150_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +}
+static const char *sm8150_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + return pin_name; +}
+static unsigned int sm8150_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +}
+static struct msm_pinctrl_data sm8150_data = { + .pin_data = { + .pin_offsets = sm8150_pin_offsets, + .pin_count = ARRAY_SIZE(sm8150_pin_offsets), + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm8150_get_function_name, + .get_function_mux = sm8150_get_function_mux, + .get_pin_name = sm8150_get_pin_name, +};
+static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,sm8150-pinctrl", .data = (ulong)&sm8150_data }, + { /* Sentinel */ } +};
+U_BOOT_DRIVER(pinctrl_sm8150) = { + .name = "pinctrl_sm8150", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +};
Enable clk and pinctrl for sm8150
Signed-off-by: Julius Lehmann lehmanju@devpi.de
---
configs/qcom_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 419e969e5d..03587d2dc7 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -49,6 +49,7 @@ CONFIG_CLK_QCOM_SM6115=y CONFIG_CLK_QCOM_SM8250=y CONFIG_CLK_QCOM_SM8550=y CONFIG_CLK_QCOM_SM8650=y +CONFIG_CLK_QCOM_SM8150=y CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_I2C=y @@ -87,6 +88,7 @@ CONFIG_PINCTRL_QCOM_SM6115=y CONFIG_PINCTRL_QCOM_SM8250=y CONFIG_PINCTRL_QCOM_SM8550=y CONFIG_PINCTRL_QCOM_SM8650=y +CONFIG_PINCTRL_QCOM_SM8150=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_DM_REGULATOR=y
On 09/09/2024 17:53, Julius Lehmann wrote:
Enable clk and pinctrl for sm8150
Signed-off-by: Julius Lehmann lehmanju@devpi.de
Reviewed-by: Caleb Connolly caleb.connolly@linaro.org
configs/qcom_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 419e969e5d..03587d2dc7 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -49,6 +49,7 @@ CONFIG_CLK_QCOM_SM6115=y CONFIG_CLK_QCOM_SM8250=y CONFIG_CLK_QCOM_SM8550=y CONFIG_CLK_QCOM_SM8650=y +CONFIG_CLK_QCOM_SM8150=y CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_I2C=y @@ -87,6 +88,7 @@ CONFIG_PINCTRL_QCOM_SM6115=y CONFIG_PINCTRL_QCOM_SM8250=y CONFIG_PINCTRL_QCOM_SM8550=y CONFIG_PINCTRL_QCOM_SM8650=y +CONFIG_PINCTRL_QCOM_SM8150=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_DM_REGULATOR=y
participants (4)
-
Caleb Connolly -
Julius Lehmann -
Neil Armstrong -
neil.armstrong＠linaro.org