[U-Boot-Users] BITBANGMII implementation for MPC8548 eTSEC && 88E1111
Hi all,
I'd like to implemente BITBANGMII for MPC8548 with a external Marvell 88E1111 PHY as RGMII interface. The reason was that this board's MII control lines MDC was broken as HIGH level always(Sure, it worked right with tsec driver). So u-boot reported no PHY found - Bad news:-(
I followed EP8248 BITBANGMII way to use CPLD to implementate BITBANGMII but couldn't read PHY register correctly - PHY ID still unknown.
I wonder whether eTSEC controller can use BITBANGMII way to work with outside PHY. Seems that no MII support eTSEC driver not functional.
<board>.h #define CONFIG_BITBANGMII
#define MDIO_PORT 0 /* Not used - implemented in BCSR */ #define MDIO_ACTIVE \ (*(vu_char *)(CFG_BCSR + 83) |= 0x01) #define MDIO_TRISTATE \ (*(vu_char *)(CFG_BCSR + 83) &= 0xFE) #define MDIO_READ \ ((*(vu_char *)(CFG_BCSR + 83) & 1) != 0)
#define MDIO(bit) \ if(bit) *(vu_char *)(CFG_BCSR + 83) |= 0x01; \ else *(vu_char *)(CFG_BCSR + 83) &= 0xFE
#define MDC(bit) \ if(bit) *(vu_char *)(CFG_BCSR + 83) |= 0x02; \ else *(vu_char *)(CFG_BCSR + 83) &= 0xFD #define MIIDELAY udelay(1)
drivers/tsec.c uint read_phy_reg(struct tsec_private *priv, uint regnum) { uint value; volatile tsec_t *regbase = priv->phyregs; uint phyid = priv->phyaddr;
+#ifndef CONFIG_BITBANGMII /* Put the address of the phy, and the register * number into MIIMADD */ regbase->miimadd = (phyid << 8) | regnum; @@ -281,6 +292,11 @@ uint read_phy_reg(struct tsec_private *p
/* Grab the value read from the PHY */ value = regbase->miimstat; +#else bb_miiphy_read (NULL, phyid, regnum, &value); +#endif /* CONFIG_BITBANGMII */
Am I on the right track?
Thanks in advance,
Sam
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Sam,
On Tue, 2007-03-06 at 21:19 +0800, Sam Song wrote:
Hi all,
I'd like to implemente BITBANGMII for MPC8548 with a external Marvell 88E1111 PHY as RGMII interface. The reason was that this board's MII control lines MDC was broken as HIGH level always(Sure, it worked right with tsec driver). So u-boot reported no PHY found - Bad news:-(
I followed EP8248 BITBANGMII way to use CPLD to implementate BITBANGMII but couldn't read PHY register correctly - PHY ID still unknown.
Time to reach into your engineering tool bag.
I wonder whether eTSEC controller can use BITBANGMII way to work with outside PHY. Seems that no MII support eTSEC driver not functional.
MDIO comms are always (well, maybe not always) done in software. By this I mean that while the MDIO controllers are part of the Ethernet controllers, coupling is loose. You should be able to bitbang this provided the physical wires exist between the CPLD and the PHY. I guess white-wiring the TSEC's MDC line isn't an option?
<board>.h #define CONFIG_BITBANGMII
#define MDIO_PORT 0 /* Not used - implemented in BCSR */ #define MDIO_ACTIVE \ (*(vu_char *)(CFG_BCSR + 83) |= 0x01) #define MDIO_TRISTATE \ (*(vu_char *)(CFG_BCSR + 83) &= 0xFE) #define MDIO_READ \ ((*(vu_char *)(CFG_BCSR + 83) & 1) != 0)
#define MDIO(bit) \ if(bit) *(vu_char *)(CFG_BCSR + 83) |= 0x01; \ else *(vu_char *)(CFG_BCSR + 83) &= 0xFE
#define MDC(bit) \ if(bit) *(vu_char *)(CFG_BCSR + 83) |= 0x02; \ else *(vu_char *)(CFG_BCSR + 83) &= 0xFD #define MIIDELAY udelay(1)
Stylistically, this leaves a lot to be desired, but if register 83 (better to use hex here) really maps to the MDC and MDIO pins, it should work.
drivers/tsec.c
<SNIP>
Am I on the right track?
Before messing with the TSEC driver, try talking with the PHY using the 'mii' U-boot commands. Also, pull out your oscilloscope and check that the lines are toggling as you want. Once you're confident Bitbanged-MII works, integrate it into TSEC.
regards, Ben
Hi Ben,
Ben Warren bwarren@qstreams.com wrote:
Time to reach into your engineering tool bag.
Indead!
controllers, coupling is loose. You should be able to bitbang this provided the physical wires exist between the CPLD and the PHY. I guess white-wiring the TSEC's MDC line isn't an option?
I did wire two CPLD GPIOs to MDC/MDIO of PHY.
Stylistically, this leaves a lot to be desired, but if register 83 (better to use hex here) really maps to the MDC and MDIO pins, it should work.
Good catch. I did mistake 0x83 for 83:-(
Am I on the right track?
Before messing with the TSEC driver, try talking with the PHY using the 'mii' U-boot commands. Also, pull out your oscilloscope and check that the lines are toggling as you want. Once you're confident Bitbanged-MII works, integrate it into TSEC.
This is really a nice debug method. With it, we found that PHY MDIO output HIGH level was too low - less than 1.5V. So CPLD took it as '0' always. We pulled up it to 3.3V via a resistor and changed CPLD internal bank power supply level as 2.5/1.8V but no luck. Now hardware colleagues help us to work out another way to solve it.
As the HIGH-Performance processors comes out, there is an extra workload to debug those broken board besides normal development. No easy to drop it as before. Luckily, u-boot's rich features and the poweful resources make it easier than it should be.
Thanks a lot,
Sam
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participants (2)
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Ben Warren -
Sam Song