Signed-off-by: Lukasz Majewski lukma@denx.de --- arch/arm/include/asm/arch-am33xx/cpu.h | 48 +------------------------ arch/arm/include/asm/arch-omap5/cpu.h | 2 ++ arch/arm/include/asm/ti-common/omap_wdt.h | 60 +++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+), 47 deletions(-) create mode 100644 arch/arm/include/asm/ti-common/omap_wdt.h

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index dbed776..54f449f 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -66,29 +66,9 @@ #define PRM_RSTCTRL_RESET 0x01 #define PRM_RSTST_WARM_RESET_MASK 0x232

-/* - * Watchdog: - * Using the prescaler, the OMAP watchdog could go for many - * months before firing. These limits work without scaling, - * with the 60 second default assumed by most tools and docs. - */ -#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */ -#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ -#define TIMER_MARGIN_MIN 1 - -#define PTV 0 /* prescale */ -#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1) -#define WDT_WWPS_PEND_WCLR BIT(0) -#define WDT_WWPS_PEND_WLDR BIT(2) -#define WDT_WWPS_PEND_WTGR BIT(3) -#define WDT_WWPS_PEND_WSPR BIT(4) - -#define WDT_WCLR_PRE BIT(5) -#define WDT_WCLR_PTV_OFF 2 - #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ - +#include <asm/ti-common/omap_wdt.h>

#ifndef CONFIG_AM43XX /* Encapsulating core pll registers */ @@ -422,32 +402,6 @@ struct cm_rtc { unsigned int clkstctrl; /* offset 0x4 */ };

-/* Watchdog timer registers */ -struct wd_timer { - unsigned int resv1[4]; - unsigned int wdtwdsc; /* offset 0x010 */ - unsigned int wdtwdst; /* offset 0x014 */ - unsigned int wdtwisr; /* offset 0x018 */ - unsigned int wdtwier; /* offset 0x01C */ - unsigned int wdtwwer; /* offset 0x020 */ - unsigned int wdtwclr; /* offset 0x024 */ - unsigned int wdtwcrr; /* offset 0x028 */ - unsigned int wdtwldr; /* offset 0x02C */ - unsigned int wdtwtgr; /* offset 0x030 */ - unsigned int wdtwwps; /* offset 0x034 */ - unsigned int resv2[3]; - unsigned int wdtwdly; /* offset 0x044 */ - unsigned int wdtwspr; /* offset 0x048 */ - unsigned int resv3[1]; - unsigned int wdtwqeoi; /* offset 0x050 */ - unsigned int wdtwqstar; /* offset 0x054 */ - unsigned int wdtwqsta; /* offset 0x058 */ - unsigned int wdtwqens; /* offset 0x05C */ - unsigned int wdtwqenc; /* offset 0x060 */ - unsigned int resv4[39]; - unsigned int wdt_unfr; /* offset 0x100 */ -}; - /* Timer 32 bit registers */ struct gptimer { unsigned int tidr; /* offset 0x00 */ diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 683d905..d7c46605 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -18,6 +18,8 @@

#ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ +#include <asm/ti-common/omap_wdt.h> + struct gptimer { u32 tidr; /* 0x00 r */ u8 res1[0xc]; diff --git a/arch/arm/include/asm/ti-common/omap_wdt.h b/arch/arm/include/asm/ti-common/omap_wdt.h new file mode 100644 index 0000000..b9f4c07 --- /dev/null +++ b/arch/arm/include/asm/ti-common/omap_wdt.h @@ -0,0 +1,60 @@ +/* + * omap_wdt.h + * + * OMAP Watchdog header file + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP_WDT_H__ +#define __OMAP_WDT_H__ + +/* + * Watchdog: + * Using the prescaler, the OMAP watchdog could go for many + * months before firing. These limits work without scaling, + * with the 60 second default assumed by most tools and docs. + */ +#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */ +#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ +#define TIMER_MARGIN_MIN 1 + +#define PTV 0 /* prescale */ +#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1) +#define WDT_WWPS_PEND_WCLR BIT(0) +#define WDT_WWPS_PEND_WLDR BIT(2) +#define WDT_WWPS_PEND_WTGR BIT(3) +#define WDT_WWPS_PEND_WSPR BIT(4) + +#define WDT_WCLR_PRE BIT(5) +#define WDT_WCLR_PTV_OFF 2 + +/* Watchdog timer registers */ +struct wd_timer { + unsigned int resv1[4]; + unsigned int wdtwdsc; /* offset 0x010 */ + unsigned int wdtwdst; /* offset 0x014 */ + unsigned int wdtwisr; /* offset 0x018 */ + unsigned int wdtwier; /* offset 0x01C */ + unsigned int wdtwwer; /* offset 0x020 */ + unsigned int wdtwclr; /* offset 0x024 */ + unsigned int wdtwcrr; /* offset 0x028 */ + unsigned int wdtwldr; /* offset 0x02C */ + unsigned int wdtwtgr; /* offset 0x030 */ + unsigned int wdtwwps; /* offset 0x034 */ + unsigned int resv2[3]; + unsigned int wdtwdly; /* offset 0x044 */ + unsigned int wdtwspr; /* offset 0x048 */ + unsigned int resv3[1]; + unsigned int wdtwqeoi; /* offset 0x050 */ + unsigned int wdtwqstar; /* offset 0x054 */ + unsigned int wdtwqsta; /* offset 0x058 */ + unsigned int wdtwqens; /* offset 0x05C */ + unsigned int wdtwqenc; /* offset 0x060 */ + unsigned int resv4[39]; + unsigned int wdt_unfr; /* offset 0x100 */ +}; + +#endif /* __OMAP_WDT_H__ */

The OMAP WDT IP block requires to be stopped before any write to its registers is performed.

This problem has been thoroughly described in Linux kernel:

"watchdog: omap: assert the counter being stopped before reprogramming: SHA1: 530c11d432727c697629ad5f9d00ee8e2864d453

Signed-off-by: Lukasz Majewski lukma@denx.de --- drivers/watchdog/omap_wdt.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-)

diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 7ea4b60..7b1f429 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -81,10 +81,32 @@ static int omap_wdt_set_timeout(unsigned int timeout) return 0; }

+void hw_watchdog_disable(void) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + + /* + * Disable watchdog + */ + writel(0xAAAA, &wdt->wdtwspr); + while (readl(&wdt->wdtwwps) != 0x0) + ; + writel(0x5555, &wdt->wdtwspr); + while (readl(&wdt->wdtwwps) != 0x0) + ; +} + void hw_watchdog_init(void) { struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;

+ /* + * Make sure the watchdog is disabled. This is unfortunately required + * because writing to various registers with the watchdog running has no + * effect. + */ + hw_watchdog_disable(); + /* initialize prescaler */ while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) ; @@ -104,18 +126,3 @@ void hw_watchdog_init(void) while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) ; } - -void hw_watchdog_disable(void) -{ - struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; - - /* - * Disable watchdog - */ - writel(0xAAAA, &wdt->wdtwspr); - while (readl(&wdt->wdtwwps) != 0x0) - ; - writel(0x5555, &wdt->wdtwspr); - while (readl(&wdt->wdtwwps) != 0x0) - ; -}

This patch removes some legacy code inherited from omap4. It is redundant to the code already available in ./drivers/watchdog/omap_wdt.c

The code dates back to 2010: "ARMV7: Add basic support for TI OMAP4" SHA1: d34efc767d26d353e0257042080eec7012e5440f

In contemporary u-boot omap watchdog: - Can be enabled in SPL: TI watchdog is initialized in spl_board_init() (call to hw_watchdog_init)

- Is explicitly disabled before making any changes of its registers

- Is re-enabled in init_func_watchdog_init() in ./common/board_f.c with other architectures.

This patch removes silent watchdog disable on TI platform, which caused lack of wdt protection in u-boot even when it was explicitly enabled (in SPL) with CONFIG_HW_WATCHDOG.

Signed-off-by: Lukasz Majewski lukma@denx.de --- arch/arm/mach-omap2/hwinit-common.c | 27 --------------------------- 1 file changed, 27 deletions(-)

diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index f317293..d6549d3 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -150,7 +150,6 @@ void early_system_init(void) if (warm_reset()) force_emif_self_refresh(); #endif - watchdog_init(); set_mux_conf_regs(); #ifdef CONFIG_SPL_BUILD srcomp_enable(); @@ -181,32 +180,6 @@ int arch_cpu_init_dm(void) }

/* - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - */ -void wait_for_command_complete(struct watchdog *wd_base) -{ - int pending = 1; - do { - pending = readl(&wd_base->wwps); - } while (pending); -} - -/* - * Routine: watchdog_init - * Description: Shut down watch dogs - */ -void watchdog_init(void) -{ - struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; - - writel(WD_UNLOCK1, &wd2_base->wspr); - wait_for_command_complete(wd2_base); - writel(WD_UNLOCK2, &wd2_base->wspr); -} - - -/* * This function finds the SDRAM size available in the system * based on DMM section configurations * This is needed because the size of memory installed may be

After removal of watchdog_init() redundant code from arch/arm/cpu/armv7/omap-common/hwinit-common.c, this structure is not needed anymore.

Signed-off-by: Lukasz Majewski lukma@denx.de --- arch/arm/include/asm/arch-omap5/cpu.h | 14 -------------- 1 file changed, 14 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 26e7417..de6c4e2 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -47,20 +47,6 @@ struct gptimer { #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))

#define WDT_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) -/* Watchdog */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct watchdog { - u8 res1[0x34]; - u32 wwps; /* 0x34 r */ - u8 res2[0x10]; - u32 wspr; /* 0x48 rw */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555

#define TCLR_ST (0x1 << 0) #define TCLR_AR (0x1 << 1)

Now it is possible to specify in the config file the time after which watchdog will trigger.

The flag itself has been reused from designware watchdog code (./drivers/watchdog/designware_wdt.c).

Signed-off-by: Lukasz Majewski lukma@denx.de --- drivers/watchdog/omap_wdt.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 7b1f429..5a2126b 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -45,7 +45,9 @@ #include <asm/arch/cpu.h>

/* Hardware timeout in seconds */ -#define WDT_HW_TIMEOUT 60 +#ifndef CONFIG_HW_WATCHDOG_TIMEOUT_MS +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 60000 +#endif

static unsigned int wdt_trgr_pattern = 0x1234;

@@ -68,7 +70,7 @@ void hw_watchdog_reset(void) static int omap_wdt_set_timeout(unsigned int timeout) { struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; - u32 pre_margin = GET_WLDR_VAL(timeout); + u32 pre_margin = GET_WLDR_VAL(timeout / 1000);

/* just count up at 32 KHz */ while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) @@ -115,7 +117,7 @@ void hw_watchdog_init(void) while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) ;

- omap_wdt_set_timeout(WDT_HW_TIMEOUT); + omap_wdt_set_timeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS);

/* Sequence to enable the watchdog */ writel(0xBBBB, &wdt->wdtwspr);

The init_func_watchdog_init called in u-boot's board_f.c's init_sequence is responsible for enabling WDT in u-boot and notify user about it.

Several other architectures have adopted it for this purpose. This code does the same with OMAP watchdog.

Signed-off-by: Lukasz Majewski lukma@denx.de --- common/board_f.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/board_f.c b/common/board_f.c index ae6cd85..5dd56a4 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -120,7 +120,7 @@ static int init_func_watchdog_init(void) defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ defined(CONFIG_DESIGNWARE_WATCHDOG) || \ - defined(CONFIG_IMX_WATCHDOG)) + defined(CONFIG_IMX_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG)) hw_watchdog_init(); puts(" Watchdog enabled\n"); # endif