To TO1.0, we can not rely on finish bit to read temperature. But to TO1.1, the issue was fixed by IC, we can rely on finish bit for temperature reading for TO1.1.

Signed-off-by: Peng Fan peng.fan@nxp.com Cc: Stefano Babic sbabic@denx.de Cc: Tim Harvey tharvey@gateworks.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Adrian Alonso aalonso@freescale.com ---

Changes V3: Fix build warning.

Changes V2: Discard reading register each time in the while loop for TO1.0. No need to do this. Discard udelay for TO1.1 when reading register.

drivers/thermal/imx_thermal.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 09a3c52..6578271 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -130,7 +130,7 @@ static int read_cpu_temperature(struct udevice *dev) #elif defined(CONFIG_MX7) static int read_cpu_temperature(struct udevice *dev) { - unsigned int reg, tmp, start; + unsigned int reg, tmp; unsigned int raw_25c, te1; int temperature; unsigned int *priv = dev_get_priv(dev); @@ -169,18 +169,25 @@ static int read_cpu_temperature(struct udevice *dev) writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set);

- start = get_timer(0); - /* Wait max 100ms */ - do { + if (soc_rev() >= CHIP_REV_1_1) { + while ((readl(&ccm_anatop->tempsense1) & + TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0) + ; + reg = readl(&ccm_anatop->tempsense1); + tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) + >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; + } else { /* - * Since we can not rely on finish bit, use 1ms delay to get - * temperature. From RM, 17us is enough to get data, but - * to gurantee to get the data, delay 100ms here. + * Since we can not rely on finish bit, use 10ms + * delay to get temperature. From RM, 17us is + * enough to get data, but to gurantee to get + * the data, delay 10ms here. */ + udelay(10000); reg = readl(&ccm_anatop->tempsense1); tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; - } while (get_timer(0) < (start + 100)); + }

writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);