[U-Boot] [PATCH 00/08 V2] Allow PCI bus address, PA, and VA to differ
This is resubmit of a series I sent back in December - I've rebased to the latest tree and split out a couple of the patches as requested.
This patch series cleans up much of the VA/PA/PCI bus address confusion that is is currently causing a couple of problems on the 8641 36-bit port, and was preventing us from having a PCI mem bus address that differed from the virtual address of the region.
I have fixed a number of problems, such as the ahci driver directly using the pci BAR setting as a virtual address and pci window mapping overlap. There's also some cleanup to the BAT code that were needed to make some of this cleaner.
Cheers, Becky
The diffstat: board/alaska/alaska.c | 36 +++++++------- board/etin/debris/flash.c | 1 + board/etin/kvme080/kvme080.c | 1 + board/freescale/mpc8641hpcn/mpc8641hpcn.c | 22 ++++---- cpu/mpc86xx/cpu_init.c | 27 +++++++++++ drivers/block/ahci.c | 7 +-- drivers/pci/pci.c | 19 ++++++++ include/74xx_7xx.h | 37 --------------- include/asm-ppc/e300.h | 35 -------------- include/asm-ppc/mmu.h | 73 ++++++++++++++++++++++------ include/configs/MPC8641HPCN.h | 28 +++++++++-- include/mpc824x.h | 39 --------------- include/mpc86xx.h | 41 ---------------- include/pci.h | 28 +++++++++-- lib_ppc/bat_rw.c | 28 +++++++++++ lib_ppc/board.c | 2 +- 16 files changed, 211 insertions(+), 213 deletions(-)
Because the inbound pci windows are mapped generously, set up the more specific outbound windows first. This way, when we search the pci regions for something, we will hit on the more specific region. This can actually be a problem on systems with large amounts of RAM.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index b83ed6c..9b6b69e 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -163,9 +163,6 @@ void pci_init_board(void) } debug("\n");
- /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BASE, @@ -180,6 +177,9 @@ void pci_init_board(void) CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
+ /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno; @@ -212,9 +212,6 @@ void pci_init_board(void) struct pci_controller *hose = &pci2_hose; struct pci_region *r = hose->regions;
- /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI2_MEM_BASE, @@ -229,6 +226,9 @@ void pci_init_board(void) CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO);
+ /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
Becky Bruce wrote:
Because the inbound pci windows are mapped generously, set up the more specific outbound windows first. This way, when we search the pci regions for something, we will hit on the more specific region. This can actually be a problem on systems with large amounts of RAM.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
Acked-by: Jon Loeliger jdl@freescale.com
Assuming someone else will now pick up this series.
Thanks, jdl
Assuming someone else will now pick up this series.
Do we just want to elect Andy maintainer for 86xx as well? He's already handling generic 85xx/86xx common stuff. Seeing as there isn't much 86xx work going on at this point doesn't seem like that much more.
- k
Dear Jon,
In message DA87EDF9-3E25-4F76-A43C-14A454F2ECA1@kernel.crashing.org Kumar Gala wrote:
Assuming someone else will now pick up this series.
Do we just want to elect Andy maintainer for 86xx as well? He's already handling generic 85xx/86xx common stuff. Seeing as there isn't much 86xx work going on at this point doesn't seem like that much more.
Jon, what do you think?
Best regards,
Wolfgang Denk
On Feb 3, 2009, at 6:10 PM, Becky Bruce wrote:
Because the inbound pci windows are mapped generously, set up the more specific outbound windows first. This way, when we search the pci regions for something, we will hit on the more specific region. This can actually be a problem on systems with large amounts of RAM.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
board/freescale/mpc8641hpcn/mpc8641hpcn.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-)
this shouldn't be needed w/the recent change I made to add priority to the search that Wolfgang has committed.
- k
On Feb 9, 2009, at 9:50 AM, Kumar Gala wrote:
On Feb 3, 2009, at 6:10 PM, Becky Bruce wrote:
Because the inbound pci windows are mapped generously, set up the more specific outbound windows first. This way, when we search the pci regions for something, we will hit on the more specific region. This can actually be a problem on systems with large amounts of RAM.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
board/freescale/mpc8641hpcn/mpc8641hpcn.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-)
this shouldn't be needed w/the recent change I made to add priority to the search that Wolfgang has committed.
Fine with me :)
-B
Dear Becky Bruce,
In message 1233706256-13878-2-git-send-email-beckyb@kernel.crashing.org you wrote:
Because the inbound pci windows are mapped generously, set up the more specific outbound windows first. This way, when we search the pci regions for something, we will hit on the more specific region. This can actually be a problem on systems with large amounts of RAM.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
board/freescale/mpc8641hpcn/mpc8641hpcn.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- drivers/pci/pci.c | 19 +++++++++++++++++++ include/pci.h | 28 ++++++++++++++++++++++++---- 2 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e2b05d8..cb1217f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -116,6 +116,25 @@ PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
+/* Get a virtual address associated with a BAR region */ +void *pci_map_bar(pci_dev_t pdev, int bar, int flags) +{ + pci_addr_t pci_bus_addr; + u32 bar_response; + + /* read BAR address */ + pci_read_config_dword(pdev, bar, &bar_response); + pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); + + /* + * Pass "0" as the length argument to pci_bus_to_virt. The arg + * isn't actualy used on any platform because u-boot assumes a static + * linear mapping. In the future, this could read the BAR size + * and pass that as the size if needed. + */ + return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE); +} + /* * */ diff --git a/include/pci.h b/include/pci.h index 072273b..058b943 100644 --- a/include/pci.h +++ b/include/pci.h @@ -454,10 +454,29 @@ extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, #define pci_bus_to_phys(dev, addr, flags) \ pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
-#define pci_phys_to_mem(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) -#define pci_mem_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) -#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) -#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) +#define pci_virt_to_bus(dev, addr, flags) \ + pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ + (virt_to_phys(addr)), (flags)) +#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ + map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ + (addr), (flags)), \ + (len), (map_flags)) + +#define pci_phys_to_mem(dev, addr) \ + pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) +#define pci_mem_to_phys(dev, addr) \ + pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) +#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) +#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) + +#define pci_virt_to_mem(dev, addr) \ + pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) +#define pci_mem_to_virt(dev, addr, len, map_flags) \ + pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) +#define pci_virt_to_io(dev, addr) \ + pci_virt_to_bus((dev), (addr), PCI_REGION_IO) +#define pci_io_to_virt(dev, addr, len, map_flags) \ + pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
extern int pci_hose_read_config_byte(struct pci_controller *hose, pci_dev_t dev, int where, u8 *val); @@ -488,6 +507,7 @@ extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, pci_dev_t dev, int where, u16 val);
+extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); extern void pci_register_hose(struct pci_controller* hose); extern struct pci_controller* pci_bus_to_hose(int bus);
Dear Becky Bruce,
In message 1233706256-13878-3-git-send-email-beckyb@kernel.crashing.org you wrote:
It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
drivers/pci/pci.c | 19 +++++++++++++++++++ include/pci.h | 28 ++++++++++++++++++++++++---- 2 files changed, 43 insertions(+), 4 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
The BAT fields are architected; there's no need for these to be in cpu-specific files. Drop the duplication and move these to include/asm-ppc/mmu.h. Also, remove the BL_xxx defines that were only used by the alaska board, and switch to using the BATU_BL_xxx defines used by all the other boards. The BL_ defines previously in use had to be shifted into the proper position for use, which was inefficient.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/alaska/alaska.c | 36 +++++++++++++------------- board/etin/debris/flash.c | 1 + board/etin/kvme080/kvme080.c | 1 + include/74xx_7xx.h | 37 --------------------------- include/asm-ppc/e300.h | 35 ------------------------- include/asm-ppc/mmu.h | 57 ++++++++++++++++++++++++++++++++--------- include/mpc824x.h | 39 ---------------------------- include/mpc86xx.h | 41 ------------------------------ 8 files changed, 64 insertions(+), 183 deletions(-)
diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c index 33b4a6e..89c1abd 100644 --- a/board/alaska/alaska.c +++ b/board/alaska/alaska.c @@ -33,9 +33,9 @@ void setupBat (ulong size)
/* Flash 0 */ #if defined (CONFIG_SYS_AMD_BOOT) - batu = CONFIG_SYS_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_512K | BPP_RW | BPP_RX; #else - batu = CONFIG_SYS_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_16M | BPP_RW | BPP_RX; #endif batl = CONFIG_SYS_FLASH0_BASE | 0x22; write_bat (IBAT0, batu, batl); @@ -43,22 +43,22 @@ void setupBat (ulong size)
/* Flash 1 */ #if defined (CONFIG_SYS_AMD_BOOT) - batu = CONFIG_SYS_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_16M | BPP_RW | BPP_RX; #else - batu = CONFIG_SYS_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_512K | BPP_RW | BPP_RX; #endif batl = CONFIG_SYS_FLASH1_BASE | 0x22; write_bat (IBAT1, batu, batl); write_bat (DBAT1, batu, batl);
/* CPLD */ - batu = CONFIG_SYS_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_CPLD_BASE | BATU_BL_512K | BPP_RW | BPP_RX; batl = CONFIG_SYS_CPLD_BASE | 0x22; write_bat (IBAT2, 0, 0); write_bat (DBAT2, batu, batl);
/* FPGA */ - batu = CONFIG_SYS_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_FPGA_BASE | BATU_BL_512K | BPP_RW | BPP_RX; batl = CONFIG_SYS_FPGA_BASE | 0x22; write_bat (IBAT3, 0, 0); write_bat (DBAT3, batu, batl); @@ -80,17 +80,17 @@ void setupBat (ulong size) mtspr (DBAT5U, batu);
if (size <= 0x800000) /* 8MB */ - blocksize = BL_8M << 2; + blocksize = BATU_BL_8M; else if (size <= 0x1000000) /* 16MB */ - blocksize = BL_16M << 2; + blocksize = BATU_BL_16M; else if (size <= 0x2000000) /* 32MB */ - blocksize = BL_32M << 2; + blocksize = BATU_BL_32M; else if (size <= 0x4000000) /* 64MB */ - blocksize = BL_64M << 2; + blocksize = BATU_BL_64M; else if (size <= 0x8000000) /* 128MB */ - blocksize = BL_128M << 2; + blocksize = BATU_BL_128M; else if (size <= 0x10000000) /* 256MB */ - blocksize = BL_256M << 2; + blocksize = BATU_BL_256M;
/* Memory */ batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX; @@ -108,17 +108,17 @@ void setupBat (ulong size) } else { size -= 0x10000000; if (size <= 0x800000) /* 8MB */ - blocksize = BL_8M << 2; + blocksize = BATU_BL_8M; else if (size <= 0x1000000) /* 16MB */ - blocksize = BL_16M << 2; + blocksize = BATU_BL_16M; else if (size <= 0x2000000) /* 32MB */ - blocksize = BL_32M << 2; + blocksize = BATU_BL_32M; else if (size <= 0x4000000) /* 64MB */ - blocksize = BL_64M << 2; + blocksize = BATU_BL_64M; else if (size <= 0x8000000) /* 128MB */ - blocksize = BL_128M << 2; + blocksize = BATU_BL_128M; else if (size <= 0x10000000) /* 256MB */ - blocksize = BL_256M << 2; + blocksize = BATU_BL_256M;
batu = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | blocksize | BPP_RW | BPP_RX; diff --git a/board/etin/debris/flash.c b/board/etin/debris/flash.c index a3c8138..f9e8619 100644 --- a/board/etin/debris/flash.c +++ b/board/etin/debris/flash.c @@ -27,6 +27,7 @@ #include <asm/processor.h> #include <asm/pci_io.h> #include <mpc824x.h> +#include <asm/mmu.h>
int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t); int (*write_dword)(flash_info_t*, ulong, uint64_t); diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c index 8c6afc9..21616f5 100644 --- a/board/etin/kvme080/kvme080.c +++ b/board/etin/kvme080/kvme080.c @@ -27,6 +27,7 @@ #include <i2c.h> #include <netdev.h> #include <asm/processor.h> +#include <asm/mmu.h>
int checkboard(void) { diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index 4a03cec..69a2174 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -66,43 +66,6 @@ #define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */ #define L2CR_L2IP 0x00000001 /* global invalidate in progress */
-/*---------------------------------------------------------------- - * BAT settings. Look in config_<BOARD>.h for the actual setup - */ - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 -#define BATU_INVALID 0x00000000 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 -#define BATL_NO_ACCESS 0x00000000 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -#define BATL_PP_NO_ACCESS BATL_PP_00 -#define BATL_PP_RO BATL_PP_01 -#define BATL_PP_RW BATL_PP_10 - #ifndef __ASSEMBLY__ /* cpu ids we detect */ typedef enum __cpu_t { diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index 05db0de..bfef4df 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -88,39 +88,4 @@ #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */ #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
- -/* BAT (block address translation */ -#define BATU_BEPI_MSK 0xfffe0000 -#define BATU_BL_MSK 0x00001ffc - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 - -#define BATL_BRPN_MSK 0xfffe0000 -#define BATL_WIMG_MSK 0x00000078 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - #endif /* __E300_H__ */ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 6d942d0..ce04e62 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -153,19 +153,50 @@ extern void print_bats(void);
#endif /* __ASSEMBLY__ */
-/* Block size masks */ -#define BL_128K 0x000 -#define BL_256K 0x001 -#define BL_512K 0x003 -#define BL_1M 0x007 -#define BL_2M 0x00F -#define BL_4M 0x01F -#define BL_8M 0x03F -#define BL_16M 0x07F -#define BL_32M 0x0FF -#define BL_64M 0x1FF -#define BL_128M 0x3FF -#define BL_256M 0x7FF +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 +#define BATU_INVALID 0x00000000 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_NO_ACCESS 0x00000000 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#define BATL_PP_NO_ACCESS BATL_PP_00 +#define BATL_PP_RO BATL_PP_01 +#define BATL_PP_RW BATL_PP_10 + +/* BAT Block size values */ +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc + +/* Block lengths for processors that support extended block length */ +#ifdef HID0_XBSEN +#define BATU_BL_512M 0x00003ffc +#define BATU_BL_1G 0x00007ffc +#define BATU_BL_2G 0x0000fffc +#define BATU_BL_4G 0x0001fffc +#define BATU_BL_MAX BATU_BL_4G +#else +#define BATU_BL_MAX BATU_BL_256M +#endif
/* BAT Access Protection */ #define BPP_XX 0x00 /* No access */ diff --git a/include/mpc824x.h b/include/mpc824x.h index 5aa9370..fca9371 100644 --- a/include/mpc824x.h +++ b/include/mpc824x.h @@ -451,45 +451,6 @@ #define MICR_EADDR_MASK 0x30000000 #define MICR_EADDR_SHIFT 28
-#define BATU_BEPI_MSK 0xfffe0000 -#define BATU_BL_MSK 0x00001ffc - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 - -#define BATL_BRPN_MSK 0xfffe0000 -#define BATL_WIMG_MSK 0x00000078 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -/* - * I'd attempt to do defines for the PP bits, but it's use is a bit - * too complex, see the PowerPC Operating Environment Architecture - * section in the PowerPc arch book, chapter 4. - */ - /*eumb and epic config*/
#define EPIC_FPR 0x00041000 diff --git a/include/mpc86xx.h b/include/mpc86xx.h index a6fdea3..c6f30f9 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -34,47 +34,6 @@ #define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ #define L2CR_L2IP 0x00000001 /* global invalidate in progress */
-/* - * BAT settings. Look in config_<BOARD>.h for the actual setup - */ - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc -#define BATU_BL_512M 0x00003ffc -#define BATU_BL_1G 0x00007ffc -#define BATU_BL_2G 0x0000fffc -#define BATU_BL_4G 0x0001fffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 -#define BATU_INVALID 0x00000000 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 -#define BATL_NO_ACCESS 0x00000000 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -#define BATL_PP_NO_ACCESS BATL_PP_00 -#define BATL_PP_RO BATL_PP_01 -#define BATL_PP_RW BATL_PP_10 - #define HID0_XBSEN 0x00000100 #define HID0_HIGH_BAT_EN 0x00800000 #define HID0_XAEN 0x00020000
Dear Becky Bruce,
In message 1233706256-13878-4-git-send-email-beckyb@kernel.crashing.org you wrote:
The BAT fields are architected; there's no need for these to be in cpu-specific files. Drop the duplication and move these to include/asm-ppc/mmu.h. Also, remove the BL_xxx defines that were only used by the alaska board, and switch to using the BATU_BL_xxx defines used by all the other boards. The BL_ defines previously in use had to be shifted into the proper position for use, which was inefficient.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
board/alaska/alaska.c | 36 +++++++++++++------------- board/etin/debris/flash.c | 1 + board/etin/kvme080/kvme080.c | 1 + include/74xx_7xx.h | 37 --------------------------- include/asm-ppc/e300.h | 35 ------------------------- include/asm-ppc/mmu.h | 57 ++++++++++++++++++++++++++++++++--------- include/mpc824x.h | 39 ---------------------------- include/mpc86xx.h | 41 ------------------------------ 8 files changed, 64 insertions(+), 183 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
If CONFIG_ADDR_MAP is enabled, update the address map whenever we write a bat.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- cpu/mpc86xx/cpu_init.c | 27 +++++++++++++++++++++++++++ include/asm-ppc/mmu.h | 16 +++++++++++++--- lib_ppc/bat_rw.c | 28 ++++++++++++++++++++++++++++ lib_ppc/board.c | 2 +- 4 files changed, 69 insertions(+), 4 deletions(-)
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index a7e6036..4f29122 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -154,3 +154,30 @@ void setup_bats(void)
return; } + +#ifdef CONFIG_ADDR_MAP +/* Initialize address mapping array */ +void init_addr_map(void) +{ + int i; + ppc_bat_t bat = DBAT0; + phys_size_t size; + unsigned long upper, lower; + + for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) { + if (read_bat(bat, &upper, &lower) != -1) { + if (!BATU_VALID(upper)) + size = 0; + else + size = BATU_SIZE(upper); + addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), + size, i); + } +#ifdef CONFIG_HIGH_BATS + /* High bats are not contiguous with low BAT numbers */ + if (bat == DBAT3) + bat = DBAT4 - 1; +#endif + } +} +#endif diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index ce04e62..fa92b90 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -138,6 +138,10 @@ typedef struct _MMU_context { extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ extern void _tlbia(void); /* invalidate all TLB entries */
+#ifdef CONFIG_ADDR_MAP +extern void init_addr_map(void); +#endif + typedef enum { IBAT0 = 0, IBAT1, IBAT2, IBAT3, DBAT0, DBAT1, DBAT2, DBAT3, @@ -203,6 +207,14 @@ extern void print_bats(void); #define BPP_RX 0x01 /* Read only */ #define BPP_RW 0x02 /* Read/write */
+/* Macros to get values from BATs, once data is in the BAT register format */ +#define BATU_VALID(x) (x & 0x3) +#define BATU_VADDR(x) (x & 0xfffe0000) +#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \ + | ((x & 0x0e00ULL) << 24) \ + | ((x & 0x04ULL) << 30))) +#define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17)) + /* Used to set up SDR1 register */ #define HASH_TABLE_SIZE_64K 0x00010000 #define HASH_TABLE_SIZE_128K 0x00020000 @@ -462,9 +474,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn, extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); -#ifdef CONFIG_ADDR_MAP -extern void init_addr_map(void); -#endif + extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c index a40b377..c48c240 100644 --- a/lib_ppc/bat_rw.c +++ b/lib_ppc/bat_rw.c @@ -27,14 +27,23 @@ #include <asm/mmu.h> #include <asm/io.h>
+#ifdef CONFIG_ADDR_MAP +#include <addr_map.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) { + int batn = -1; + sync();
switch (bat) { case DBAT0: mtspr (DBAT0L, lower); mtspr (DBAT0U, upper); + batn = 0; break; case IBAT0: mtspr (IBAT0L, lower); @@ -43,6 +52,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) case DBAT1: mtspr (DBAT1L, lower); mtspr (DBAT1U, upper); + batn = 1; break; case IBAT1: mtspr (IBAT1L, lower); @@ -51,6 +61,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) case DBAT2: mtspr (DBAT2L, lower); mtspr (DBAT2U, upper); + batn = 2; break; case IBAT2: mtspr (IBAT2L, lower); @@ -59,6 +70,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) case DBAT3: mtspr (DBAT3L, lower); mtspr (DBAT3U, upper); + batn = 3; break; case IBAT3: mtspr (IBAT3L, lower); @@ -68,6 +80,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) case DBAT4: mtspr (DBAT4L, lower); mtspr (DBAT4U, upper); + batn = 4; break; case IBAT4: mtspr (IBAT4L, lower); @@ -76,6 +89,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) case DBAT5: mtspr (DBAT5L, lower); mtspr (DBAT5U, upper); + batn = 5; break; case IBAT5: mtspr (IBAT5L, lower); @@ -84,6 +98,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) case DBAT6: mtspr (DBAT6L, lower); mtspr (DBAT6U, upper); + batn = 6; break; case IBAT6: mtspr (IBAT6L, lower); @@ -92,6 +107,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) case DBAT7: mtspr (DBAT7L, lower); mtspr (DBAT7U, upper); + batn = 7; break; case IBAT7: mtspr (IBAT7L, lower); @@ -102,6 +118,18 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) return (-1); }
+#ifdef CONFIG_ADDR_MAP + if ((gd->flags & GD_FLG_RELOC) && (batn >= 0)) { + phys_size_t size; + if (!BATU_VALID(upper)) + size = 0; + else + size = BATU_SIZE(upper); + addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), + size, batn); + } +#endif + sync(); isync();
diff --git a/lib_ppc/board.c b/lib_ppc/board.c index df1cf13..2262bb4 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -685,7 +685,7 @@ void board_init_r (gd_t *id, ulong dest_addr) */ trap_init (dest_addr);
-#if defined(CONFIG_ADDR_MAP) && defined(CONFIG_E500) +#ifdef CONFIG_ADDR_MAP init_addr_map(); #endif
Becky Bruce wrote:
If CONFIG_ADDR_MAP is enabled, update the address map whenever we write a bat.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
Acked-by: Jon Loeliger jdl@freescale.com
Assuming someone else will now pick up this series.
Thanks, jdl
Dear Becky Bruce,
In message 1233706256-13878-5-git-send-email-beckyb@kernel.crashing.org you wrote:
If CONFIG_ADDR_MAP is enabled, update the address map whenever we write a bat.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
cpu/mpc86xx/cpu_init.c | 27 +++++++++++++++++++++++++++ include/asm-ppc/mmu.h | 16 +++++++++++++--- lib_ppc/bat_rw.c | 28 ++++++++++++++++++++++++++++ lib_ppc/board.c | 2 +- 4 files changed, 69 insertions(+), 4 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
Clean up PCI mapping concepts in the 8641 config - rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 10 +++++----- include/configs/MPC8641HPCN.h | 17 +++++++++++------ 2 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 9b6b69e..28c1683 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -165,14 +165,14 @@ void pci_init_board(void)
/* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
/* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); @@ -195,7 +195,7 @@ void pci_init_board(void) * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ - in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_BASE + in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
} else { @@ -214,14 +214,14 @@ void pci_init_board(void)
/* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_BUS, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM);
/* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_BUS, CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index ceb8e54..ce94b7a 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -331,14 +331,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 + +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL #else -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_VIRT #endif #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \ | CONFIG_SYS_PHYS_ADDR_HIGH) @@ -348,12 +351,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) #define _IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \ +#define CONFIG_SYS_PCI2_MEM_BUS (CONFIG_SYS_PCI1_MEM_BUS \ + + CONFIG_SYS_PCI1_MEM_SIZE) +#define CONFIG_SYS_PCI2_MEM_VIRT (CONFIG_SYS_PCI1_MEM_VIRT \ + CONFIG_SYS_PCI1_MEM_SIZE) #define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \ + CONFIG_SYS_PCI1_MEM_SIZE) #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \ + CONFIG_SYS_PCI1_IO_SIZE) #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ @@ -501,7 +506,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \ +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \ | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT)
Becky Bruce wrote:
Clean up PCI mapping concepts in the 8641 config - rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
Acked-by: Jon Loeliger jdl@freescale.com
Assuming someone else will now pick up this series.
Thanks, jdl
Dear Becky Bruce,
In message 1233706256-13878-6-git-send-email-beckyb@kernel.crashing.org you wrote:
Clean up PCI mapping concepts in the 8641 config - rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
board/freescale/mpc8641hpcn/mpc8641hpcn.c | 10 +++++----- include/configs/MPC8641HPCN.h | 17 +++++++++++------ 2 files changed, 16 insertions(+), 11 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- include/configs/MPC8641HPCN.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index ce94b7a..84708c4 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -39,6 +39,7 @@ #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ +#define CONFIG_ADDR_MAP 1 /* Use addr map */
#ifdef RUN_DIAG #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE @@ -70,6 +71,7 @@ #define CONFIG_ENV_OVERWRITE
#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ +#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
#define CONFIG_ALTIVEC 1
Becky Bruce wrote:
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
Acked-by: Jon Loeliger jdl@freescale.com
Assuming someone else will now pick up this series.
Thanks, jdl
Dear Becky Bruce,
In message 1233706256-13878-7-git-send-email-beckyb@kernel.crashing.org you wrote:
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
include/configs/MPC8641HPCN.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
The code assumes that the pci bus address and the virtual address used to access a region are the same, but they might not be. Fix this assumption.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- drivers/block/ahci.c | 7 ++----- 1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 2445e8c..e1b66fd 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -251,7 +251,6 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent)
static int ahci_init_one(pci_dev_t pdev) { - u32 iobase; u16 vendor; int rc;
@@ -261,9 +260,6 @@ static int ahci_init_one(pci_dev_t pdev) memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); probe_ent->dev = pdev;
- pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); - iobase &= ~0xf; - probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO @@ -272,7 +268,8 @@ static int ahci_init_one(pci_dev_t pdev) probe_ent->pio_mask = 0x1f; probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
- probe_ent->mmio_base = iobase; + probe_ent->mmio_base = (u32)pci_map_bar(pdev, AHCI_PCI_BAR, + PCI_REGION_MEM);
/* Take from kernel: * JMicron-specific fixup:
Dear Becky Bruce,
In message 1233706256-13878-8-git-send-email-beckyb@kernel.crashing.org you wrote:
The code assumes that the pci bus address and the virtual address used to access a region are the same, but they might not be. Fix this assumption.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
drivers/block/ahci.c | 7 ++----- 1 files changed, 2 insertions(+), 5 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
Now that the rest of u-boot can support it, change the PCI bus address of the PCI MEM regions from 0x80000000 to 0xc0000000, and use the same bus address for both PCI1 and PCI2. This will maximize the amount of PCI address space left over to map RAM on systems with large amounts of memory.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- include/configs/MPC8641HPCN.h | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 84708c4..f1b7eb5 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -336,7 +336,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT +#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL #else #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT @@ -353,8 +353,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) #define _IO_BASE 0x00000000
+#ifdef CONFIG_PHYS_64BIT +/* + * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT. + * This will increase the amount of PCI address space available for + * for mapping RAM. + */ +#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI1_MEM_BUS +#else #define CONFIG_SYS_PCI2_MEM_BUS (CONFIG_SYS_PCI1_MEM_BUS \ + CONFIG_SYS_PCI1_MEM_SIZE) +#endif #define CONFIG_SYS_PCI2_MEM_VIRT (CONFIG_SYS_PCI1_MEM_VIRT \ + CONFIG_SYS_PCI1_MEM_SIZE) #define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \
Becky Bruce wrote:
Now that the rest of u-boot can support it, change the PCI bus address of the PCI MEM regions from 0x80000000 to 0xc0000000, and use the same bus address for both PCI1 and PCI2. This will maximize the amount of PCI address space left over to map RAM on systems with large amounts of memory.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
Acked-by: Jon Loeliger jdl@freescale.com
Assuming someone else will now pick up this series.
Thanks, jdl
Dear Becky Bruce,
In message 1233706256-13878-9-git-send-email-beckyb@kernel.crashing.org you wrote:
Now that the rest of u-boot can support it, change the PCI bus address of the PCI MEM regions from 0x80000000 to 0xc0000000, and use the same bus address for both PCI1 and PCI2. This will maximize the amount of PCI address space left over to map RAM on systems with large amounts of memory.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
include/configs/MPC8641HPCN.h | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
participants (4)
-
Becky Bruce -
Jon Loeliger -
Kumar Gala -
Wolfgang Denk