From: Rogan Dawes <Rogan Dawes rogan@dawes.za.net>

--- arch/arm/cpu/arm926ejs/orion5x/dram.c | 2 +- arch/arm/include/asm/arch-orion5x/orion5x.h | 1 + 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c index c719798..90b0a9c 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/dram.c +++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c @@ -38,7 +38,7 @@ u32 orion5x_sdram_bar(enum memory_bank bank) { struct orion5x_ddr_addr_decode_registers *winregs = (struct orion5x_ddr_addr_decode_registers *) - ORION5X_CPU_WIN_BASE; + ORION5X_DRAM_BASE;

u32 result = 0; u32 enable = 0x01 & winregs[bank].size; diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h index e3d3f76..1dd9f65 100644 --- a/arch/arm/include/asm/arch-orion5x/orion5x.h +++ b/arch/arm/include/asm/arch-orion5x/orion5x.h @@ -42,6 +42,7 @@ #define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x)

/* Documented registers */ +#define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500)) #define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000)) #define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000)) #define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))

From: Albert Aribaud albert.aribaud@free.fr

Fix orion5x_winctrl_calcsize() off-by-1 bug which caused mapping windows to be cut by half. This afected all windows including NOR flash (causing half the flash to be unaccessible) but DRAM was and still is fine as its size is determined otherwise.

Signed-off-by: Albert Aribaud albert.aribaud@free.fr --- arch/arm/cpu/arm926ejs/orion5x/cpu.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 3740e33..260f88b 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -61,7 +61,7 @@ unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) unsigned int j = 0; u32 val = sizeval >> 1;

- for (i = 0; val > 0x10000; i++) { + for (i = 0; val >= 0x10000; i++) { j |= (1 << i); val = val >> 1; }

From: Albert Aribaud albert.aribaud@free.fr

This driver is for the Marvell TWSI/I2C module found in the orion and kirkwood families among others.

Signed-off-by: Albert Aribaud albert.aribaud@free.fr --- drivers/i2c/Makefile | 1 + drivers/i2c/mvtwsi.c | 419 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 420 insertions(+), 0 deletions(-) create mode 100644 drivers/i2c/mvtwsi.c

diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index d2c2515..73c415d 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -30,6 +30,7 @@ COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o COBJS-$(CONFIG_I2C_KIRKWOOD) += kirkwood_i2c.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o +COBJS-$(CONFIG_I2C_DRIVER_MVTWSI) += mvtwsi.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c new file mode 100644 index 0000000..b591328 --- /dev/null +++ b/drivers/i2c/mvtwsi.c @@ -0,0 +1,419 @@ +/* + * Driver for the TWSI (i2c) controller on the Marvell orion5x + * + * Author: Albert Aribaud albert.aribaud@free.fr + * 2005 (c) MontaVista, Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/errno.h> +#include <asm/io.h> + +/* + * include a file that will provide CONFIG_I2C_MVTWSI_BASE + * and possibly other settings + */ + +#if defined(CONFIG_ORION5X) +#include <asm/arch/orion5x.h> +#else +#error Driver mvtwsi not supported by SoC or board +#endif + +/* + * TWSI register structure + */ + +struct mvtwsi_registers { + u32 slave_address; + u32 data; + u32 control; + union { + u32 status; /* when reading */ + u32 baudrate; /* when writing */ + }; + u32 extended_slave_address; + u32 reserved[2]; + u32 soft_reset; +}; + +/* + * Control register fields + */ + +#define MVTWSI_CONTROL_ACK 0x00000004 +#define MVTWSI_CONTROL_IFLG 0x00000008 +#define MVTWSI_CONTROL_STOP 0x00000010 +#define MVTWSI_CONTROL_START 0x00000020 +#define MVTWSI_CONTROL_TWSIEN 0x00000040 +#define MVTWSI_CONTROL_INTEN 0x00000080 + +/* + * Status register values -- only those expected in normal master + * operation on non-10-bit-address devices; whatever status we don't + * expect in nominal conditions (bus errors, arbitration losses, + * missing ACKs...) we just pass back to the caller as an error + * code. + */ + +#define MVTWSI_STATUS_START 0x08 +#define MVTWSI_STATUS_REPEATED_START 0x10 +#define MVTWSI_STATUS_ADDR_W_ACK 0x18 +#define MVTWSI_STATUS_DATA_W_ACK 0x28 +#define MVTWSI_STATUS_ADDR_R_ACK 0x40 +#define MVTWSI_STATUS_ADDR_R_NAK 0x48 +#define MVTWSI_STATUS_DATA_R_ACK 0x50 +#define MVTWSI_STATUS_DATA_R_NAK 0x58 /* our NAK, not the slave's */ +#define MVTWSI_STATUS_IDLE 0xF8 + +/* + * The single instance of the controller we'll be dealing with + */ + +static struct mvtwsi_registers *twsi = + (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE; + +/* + * Returned statuses are 0 for success and nonzero otherwise. + * Currently, cmd_i2c and cmd_eeprom do not interpret an error status. + * Thus to ease debugging, the return status contains some debug info: + * - bits 31..24 are an error class: 0x01 is timeout, 0x02 is 'status mismatch'. + * - bits 23..16 are the last value of the control register. + * - bits 15..8 are the last value of the status register. + * - bits 7..0 are the expected value of the status register. + */ + +#define MVTWSI_ERROR_WRONG_STATUS 0x01 +#define MVTWSI_ERROR_TIMEOUT 0x02 + +#define MVTWSI_ERROR(ec,lc,ls,es) ( ( (ec << 24) & 0xFF000000) | \ + ( (lc << 16) & 0x00FF0000) | ( (ls<<8) & 0x0000FF00) | (es & 0xFF) ) + +/* + * Wait for IFLG to raise, or return 'timeout'; then if status is as expected, + * return 0 (ok) or return 'wrong status'. + */ + +static int twsi_wait(int expected_status) +{ + int control,status; + int timeout = 1000; + do { + control = readl(&twsi->control); + if (control & MVTWSI_CONTROL_IFLG) { + status = readl(&twsi->status); + if (status==expected_status) + return 0; + else + return MVTWSI_ERROR(MVTWSI_ERROR_WRONG_STATUS,control, status, + expected_status); + } + udelay(10); + } while (timeout--); + status = readl(&twsi->status); + return MVTWSI_ERROR(MVTWSI_ERROR_TIMEOUT,control,status,expected_status); +} + +/* + * These flags are ORed to any write to the control register + * They allow global setting of TWSIEN and ACK. + * By default none are set. + * twsi_start() sets TWSIEN (in case the controller was disabled) + * twsi_recv() sets ACK or resets it depending on expected status. + */ + +static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN; + +/* + * Assert the START condition, either in a single I2C transaction + * or inside back-to-back ones (repeated starts). + */ + +static int twsi_start(int expected_status) +{ + /* globally set TWSIEN in case it was not */ + twsi_control_flags |= MVTWSI_CONTROL_TWSIEN; + /* assert START */ + writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control); + /* wait for controller to process START */ + return twsi_wait(expected_status); +} + +/* + * Send a byte (i2c address or data). + */ + +static int twsi_send(u8 byte, int expected_status) +{ + /* put byte in data register for sending */ + writel(byte, &twsi->data); + /* clear any pending interrupt -- that'll cause sending */ + writel(twsi_control_flags, &twsi->control); + /* wait for controller to receive byte and check ACK */ + return twsi_wait(expected_status); +} + +/* + * Receive a byte. + * Global mvtwsi_control_flags variable says if we should ack or nak. + */ + +static int twsi_recv(u8 *byte) +{ + int expected_status, status; + /* compute expected status based on ACK bit in global control flags */ + if (twsi_control_flags & MVTWSI_CONTROL_ACK) + expected_status = MVTWSI_STATUS_DATA_R_ACK; + else + expected_status = MVTWSI_STATUS_DATA_R_NAK; + /* acknowledge *previous state* and launch receive */ + writel(twsi_control_flags, &twsi->control); + /* wait for controller to receive byte and assert ACK or NAK */ + status = twsi_wait(expected_status); + /* if we did receive expected byte then store it */ + if (status==0) + *byte = readl(&twsi->data); + /* return status */ + return status; +} + +/* + * Assert the STOP condition. + * This is also used to force the bus back in idle (SDA=SCL=1). + */ + +static int twsi_stop(void) +{ + int control,status; + int timeout = 1000; + /* assert STOP */ + control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; + writel(control, &twsi->control); + /* wait for idle condition. There won't be an IFLG so we cannot use twsi_wait(). */ + do { + status = readl(&twsi->status); + if (status==MVTWSI_STATUS_IDLE) + return 0; + udelay(10); + } while (timeout--); + control = readl(&twsi->control); + return MVTWSI_ERROR(MVTWSI_ERROR_TIMEOUT,control,status,MVTWSI_STATUS_IDLE); +} + +/* + * Ugly formula to convert m and n values to a frequency comes from + * TWSI specifications + */ + +#define TWSI_FREQUENCY(m,n) \ + ( (u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n))) ) + +/* + * These are required to be reprogrammed before enabling the controller + * because a reset loses them. + * Default values come from the spec, but a twsi_reset will change them. + */ + +static u8 twsi_baud_rate = 0x44; +static u8 twsi_actual_speed = TWSI_FREQUENCY(4,4); +static u8 twsi_slave_address = 0; + +/* + * Reset controller. + * Called at end of i2c_init unsuccessful i2c transactions. + * Controller reset also resets the baud rate and slave address, so + * re-establish them. + */ + +static void twsi_reset(void) +{ + /* ensure controller will be enabled by any twsi*() function */ + twsi_control_flags = MVTWSI_CONTROL_TWSIEN; + /* reset controller */ + writel(0, &twsi->soft_reset); + /* wait 2 ms -- this is what the Marvell LSP does */ + udelay(20000); + /* set baud rate */ + writel(twsi_baud_rate, &twsi->baudrate); + /* set slave address even though we don't use it */ + writel(twsi_slave_address, &twsi->slave_address); + writel(0, &twsi->extended_slave_address); + /* assert STOP but don't care for the result */ + (void) twsi_stop(); +} + +/* + * I2C init called by cmd_i2c when doing 'i2c reset'. + * Sets baud to the highest possible value not exceeding requested one. + */ + +void i2c_init(int requested_speed, int slaveadd) +{ + int tmp_speed, highest_speed, n, m; + int baud = 0x44; /* value at controller reset */ + /* use actual speed to collect progressively higher values */ + highest_speed = 0; + /* compute m,n setting for highest speed not above requested speed */ + for (n = 0; n < 8; n++) { + for (m = 0; m < 16; m++) { + tmp_speed = TWSI_FREQUENCY(m,n); + if (tmp_speed <= requested_speed) + if (tmp_speed > highest_speed) { + highest_speed = tmp_speed; + baud = (m << 3) | n; + } + } + } + /* save baud rate and slave for later calls to twsi_reset */ + twsi_baud_rate = baud; + twsi_actual_speed = highest_speed; + twsi_slave_address = slaveadd; + /* reset controller */ + twsi_reset(); +} + +/* + * Begin I2C transaction with expected start status, at given address. + * Common to i2c_probe, i2c_read and i2c_write. + * Expected address status will derive from direction bit (bit 0) in addr. + */ + +static int i2c_begin(int expected_start_status, u8 addr) +{ + int status, expected_addr_status; + /* compute expected address status from direction bit in addr */ + if (addr & 1) /* reading */ + expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; + else /* writing */ + expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; + /* assert START */ + status = twsi_start(expected_start_status); + /* send out the address if the start went well */ + if (status == 0) + status = twsi_send(addr, expected_addr_status); + /* return ok or status of first failure to caller */ + return status; +} + +/* + * End I2C transaction, of which the current status is given. + * Common to i2c_probe, i2c_read and i2c_write. + */ + +static int i2c_end(int status) +{ + /* if transaction went well so far, try to assert a STOP */ + /*if (status == 0)*/ + twsi_stop(); + /* if anything went wrong (including the STOP we tried), do a reset */ + /*else + twsi_reset();*/ + /* return ok or status of first failure to caller */ + return status; +} + +/* + * I2C probe called by cmd_i2c when doing 'i2c probe'. + * Begin read, nak data byte, end. + */ + +int i2c_probe(uchar chip) +{ + u8 dummy_byte; + int status; + /* begin i2c read */ + status = i2c_begin(MVTWSI_STATUS_START, (chip << 1) | 1 ); + /* dummy read was accepted: receive byte but NAK it. */ + if (status==0) + status = twsi_recv( &dummy_byte); + /* We expected either 0 (ok) or MVTWSI_STATUS_ADDR_R_NAK */ + return i2c_end( (status==MVTWSI_STATUS_ADDR_R_NAK) ? 0: status); +} + +/* + * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c + * Begin write, send address byte(s), begin read, receive data bytes, end. + */ + +int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) +{ + int status; + /* begin i2c write to send the address bytes */ + status = i2c_begin(MVTWSI_STATUS_START, (dev << 1) ); + /* send addr bytes */ + while ( (status==0) && alen--) + status = twsi_send(addr >> (8*alen), MVTWSI_STATUS_DATA_W_ACK); + /* NOTE: should we send a stop before a start? That's eeprom-level stuff */ + /* begin i2c read to receive eeprom data bytes */ + if (status == 0) + status = i2c_begin(MVTWSI_STATUS_REPEATED_START, (dev << 1) | 1); + /* prepare ACK if at least one byte must be received */ + if (length > 0) + twsi_control_flags |= MVTWSI_CONTROL_ACK; + /* now receive actual bytes */ + while ( (status==0) && length-- ) { + /* reset NAK if we if no more to read now */ + if (length == 0) + twsi_control_flags &= ~MVTWSI_CONTROL_ACK; + /* read current byte */ + status = twsi_recv(data++); + } + /* end i2c transaction */ + return i2c_end(status); +} + +/* + * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c + * Begin write, send address byte(s), send data bytes, end. + */ + +int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) +{ + int status; + /* begin i2c write to send the eeprom adress bytes then data bytes */ + status = i2c_begin(MVTWSI_STATUS_START, (dev << 1) ); + /* send addr bytes */ + while ( (status==0) && alen--) + status = twsi_send(addr >> (8*alen), MVTWSI_STATUS_DATA_W_ACK); + /* send data bytes */ + while ( (status==0) && (length-->0) ) + status = twsi_send(*(data++), MVTWSI_STATUS_DATA_W_ACK); + /* end i2c transaction */ + return i2c_end(status); +} + +/* + * Bus set/get routines: we only support bus 0. + */ + +int i2c_set_bus_num(unsigned int bus) +{ + if (bus > 0) { + return -1; + } + return 0; +} + +unsigned int i2c_get_bus_num(void) +{ + return 0; +}

From: Albert Aribaud albert.aribaud@free.fr

Signed-off-by: Albert Aribaud albert.aribaud@free.fr --- include/configs/edminiv2.h | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 57dd165..36ed392 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -182,6 +182,15 @@ #endif /* CMD_IDE */

/* + * I2C related stuff + */ +#define CONFIG_I2C_DRIVER_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C + +/* * Environment variables configurations */ #define CONFIG_ENV_IS_IN_FLASH 1

From: Rogan Dawes rogan@dawes.za.net

--- arch/arm/include/asm/setup.h | 18 ++++++++++++++++++ arch/arm/lib/bootm.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index 89df4dc..bd6229a 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -198,6 +198,19 @@ struct tag_acorn { u8 adfsdrives; };

+/* Marvell specific information + * requred for compatability with vendor kernels + */ +#define ATAG_MV_UBOOT 0x41000403 + +struct tag_mv_uboot { + u32 uboot_version; + u32 tclk; + u32 sysclk; + u32 isUsbHost; + u32 overEthAddr; +}; + /* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ #define ATAG_MEMCLK 0x41000402

@@ -227,6 +240,11 @@ struct tag { * DC21285 specific */ struct tag_memclk memclk; + + /* + * Marvell specific + */ + struct tag_mv_uboot mv_uboot; } u; };

diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 3101321..f3acd6c 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -45,6 +45,11 @@ static void setup_commandline_tag (bd_t *bd, char *commandline); static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end); # endif + +#ifdef CONFIG_MARVELL_TAG +static void setup_marvell_tag(void); +#endif + static void setup_end_tag (bd_t *bd);

static struct tag *params; @@ -80,6 +85,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima #if defined (CONFIG_SETUP_MEMORY_TAGS) || \ defined (CONFIG_CMDLINE_TAG) || \ defined (CONFIG_INITRD_TAG) || \ + defined (CONFIG_MARVELL_TAG) || \ defined (CONFIG_SERIAL_TAG) || \ defined (CONFIG_REVISION_TAG) setup_start_tag (bd); @@ -99,6 +105,9 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima if (images->rd_start && images->rd_end) setup_initrd_tag (bd, images->rd_start, images->rd_end); #endif +#ifdef CONFIG_MARVELL_TAG + setup_marvell_tag(); +#endif setup_end_tag (bd); #endif

@@ -232,6 +241,27 @@ void setup_revision_tag(struct tag **in_params) } #endif /* CONFIG_REVISION_TAG */

+#ifdef CONFIG_MARVELL_TAG +#define ATAG_MARVELL 0x41000403 +#define VER_NUM 0x01070300 + +void setup_marvell_tag(void) { + debug("Setting up Marvell tag\n"); + params->hdr.tag = ATAG_MARVELL; + params->hdr.size = tag_size (tag_mv_uboot); + + params->u.mv_uboot.uboot_version = VER_NUM; + params->u.mv_uboot.uboot_version |= 0xB; // RD_88F5182_2XSATA + params->u.mv_uboot.tclk = 166000000; + params->u.mv_uboot.sysclk = 166000000; + params->u.mv_uboot.isUsbHost = 1; + params->u.mv_uboot.isUsbHost |= 2; + + params->u.mv_uboot.overEthAddr = 0; + + params = tag_next (params); +} +#endif

static void setup_end_tag (bd_t *bd) {

From: rogan@dawes.za.net rogan@dawes.za.net

--- common/image.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/image.c b/common/image.c index fcb938b..eea93a9 100644 --- a/common/image.c +++ b/common/image.c @@ -949,7 +949,7 @@ int boot_get_ramdisk (int argc, char * const argv[], bootm_headers_t *images, return 1; }

-#if defined(CONFIG_B2) || defined(CONFIG_EVB4510) || defined(CONFIG_ARMADILLO) +#if defined(CONFIG_B2) || defined(CONFIG_EVB4510) || defined(CONFIG_ARMADILLO) || defined(CONFIG_MACH_DNS323) /* * We need to copy the ramdisk to SRAM to let Linux boot */ @@ -957,7 +957,7 @@ int boot_get_ramdisk (int argc, char * const argv[], bootm_headers_t *images, memmove ((void *)rd_load, (uchar *)rd_data, rd_len); rd_data = rd_load; } -#endif /* CONFIG_B2 || CONFIG_EVB4510 || CONFIG_ARMADILLO */ +#endif /* CONFIG_B2 || CONFIG_EVB4510 || CONFIG_ARMADILLO || CONFIG_MACH_DNS323 */

} else if (images->legacy_hdr_valid && image_check_type (&images->legacy_hdr_os_copy, IH_TYPE_MULTI)) {

From: Rogan Dawes rogan@dawes.za.net

--- arch/arm/cpu/arm926ejs/orion5x/dram.c | 2 +- arch/arm/include/asm/arch-orion5x/orion5x.h | 1 + 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c index b749282..2ae8f48 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/dram.c +++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c @@ -38,7 +38,7 @@ u32 orion5x_sdram_bar(enum memory_bank bank) { struct orion5x_ddr_addr_decode_registers *winregs = (struct orion5x_ddr_addr_decode_registers *) - ORION5X_CPU_WIN_BASE; + ORION5X_DRAM_BASE;

u32 result = 0; u32 enable = 0x01 & winregs[bank].size; diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h index e3d3f76..1dd9f65 100644 --- a/arch/arm/include/asm/arch-orion5x/orion5x.h +++ b/arch/arm/include/asm/arch-orion5x/orion5x.h @@ -42,6 +42,7 @@ #define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x)

/* Documented registers */ +#define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500)) #define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000)) #define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000)) #define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))

From: Rogan Dawes rogan@dawes.za.net

Some SATA controllers can operate in an IDE compatible mode (e.g. mvsata) but will only ever have a single device per bus.

This allows the upcoming DNS323 port to properly identify and use a drive on both SATA interfaces. --- include/ide.h | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/include/ide.h b/include/ide.h index 6a1b7ae..c812b28 100644 --- a/include/ide.h +++ b/include/ide.h @@ -24,7 +24,8 @@ #ifndef _IDE_H #define _IDE_H

-#define IDE_BUS(dev) (dev >> 1) +#define IDE_BUS(dev) (dev >> ((CONFIG_SYS_IDE_MAXDEVICE / \ + CONFIG_SYS_IDE_MAXBUS) - 1))

#define ATA_CURR_BASE(dev) (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])

From: Rogan Dawes rogan@dawes.za.net

--- drivers/mtd/cfi_flash.c | 22 +++++++++++++++++++++- 1 files changed, 21 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index dd394a8..74e9ade 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -291,6 +291,9 @@ static inline uchar flash_read_uchar (flash_info_t * info, uint offset) uchar *cp; uchar retval;

+#if 1 // test-only + offset = offset * 2; +#endif cp = flash_map (info, 0, offset); #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) retval = flash_read8(cp); @@ -308,6 +311,9 @@ static inline ushort flash_read_word (flash_info_t * info, uint offset) { ushort *addr, retval;

+#if 1 // test-only + offset = offset * 2; +#endif addr = flash_map (info, 0, offset); retval = flash_read16 (addr); flash_unmap (info, 0, offset, addr); @@ -328,6 +334,9 @@ static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, #ifdef DEBUG int x; #endif +#if 1 // test-only + offset = offset * 2; +#endif addr = flash_map (info, sect, offset);

#ifdef DEBUG @@ -363,6 +372,9 @@ void flash_write_cmd (flash_info_t * info, flash_sect_t sect, void *addr; cfiword_t cword;

+#if 1 // test-only + offset = offset * 2; +#endif addr = flash_map (info, sect, offset); flash_make_cmd (info, cmd, &cword); switch (info->portwidth) { @@ -420,6 +432,9 @@ static int flash_isequal (flash_info_t * info, flash_sect_t sect, cfiword_t cword; int retval;

+#if 1 // test-only + offset = offset * 2; +#endif addr = flash_map (info, sect, offset); flash_make_cmd (info, cmd, &cword);

@@ -1762,6 +1777,7 @@ static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) info->addr_unlock1 = 0x555; info->addr_unlock2 = 0x2aa;

+#if 0 // test-only /* * modify the unlock address if we are * in compatibility mode @@ -1776,6 +1792,7 @@ static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) info->addr_unlock1 = 0xaaa; info->addr_unlock2 = 0x555; } +#endif

info->name = "CFI conformant"; return 1; @@ -1942,11 +1959,13 @@ ulong flash_get_size (phys_addr_t base, int banknum) debug ("cfi version is 0x%04x\n", info->cfi_version);

size_ratio = info->portwidth / info->chipwidth; +#if 0 // test-only /* if the chip is x8/x16 reduce the ratio by half */ if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { size_ratio >>= 1; } +#endif debug ("size_ratio %d port %d bits chip %d bits\n", size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); @@ -2034,12 +2053,13 @@ ulong flash_get_size (phys_addr_t base, int banknum) /* round up when converting to ms */ info->write_tout = (tmp + 999) / 1000; info->flash_id = FLASH_MAN_CFI; +#if 0 if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { /* XXX - Need to test on x8/x16 in parallel. */ info->portwidth >>= 1; } - +#endif flash_write_cmd (info, 0, 0, info->cmd_reset); }

From: Rogan Dawes rogan@dawes.za.net

--- common/image.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/image.c b/common/image.c index f63a2ff..108bb44 100644 --- a/common/image.c +++ b/common/image.c @@ -950,7 +950,7 @@ int boot_get_ramdisk (int argc, char * const argv[], bootm_headers_t *images, return 1; }

-#if defined(CONFIG_B2) || defined(CONFIG_EVB4510) || defined(CONFIG_ARMADILLO) +#if defined(CONFIG_B2) || defined(CONFIG_EVB4510) || defined(CONFIG_ARMADILLO) || defined(CONFIG_MACH_DNS323) /* * We need to copy the ramdisk to SRAM to let Linux boot */ @@ -958,7 +958,7 @@ int boot_get_ramdisk (int argc, char * const argv[], bootm_headers_t *images, memmove ((void *)rd_load, (uchar *)rd_data, rd_len); rd_data = rd_load; } -#endif /* CONFIG_B2 || CONFIG_EVB4510 || CONFIG_ARMADILLO */ +#endif /* CONFIG_B2 || CONFIG_EVB4510 || CONFIG_ARMADILLO || CONFIG_MACH_DNS323 */

} else if (images->legacy_hdr_valid && image_check_type (&images->legacy_hdr_os_copy, IH_TYPE_MULTI)) {

From: Rogan Dawes rogan@dawes.za.net

Based on that of the edminiv2, with a few additions

The image is configured to boot vendor kernels seamlessly. i.e. the kernel boot logs should be identical between the vendor bootloader and this mainline version.

Note that the vendor flash layout does not allow space for saving environment variables. All env variables are compiled in to the vendor bootloader, and saveenv is not provided.

According to the flash layout, the smallest segments are at the start of the flash chip, which conflicts with mtd0, used to save the NAS configuration by the vendor firmware. Consequently, if you intend to keep the vendor firmware, do not save any additional environment variables, or change existing ones.

GPIO pins are not configured, as they do not match the layout for the EDMiniv2. That configuration causes the kernel to shutdown, as it detects that the power button is pressed. --- board/D-Link/dns323_b1/Makefile | 53 +++++++ board/D-Link/dns323_b1/config.mk | 28 ++++ board/D-Link/dns323_b1/dns323_b1.c | 78 +++++++++++ board/D-Link/dns323_b1/dns323_b1.h | 41 ++++++ boards.cfg | 1 + include/configs/dns323_b1.h | 270 ++++++++++++++++++++++++++++++++++++ 6 files changed, 471 insertions(+), 0 deletions(-) create mode 100644 board/D-Link/dns323_b1/Makefile create mode 100644 board/D-Link/dns323_b1/config.mk create mode 100644 board/D-Link/dns323_b1/dns323_b1.c create mode 100644 board/D-Link/dns323_b1/dns323_b1.h create mode 100644 include/configs/dns323_b1.h

diff --git a/board/D-Link/dns323_b1/Makefile b/board/D-Link/dns323_b1/Makefile new file mode 100644 index 0000000..39bf546 --- /dev/null +++ b/board/D-Link/dns323_b1/Makefile @@ -0,0 +1,53 @@ +# +# Copyright (C) 2010 Albert ARIBAUD albert.aribaud@free.fr +# +# Based on original Kirkwood support which is +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := dns323_b1.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/D-Link/dns323_b1/config.mk b/board/D-Link/dns323_b1/config.mk new file mode 100644 index 0000000..ce6760d --- /dev/null +++ b/board/D-Link/dns323_b1/config.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2010 Albert ARIBAUD albert.aribaud@free.fr +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# TEXT_BASE must equal the intended FLASH location of u-boot. +CONFIG_SYS_TEXT_BASE = 0xfffd0000 diff --git a/board/D-Link/dns323_b1/dns323_b1.c b/board/D-Link/dns323_b1/dns323_b1.c new file mode 100644 index 0000000..b9a66df --- /dev/null +++ b/board/D-Link/dns323_b1/dns323_b1.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2010 Albert ARIBAUD albert.aribaud@free.fr + * + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/orion5x.h> +#include "dns323_b1.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* arch number of board */ + gd->bd->bi_arch_number = MACH_TYPE_DNS323; + + /* boot parameter start at 256th byte of RAM base */ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + return 0; +} + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/D-Link/dns323_b1/dns323_b1.h b/board/D-Link/dns323_b1/dns323_b1.h new file mode 100644 index 0000000..5b3c4e6 --- /dev/null +++ b/board/D-Link/dns323_b1/dns323_b1.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2009 + * Net Insight <www.netinsight.net> + * Written-by: Simon Kagstrom simon.kagstrom@netinsight.net + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __DNS323_BASE_H +#define __DNS323_BASE_H + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __DNS323_BASE_H */ diff --git a/boards.cfg b/boards.cfg index 45c3102..32c26ab 100644 --- a/boards.cfg +++ b/boards.cfg @@ -104,6 +104,7 @@ jadecpu arm arm926ejs jadecpu syteco imx27lite arm arm926ejs imx27lite logicpd mx27 magnesium arm arm926ejs imx27lite logicpd mx27 omap5912osk arm arm926ejs - ti omap +dns323_b1 arm arm926ejs - D-Link orion5x edminiv2 arm arm926ejs - LaCie orion5x dkb arm arm926ejs - Marvell pantheon ca9x4_ct_vxp arm armv7 vexpress armltd diff --git a/include/configs/dns323_b1.h b/include/configs/dns323_b1.h new file mode 100644 index 0000000..db18621 --- /dev/null +++ b/include/configs/dns323_b1.h @@ -0,0 +1,270 @@ +/* + * Copyright (C) 2010 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_DNS323_B1_H +#define _CONFIG_DNS323_B1_H + +/* + * Version number information + */ + +#define CONFIG_IDENT_STRING " DNS323B1" + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_FEROCEON 1 /* CPU Core subversion */ +#define CONFIG_ORION5X 1 /* SOC Family Name */ +#define CONFIG_88F5182 1 /* SOC Name */ +#define CONFIG_MACH_DNS323 1 /* Machine type */ +#define CONFIG_MARVELL_TAG /* Match Vendor U-Boot */ + +/* Skip lowlevel init - + * makes an image suitable for chaining from another u-boot loader + * This config has not been tested for flashing + */ +#define CONFIG_SKIP_LOWLEVEL_INIT 1 + +/* + * CLKs configurations + */ + +#define CONFIG_SYS_HZ 1000 + +/* + * Board-specific values for Orion5x MPP low level init: + * - MPPs 12 to 15 are SATA LEDs (mode 5) + * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for + * MPP16 to MPP19, mode 0 for others + * + * Settings for DNS323 B1 have not been determined, set all to 0 + */ + +#define ORION5X_MPP0_7 0x00000000 +#define ORION5X_MPP8_15 0x00000000 +#define ORION5X_MPP16_23 0x00000000 + +/* + * Board-specific values for Orion5x GPIO low level init: + * - GPIO3 is input (RTC interrupt) + * - GPIO16 is Power LED control (0 = on, 1 = off) + * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) + * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) + * - Last GPIO is 26, further bits are supposed to be 0. + * Enable mask has ones for INPUT, 0 for OUTPUT. + * Default is LED ON. + */ + +#define ORION5X_GPIO_OUT_ENABLE 0x00000000 +#define ORION5X_GPIO_OUT_VALUE 0x00000000 + +/* + * NS16550 Configuration + */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } + +/* + * FLASH configuration + */ + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BASE 0xff800000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +#define ORION5X_ADR_BOOTROM CONFIG_SYS_FLASH_BASE +#define ORION5X_SZ_BOOTROM (8 * 1024 * 1024) + + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_PROTECTION 1 + +#define CONFIG_SYS_FLASH_EMPTY_INFO + +/* auto boot */ +#define CONFIG_BOOTDELAY -1 /* default disable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "DNS323B1> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ +/* + * Commands configuration - using default command set for now + */ +#include <config_cmd_default.h> +#define CONFIG_CMD_IDE +#define CONFIG_CMD_I2C + +/* + * Network + */ + +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE /* Enable Marvell GbE Driver */ +#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ +#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ +#define CONFIG_PHY_BASE_ADR 0x8 +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_CMD_DHCP +#endif + +/* + * IDE + */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +/* ED Mini V has an IDE-compatible SATA connector for port 1 */ +#define CONFIG_MVSATA_IDE +#define CONFIG_MVSATA_IDE_USE_PORT1 +/* Needs byte-swapping for ATA data register */ +#define CONFIG_IDE_SWAP_IO +/* Data, registers and alternate blocks are at the same offset */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) +#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) +#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) +/* Each 8-bit ATA register is aligned to a 4-bytes address */ +#define CONFIG_SYS_ATA_STRIDE 4 +/* Controller supports 48-bits LBA addressing */ +#define CONFIG_LBA48 +/* A single bus, a single device */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 2 +/* ATA registers base is at SATA controller base */ +#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE +#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET ORION5X_SATA_PORT1_OFFSET +/* end of IDE defines */ +#endif /* CMD_IDE */ + +/* + * I2C related stuff + */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* + * Environment variables configurations + * + * NB: If you save environment variables, they will overwrite + * the configuration saved by the vendor firmware, and will in turn + * be overwritten by vendor firmware if executed. Only save U-Boot + * environment variables if you are not using the vendor firmware. + * Unfortunately, vendor U-Boot did not make place for saving the + * environment. + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x0000 /* env starts here */ + +#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,115200 :::DB88FXX81:egiga0:none" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootcmd=bootm FF820000 FF9A0000\0" \ + "machid=20e\0" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +/* size in bytes reserved for initial data */ + +/* + * Other required minimal configurations + */ +#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 4 /* Match vendor U-Boot */ + +#define CONFIG_STACKSIZE 0x00100000 +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_MEMTEST_START 0x00400000 +#define CONFIG_SYS_MEMTEST_END 0x007fffff +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 +#define CONFIG_SYS_MAXARGS 16 + +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LONGHELP + +#undef CONFIG_CONSOLE_INFO_QUIET + +// test-only: nice to have... +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ + +#endif /* _CONFIG_DNS323_B1_H */