[PATCH 1/5] sysreset: syscon: Don't assume default value for offset and mask property
From: Bin Meng bin.meng@windriver.com
Per the DT binding, <offset> is a required property. Let's abort the probe if it is missing. For the <mask> property, current codes assume a default value of zero, which is not correct either.
Signed-off-by: Bin Meng bin.meng@windriver.com ---
drivers/sysreset/sysreset_syscon.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c index f64701a..caf2482 100644 --- a/drivers/sysreset/sysreset_syscon.c +++ b/drivers/sysreset/sysreset_syscon.c @@ -41,6 +41,7 @@ static struct sysreset_ops syscon_reboot_ops = { int syscon_reboot_probe(struct udevice *dev) { struct syscon_reboot_priv *priv = dev_get_priv(dev); + int err;
priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap"); if (IS_ERR(priv->regmap)) { @@ -48,8 +49,17 @@ int syscon_reboot_probe(struct udevice *dev) return -ENODEV; }
- priv->offset = dev_read_u32_default(dev, "offset", 0); - priv->mask = dev_read_u32_default(dev, "mask", 0); + err = dev_read_u32(dev, "offset", &priv->offset); + if (err) { + pr_err("unable to find offset\n"); + return -ENOENT; + } + + err = dev_read_u32(dev, "mask", &priv->mask); + if (err) { + pr_err("unable to find mask\n"); + return -ENOENT; + }
return 0; }
From: Bin Meng bin.meng@windriver.com
Per the DT binding, <mask> and <value> property can have either one or both, and if <value> is missing, <mask> should be used, which is what current U-Boot sysreset_syscon driver supports.
This adds support to the <value> property to the driver, and <mask> semantics is updated to really be a mask to the value if both exist.
Signed-off-by: Bin Meng bin.meng@windriver.com ---
drivers/sysreset/sysreset_syscon.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c index caf2482..1c47486 100644 --- a/drivers/sysreset/sysreset_syscon.c +++ b/drivers/sysreset/sysreset_syscon.c @@ -19,6 +19,7 @@ struct syscon_reboot_priv { struct regmap *regmap; unsigned int offset; unsigned int mask; + unsigned int value; };
static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type) @@ -29,7 +30,7 @@ static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type) if (type != driver_data) return -EPROTONOSUPPORT;
- regmap_write(priv->regmap, priv->offset, priv->mask); + regmap_update_bits(priv->regmap, priv->offset, priv->mask, priv->value);
return -EINPROGRESS; } @@ -42,6 +43,7 @@ int syscon_reboot_probe(struct udevice *dev) { struct syscon_reboot_priv *priv = dev_get_priv(dev); int err; + int mask_err, value_err;
priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap"); if (IS_ERR(priv->regmap)) { @@ -55,10 +57,20 @@ int syscon_reboot_probe(struct udevice *dev) return -ENOENT; }
- err = dev_read_u32(dev, "mask", &priv->mask); - if (err) { - pr_err("unable to find mask\n"); - return -ENOENT; + mask_err = dev_read_u32(dev, "mask", &priv->mask); + value_err = dev_read_u32(dev, "value", &priv->value); + if (mask_err && value_err) { + pr_err("unable to find mask and value\n"); + return -EINVAL; + } + + if (value_err) { + /* support old binding */ + priv->value = priv->mask; + priv->mask = 0xffffffff; + } else if (mask_err) { + /* support value without mask*/ + priv->mask = 0xffffffff; }
return 0;
On Mon, 22 Jun 2020 at 23:30, Bin Meng bmeng.cn@gmail.com wrote:
From: Bin Meng bin.meng@windriver.com
Per the DT binding, <mask> and <value> property can have either one or both, and if <value> is missing, <mask> should be used, which is what current U-Boot sysreset_syscon driver supports.
This adds support to the <value> property to the driver, and <mask> semantics is updated to really be a mask to the value if both exist.
Signed-off-by: Bin Meng bin.meng@windriver.com
drivers/sysreset/sysreset_syscon.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 23 June 2020 11:00 To: Rick Chen rick@andestech.com; Simon Glass sjg@chromium.org; Pragnesh Patel pragnesh.patel@sifive.com; Sagar Kadam sagar.kadam@sifive.com; U-Boot Mailing List u-boot@lists.denx.de Cc: Bin Meng bin.meng@windriver.com Subject: [PATCH 2/5] sysreset: syscon: Support value property
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From: Bin Meng bin.meng@windriver.com
Per the DT binding, <mask> and <value> property can have either one or both, and if <value> is missing, <mask> should be used, which is what current U-Boot sysreset_syscon driver supports.
This adds support to the <value> property to the driver, and <mask> semantics is updated to really be a mask to the value if both exist.
Signed-off-by: Bin Meng bin.meng@windriver.com
drivers/sysreset/sysreset_syscon.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-)
Reviewed-by: Pragnesh Patel pragnesh.patel@sifive.com
From: Bin Meng bin.meng@windriver.com
SYSRESET uclass driver already provides all the reset APIs, hence exclude our own ad-hoc reset.c implementation.
Signed-off-by: Bin Meng bin.meng@windriver.com ---
arch/riscv/lib/Makefile | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index b5e9324..6c503ff 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -20,7 +20,9 @@ obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o endif obj-y += interrupts.o +ifeq ($(CONFIG_$(SPL_)SYSRESET),) obj-y += reset.o +endif obj-y += setjmp.o obj-$(CONFIG_$(SPL_)SMP) += smp.o obj-$(CONFIG_SPL_BUILD) += spl.o
Hello Bin,
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: Tuesday, June 23, 2020 11:00 AM To: Rick Chen rick@andestech.com; Simon Glass sjg@chromium.org; Pragnesh Patel pragnesh.patel@sifive.com; Sagar Kadam sagar.kadam@sifive.com; U-Boot Mailing List u-boot@lists.denx.de Cc: Bin Meng bin.meng@windriver.com Subject: [PATCH 3/5] riscv: Do not build reset.c if SYSRESET is on
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
From: Bin Meng bin.meng@windriver.com
SYSRESET uclass driver already provides all the reset APIs, hence exclude our own ad-hoc reset.c implementation.
Signed-off-by: Bin Meng bin.meng@windriver.com
arch/riscv/lib/Makefile | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index b5e9324..6c503ff 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -20,7 +20,9 @@ obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o endif obj-y += interrupts.o +ifeq ($(CONFIG_$(SPL_)SYSRESET),) obj-y += reset.o +endif
I could see reset get's built when SYSRESET in enabled CC spl/arch/riscv/lib/interrupts.o CC spl/arch/riscv/lib/reset.o AS spl/arch/riscv/lib/setjmp.o
Should this have been? ifneq ($(CONFIG_$(SPL_)SYSRESET),)
Thanks & BR, Sagar
obj-y += setjmp.o obj-$(CONFIG_$(SPL_)SMP) += smp.o obj-$(CONFIG_SPL_BUILD) += spl.o -- 2.7.4
Hi Sagar,
On Fri, Jun 26, 2020 at 1:14 AM Sagar Kadam sagar.kadam@sifive.com wrote:
Hello Bin,
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: Tuesday, June 23, 2020 11:00 AM To: Rick Chen rick@andestech.com; Simon Glass sjg@chromium.org; Pragnesh Patel pragnesh.patel@sifive.com; Sagar Kadam sagar.kadam@sifive.com; U-Boot Mailing List u-boot@lists.denx.de Cc: Bin Meng bin.meng@windriver.com Subject: [PATCH 3/5] riscv: Do not build reset.c if SYSRESET is on
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
From: Bin Meng bin.meng@windriver.com
SYSRESET uclass driver already provides all the reset APIs, hence exclude our own ad-hoc reset.c implementation.
Signed-off-by: Bin Meng bin.meng@windriver.com
arch/riscv/lib/Makefile | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index b5e9324..6c503ff 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -20,7 +20,9 @@ obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o endif obj-y += interrupts.o +ifeq ($(CONFIG_$(SPL_)SYSRESET),) obj-y += reset.o +endif
I could see reset get's built when SYSRESET in enabled CC spl/arch/riscv/lib/interrupts.o CC spl/arch/riscv/lib/reset.o AS spl/arch/riscv/lib/setjmp.o
This is because we don't enable CONFIG_SPL_SYSRESET in the board config. For SPL, normally we don't need to reset.
Should this have been? ifneq ($(CONFIG_$(SPL_)SYSRESET),)
Regards, Bin
Hi Bin,
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: Friday, June 26, 2020 7:26 AM To: Sagar Kadam sagar.kadam@sifive.com Cc: Rick Chen rick@andestech.com; Simon Glass sjg@chromium.org; Pragnesh Patel pragnesh.patel@sifive.com; U-Boot Mailing List <u- boot@lists.denx.de>; Bin Meng bin.meng@windriver.com Subject: Re: [PATCH 3/5] riscv: Do not build reset.c if SYSRESET is on
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Hi Sagar,
On Fri, Jun 26, 2020 at 1:14 AM Sagar Kadam sagar.kadam@sifive.com wrote:
Hello Bin,
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: Tuesday, June 23, 2020 11:00 AM To: Rick Chen rick@andestech.com; Simon Glass
Pragnesh Patel pragnesh.patel@sifive.com; Sagar Kadam sagar.kadam@sifive.com; U-Boot Mailing List u-boot@lists.denx.de Cc: Bin Meng bin.meng@windriver.com Subject: [PATCH 3/5] riscv: Do not build reset.c if SYSRESET is on
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
From: Bin Meng bin.meng@windriver.com
SYSRESET uclass driver already provides all the reset APIs, hence exclude our own ad-hoc reset.c implementation.
Signed-off-by: Bin Meng bin.meng@windriver.com
arch/riscv/lib/Makefile | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index b5e9324..6c503ff 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -20,7 +20,9 @@ obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o endif obj-y += interrupts.o +ifeq ($(CONFIG_$(SPL_)SYSRESET),) obj-y += reset.o +endif
I could see reset get's built when SYSRESET in enabled CC spl/arch/riscv/lib/interrupts.o CC spl/arch/riscv/lib/reset.o AS spl/arch/riscv/lib/setjmp.o
This is because we don't enable CONFIG_SPL_SYSRESET in the board config. For SPL, normally we don't need to reset.
Ok. Thanks for clarifying. Looks good.
Should this have been? ifneq ($(CONFIG_$(SPL_)SYSRESET),)
Regards, Bin
Reviewed-by: Sagar Kadam sagar.kadam@sifive.com
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 23 June 2020 11:00 To: Rick Chen rick@andestech.com; Simon Glass sjg@chromium.org; Pragnesh Patel pragnesh.patel@sifive.com; Sagar Kadam sagar.kadam@sifive.com; U-Boot Mailing List u-boot@lists.denx.de Cc: Bin Meng bin.meng@windriver.com Subject: [PATCH 3/5] riscv: Do not build reset.c if SYSRESET is on
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
From: Bin Meng bin.meng@windriver.com
SYSRESET uclass driver already provides all the reset APIs, hence exclude our own ad-hoc reset.c implementation.
Signed-off-by: Bin Meng bin.meng@windriver.com
arch/riscv/lib/Makefile | 2 ++ 1 file changed, 2 insertions(+)
Reviewed-by: Pragnesh Patel pragnesh.patel@sifive.com
From: Bin Meng bin.meng@windriver.com
This adds syscon reboot and poweroff support to QEMU RISC-V.
Signed-off-by: Bin Meng bin.meng@windriver.com ---
board/emulation/qemu-riscv/Kconfig | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index ad99b08..617c4aa 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -53,5 +53,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply NVME imply SPL_RAM_SUPPORT imply SPL_RAM_DEVICE + imply SYSRESET + imply SYSRESET_SYSCON + imply CMD_POWEROFF + imply SYSRESET_CMD_POWEROFF
endif
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 23 June 2020 11:00 To: Rick Chen rick@andestech.com; Simon Glass sjg@chromium.org; Pragnesh Patel pragnesh.patel@sifive.com; Sagar Kadam sagar.kadam@sifive.com; U-Boot Mailing List u-boot@lists.denx.de Cc: Bin Meng bin.meng@windriver.com Subject: [PATCH 4/5] riscv: qemu: Add syscon reboot and poweroff support
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From: Bin Meng bin.meng@windriver.com
This adds syscon reboot and poweroff support to QEMU RISC-V.
Signed-off-by: Bin Meng bin.meng@windriver.com
board/emulation/qemu-riscv/Kconfig | 4 ++++ 1 file changed, 4 insertions(+)
Reviewed-by: Pragnesh Patel pragnesh.patel@sifive.com
From: Bin Meng bin.meng@windriver.com
The HiFive Unleashed board wires GPIO pin#10 to the input of the system reset signal. This adds gpio reboot support.
Signed-off-by: Bin Meng bin.meng@windriver.com ---
board/sifive/fu540/Kconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 86193d7..6f65681 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -65,5 +65,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SMP imply MISC imply SIFIVE_OTP + imply SYSRESET + imply SYSRESET_GPIO
endif
Hi,
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: Tuesday, June 23, 2020 11:00 AM To: Rick Chen rick@andestech.com; Simon Glass sjg@chromium.org; Pragnesh Patel pragnesh.patel@sifive.com; Sagar Kadam sagar.kadam@sifive.com; U-Boot Mailing List u-boot@lists.denx.de Cc: Bin Meng bin.meng@windriver.com Subject: [PATCH 5/5] riscv: sifive: fu540: Add gpio-restart support
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
From: Bin Meng bin.meng@windriver.com
The HiFive Unleashed board wires GPIO pin#10 to the input of the system reset signal. This adds gpio reboot support.
Signed-off-by: Bin Meng bin.meng@windriver.com
board/sifive/fu540/Kconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 86193d7..6f65681 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -65,5 +65,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SMP imply MISC imply SIFIVE_OTP
imply SYSRESETimply SYSRESET_GPIO
Looks Good. Reviewed-by: Sagar Kadam sagar.kadam@sifive.com Tested-by: Sagar Kadam sagar.kadam@sifive.com
endif
2.7.4
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 23 June 2020 11:00 To: Rick Chen rick@andestech.com; Simon Glass sjg@chromium.org; Pragnesh Patel pragnesh.patel@sifive.com; Sagar Kadam sagar.kadam@sifive.com; U-Boot Mailing List u-boot@lists.denx.de Cc: Bin Meng bin.meng@windriver.com Subject: [PATCH 5/5] riscv: sifive: fu540: Add gpio-restart support
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
From: Bin Meng bin.meng@windriver.com
The HiFive Unleashed board wires GPIO pin#10 to the input of the system reset signal. This adds gpio reboot support.
Signed-off-by: Bin Meng bin.meng@windriver.com
board/sifive/fu540/Kconfig | 2 ++ 1 file changed, 2 insertions(+)
Reviewed-by: Pragnesh Patel pragnesh.patel@sifive.com
On Mon, 22 Jun 2020 at 23:30, Bin Meng bmeng.cn@gmail.com wrote:
From: Bin Meng bin.meng@windriver.com
Per the DT binding, <offset> is a required property. Let's abort the probe if it is missing. For the <mask> property, current codes assume a default value of zero, which is not correct either.
Signed-off-by: Bin Meng bin.meng@windriver.com
drivers/sysreset/sysreset_syscon.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 23 June 2020 11:00 To: Rick Chen rick@andestech.com; Simon Glass sjg@chromium.org; Pragnesh Patel pragnesh.patel@sifive.com; Sagar Kadam sagar.kadam@sifive.com; U-Boot Mailing List u-boot@lists.denx.de Cc: Bin Meng bin.meng@windriver.com Subject: [PATCH 1/5] sysreset: syscon: Don't assume default value for offset and mask property
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From: Bin Meng bin.meng@windriver.com
Per the DT binding, <offset> is a required property. Let's abort the probe if it is missing. For the <mask> property, current codes assume a default value of zero, which is not correct either.
Signed-off-by: Bin Meng bin.meng@windriver.com
drivers/sysreset/sysreset_syscon.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)
Reviewed-by: Pragnesh Patel pragnesh.patel@sifive.com
Hi Rick,
On Fri, Jun 26, 2020 at 1:53 PM Pragnesh Patel pragnesh.patel@sifive.com wrote:
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 23 June 2020 11:00 To: Rick Chen rick@andestech.com; Simon Glass sjg@chromium.org; Pragnesh Patel pragnesh.patel@sifive.com; Sagar Kadam sagar.kadam@sifive.com; U-Boot Mailing List u-boot@lists.denx.de Cc: Bin Meng bin.meng@windriver.com Subject: [PATCH 1/5] sysreset: syscon: Don't assume default value for offset and mask property
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
From: Bin Meng bin.meng@windriver.com
Per the DT binding, <offset> is a required property. Let's abort the probe if it is missing. For the <mask> property, current codes assume a default value of zero, which is not correct either.
Signed-off-by: Bin Meng bin.meng@windriver.com
drivers/sysreset/sysreset_syscon.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)
Reviewed-by: Pragnesh Patel pragnesh.patel@sifive.com
Would you please take the remaining 3 patches soon? http://patchwork.ozlabs.org/project/uboot/list/?series=185161
Regards, Bin
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