[U-Boot] [PATCH 0/4] ARM: s3c44b0: remove remainders of dead board
Commit 5dc5f36 removed the support for B2 board, which was the last S3C44B0 SoC board.
These series of patches remove s3c44b0-specific code and drivers:
- arch/arm/cpu/s3c44b0/* - arch/arm/include/asm/arch-s3c44b0/* - drivers/i2c/s3c44b0_i2c.c - drivers/serial/serial_s3c44b0.c - drivers/rtc/s3c44b0_rtc.c
Cc: Wolfgang Denk wd@denx.de Cc: Andrea Scian andrea.scian@dave-tech.it
Masahiro Yamada (4): ARM: s3c44b0: remove remainders of dead board drivers: s3c44b0_i2c: delete an unused driver drivers: serial_s3c44b0: delete an unused driver drivers: s3c44b0_rtc: delete an unused driver
README | 1 - arch/arm/cpu/s3c44b0/Makefile | 34 --- arch/arm/cpu/s3c44b0/cache.c | 74 ------- arch/arm/cpu/s3c44b0/config.mk | 18 -- arch/arm/cpu/s3c44b0/cpu.c | 58 ----- arch/arm/cpu/s3c44b0/start.S | 228 -------------------- arch/arm/cpu/s3c44b0/timer.c | 102 --------- arch/arm/include/asm/arch-s3c44b0/hardware.h | 281 ------------------------ doc/driver-model/UDM-rtc.txt | 15 +- doc/driver-model/UDM-serial.txt | 16 +- drivers/i2c/Makefile | 1 - drivers/i2c/s3c44b0_i2c.c | 299 -------------------------- drivers/rtc/Makefile | 1 - drivers/rtc/s3c44b0_rtc.c | 84 -------- drivers/serial/Makefile | 1 - drivers/serial/serial.c | 2 - drivers/serial/serial_s3c44b0.c | 216 ------------------- 17 files changed, 11 insertions(+), 1420 deletions(-) delete mode 100644 arch/arm/cpu/s3c44b0/Makefile delete mode 100644 arch/arm/cpu/s3c44b0/cache.c delete mode 100644 arch/arm/cpu/s3c44b0/config.mk delete mode 100644 arch/arm/cpu/s3c44b0/cpu.c delete mode 100644 arch/arm/cpu/s3c44b0/start.S delete mode 100644 arch/arm/cpu/s3c44b0/timer.c delete mode 100644 arch/arm/include/asm/arch-s3c44b0/hardware.h delete mode 100644 drivers/i2c/s3c44b0_i2c.c delete mode 100644 drivers/rtc/s3c44b0_rtc.c delete mode 100644 drivers/serial/serial_s3c44b0.c
Because commit 5dc5f36 removed B2 board support, arch/arm/cpu/s3c44b0/* and arch/arm/include/asm/arch-s3c44b0/* are not necessary anymore.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Wolfgang Denk wd@denx.de Cc: Andrea Scian andrea.scian@dave-tech.it --- README | 1 - arch/arm/cpu/s3c44b0/Makefile | 34 ---- arch/arm/cpu/s3c44b0/cache.c | 74 ------- arch/arm/cpu/s3c44b0/config.mk | 18 -- arch/arm/cpu/s3c44b0/cpu.c | 58 ------ arch/arm/cpu/s3c44b0/start.S | 228 --------------------- arch/arm/cpu/s3c44b0/timer.c | 102 ---------- arch/arm/include/asm/arch-s3c44b0/hardware.h | 281 -------------------------- 8 files changed, 796 deletions(-) delete mode 100644 arch/arm/cpu/s3c44b0/Makefile delete mode 100644 arch/arm/cpu/s3c44b0/cache.c delete mode 100644 arch/arm/cpu/s3c44b0/config.mk delete mode 100644 arch/arm/cpu/s3c44b0/cpu.c delete mode 100644 arch/arm/cpu/s3c44b0/start.S delete mode 100644 arch/arm/cpu/s3c44b0/timer.c delete mode 100644 arch/arm/include/asm/arch-s3c44b0/hardware.h
diff --git a/README b/README index 3918807..f8b92d0 100644 --- a/README +++ b/README @@ -144,7 +144,6 @@ Directory Hierarchy: /arm1136 Files specific to ARM 1136 CPUs /ixp Files specific to Intel XScale IXP CPUs /pxa Files specific to Intel XScale PXA CPUs - /s3c44b0 Files specific to Samsung S3C44B0 CPUs /sa1100 Files specific to Intel StrongARM SA1100 CPUs /lib Architecture specific library files /avr32 Files generic to AVR32 architecture diff --git a/arch/arm/cpu/s3c44b0/Makefile b/arch/arm/cpu/s3c44b0/Makefile deleted file mode 100644 index 39fdbf8..0000000 --- a/arch/arm/cpu/s3c44b0/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o - -COBJS += cache.o -COBJS += cpu.o -COBJS += timer.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/s3c44b0/cache.c b/arch/arm/cpu/s3c44b0/cache.c deleted file mode 100644 index aeee02d..0000000 --- a/arch/arm/cpu/s3c44b0/cache.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/hardware.h> - -static void s3c44b0_flush_cache(void) -{ - volatile int i; - /* flush cycle */ - for(i=0x10002000;i<0x10004800;i+=16) - { - *((int *)i)=0x0; - } -} - -void icache_enable (void) -{ - ulong reg; - - s3c44b0_flush_cache(); - - /* - Init cache - Non-cacheable area (everything outside RAM) - 0x0000:0000 - 0x0C00:0000 - */ - NCACHBE0 = 0xC0000000; - NCACHBE1 = 0x00000000; - - /* - Enable chache - */ - reg = SYSCFG; - reg |= 0x00000006; /* 8kB */ - SYSCFG = reg; -} - -void icache_disable (void) -{ - ulong reg; - - reg = SYSCFG; - reg &= ~0x00000006; /* 8kB */ - SYSCFG = reg; -} - -int icache_status (void) -{ - return 0; -} - -void dcache_enable (void) -{ - icache_enable(); -} - -void dcache_disable (void) -{ - icache_disable(); -} - -int dcache_status (void) -{ - return dcache_status(); -} diff --git a/arch/arm/cpu/s3c44b0/config.mk b/arch/arm/cpu/s3c44b0/config.mk deleted file mode 100644 index b902ca3..0000000 --- a/arch/arm/cpu/s3c44b0/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH <www.elinos.com> -# Marius Groeger mgroeger@sysgo.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/s3c44b0/cpu.c b/arch/arm/cpu/s3c44b0/cpu.c deleted file mode 100644 index fa93150..0000000 --- a/arch/arm/cpu/s3c44b0/cpu.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * S3C44B0 CPU specific code - */ - -#include <common.h> -#include <command.h> -#include <asm/hardware.h> - -int arch_cpu_init (void) -{ - icache_enable(); - - return 0; -} - -int cleanup_before_linux (void) -{ - /* - cache memory should be enabled before calling - Linux to make the kernel uncompression faster - */ - icache_enable(); - - disable_interrupts (); - - return 0; -} - -void reset_cpu (ulong addr) -{ - /* - reset the cpu using watchdog - */ - - /* Disable the watchdog.*/ - WTCON&=~(1<<5); - - /* set the timeout value to a short time... */ - WTCNT = 0x1; - - /* Enable the watchdog. */ - WTCON|=1; - WTCON|=(1<<5); - - while(1) { - /*NOP*/ - } -} diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S deleted file mode 100644 index 6a59592..0000000 --- a/arch/arm/cpu/s3c44b0/start.S +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Startup Code for S3C44B0 CPU-core - * - * (C) Copyright 2004 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> -#include <version.h> - -/* - * Jump vector table - */ - - -.globl _start -_start: b reset - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * relocate u-boot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - bl lowlevel_init -#endif - - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - - bx lr - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - -#define INTCON (0x01c00000+0x200000) -#define INTMSK (0x01c00000+0x20000c) -#define LOCKTIME (0x01c00000+0x18000c) -#define PLLCON (0x01c00000+0x180000) -#define CLKCON (0x01c00000+0x180004) -#define WTCON (0x01c00000+0x130000) -cpu_init_crit: - /* disable watch dog */ - ldr r0, =WTCON - ldr r1, =0x0 - str r1, [r0] - - /* - * mask all IRQs by clearing all bits in the INTMRs - */ - ldr r1,=INTMSK - ldr r0, =0x03fffeff - str r0, [r1] - - ldr r1, =INTCON - ldr r0, =0x05 - str r0, [r1] - - /* Set Clock Control Register */ - ldr r1, =LOCKTIME - ldrb r0, =800 - strb r0, [r1] - - ldr r1, =PLLCON - -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */ -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */ -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - - str r0, [r1] - - ldr r1,=CLKCON - ldr r0, =0x7ff8 - str r0, [r1] - - mov pc, lr - - -/*************************************************/ -/* interrupt vectors */ -/*************************************************/ -real_vectors: - b reset - b undefined_instruction - b software_interrupt - b prefetch_abort - b data_abort - b not_used - b irq - b fiq - -/*************************************************/ - -undefined_instruction: - mov r6, #3 - b reset - -software_interrupt: - mov r6, #4 - b reset - -prefetch_abort: - mov r6, #5 - b reset - -data_abort: - mov r6, #6 - b reset - -not_used: - /* we *should* never reach this */ - mov r6, #7 - b reset - -irq: - mov r6, #8 - b reset - -fiq: - mov r6, #9 - b reset diff --git a/arch/arm/cpu/s3c44b0/timer.c b/arch/arm/cpu/s3c44b0/timer.c deleted file mode 100644 index f25af7a..0000000 --- a/arch/arm/cpu/s3c44b0/timer.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/hardware.h> - -/* we always count down the max. */ -#define TIMER_LOAD_VAL 0xffff - -/* macro to read the 16 bit timer */ -#define READ_TIMER (TCNTO1 & 0xffff) - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ NOT supported -#endif - -static ulong timestamp; -static ulong lastdec; - -int timer_init (void) -{ - TCFG0 = 0x000000E9; - TCFG1 = 0x00000004; - TCON = 0x00000900; - TCNTB1 = TIMER_LOAD_VAL; - TCMPB1 = 0; - TCON = 0x00000B00; - TCON = 0x00000900; - - - lastdec = TCNTB1 = TIMER_LOAD_VAL; - timestamp = 0; - return 0; -} - -/* - * timer without interrupts - */ -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void __udelay (unsigned long usec) -{ - ulong tmo; - - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 8; - - tmo += get_timer (0); - - while (get_timer_masked () < tmo) - /*NOP*/; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 8; - } else { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*8); - } - - endtime = get_timer(0) + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} diff --git a/arch/arm/include/asm/arch-s3c44b0/hardware.h b/arch/arm/include/asm/arch-s3c44b0/hardware.h deleted file mode 100644 index 146e265..0000000 --- a/arch/arm/include/asm/arch-s3c44b0/hardware.h +++ /dev/null @@ -1,281 +0,0 @@ -/********************************************************/ -/* */ -/* Samsung S3C44B0 */ -/* tpu tapu@371.net */ -/* */ -/********************************************************/ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#define REGBASE 0x01c00000 -#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr)) -#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr)) -#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr)) - - -/*****************************/ -/* CPU Wrapper Registers */ -/*****************************/ - -#define SYSCFG REGL(0x000000) -#define NCACHBE0 REGL(0x000004) -#define NCACHBE1 REGL(0x000008) -#define SBUSCON REGL(0x040000) - -/************************************/ -/* Memory Controller Registers */ -/************************************/ - -#define BWSCON REGL(0x080000) -#define BANKCON0 REGL(0x080004) -#define BANKCON1 REGL(0x080008) -#define BANKCON2 REGL(0x08000c) -#define BANKCON3 REGL(0x080010) -#define BANKCON4 REGL(0x080014) -#define BANKCON5 REGL(0x080018) -#define BANKCON6 REGL(0x08001c) -#define BANKCON7 REGL(0x080020) -#define REFRESH REGL(0x080024) -#define BANKSIZE REGL(0x080028) -#define MRSRB6 REGL(0x08002c) -#define MRSRB7 REGL(0x080030) - -/*********************/ -/* UART Registers */ -/*********************/ - -#define ULCON0 REGL(0x100000) -#define ULCON1 REGL(0x104000) -#define UCON0 REGL(0x100004) -#define UCON1 REGL(0x104004) -#define UFCON0 REGL(0x100008) -#define UFCON1 REGL(0x104008) -#define UMCON0 REGL(0x10000c) -#define UMCON1 REGL(0x10400c) -#define UTRSTAT0 REGL(0x100010) -#define UTRSTAT1 REGL(0x104010) -#define UERSTAT0 REGL(0x100014) -#define UERSTAT1 REGL(0x104014) -#define UFSTAT0 REGL(0x100018) -#define UFSTAT1 REGL(0x104018) -#define UMSTAT0 REGL(0x10001c) -#define UMSTAT1 REGL(0x10401c) -#define UTXH0 REGB(0x100020) -#define UTXH1 REGB(0x104020) -#define URXH0 REGB(0x100024) -#define URXH1 REGB(0x104024) -#define UBRDIV0 REGL(0x100028) -#define UBRDIV1 REGL(0x104028) - -/*******************/ -/* SIO Registers */ -/*******************/ - -#define SIOCON REGL(0x114000) -#define SIODAT REGL(0x114004) -#define SBRDR REGL(0x114008) -#define ITVCNT REGL(0x11400c) -#define DCNTZ REGL(0x114010) - -/********************/ -/* IIS Registers */ -/********************/ - -#define IISCON REGL(0x118000) -#define IISMOD REGL(0x118004) -#define IISPSR REGL(0x118008) -#define IISFIFCON REGL(0x11800c) -#define IISFIF REGW(0x118010) - -/**************************/ -/* I/O Ports Registers */ -/**************************/ - -#define PCONA REGL(0x120000) -#define PDATA REGL(0x120004) -#define PCONB REGL(0x120008) -#define PDATB REGL(0x12000c) -#define PCONC REGL(0x120010) -#define PDATC REGL(0x120014) -#define PUPC REGL(0x120018) -#define PCOND REGL(0x12001c) -#define PDATD REGL(0x120020) -#define PUPD REGL(0x120024) -#define PCONE REGL(0x120028) -#define PDATE REGL(0x12002c) -#define PUPE REGL(0x120030) -#define PCONF REGL(0x120034) -#define PDATF REGL(0x120038) -#define PUPF REGL(0x12003c) -#define PCONG REGL(0x120040) -#define PDATG REGL(0x120044) -#define PUPG REGL(0x120048) -#define SPUCR REGL(0x12004c) -#define EXTINT REGL(0x120050) -#define EXTINTPND REGL(0x120054) - -/*********************************/ -/* WatchDog Timers Registers */ -/*********************************/ - -#define WTCON REGL(0x130000) -#define WTDAT REGL(0x130004) -#define WTCNT REGL(0x130008) - -/*********************************/ -/* A/D Converter Registers */ -/*********************************/ - -#define ADCCON REGL(0x140000) -#define ADCPSR REGL(0x140004) -#define ADCDAT REGL(0x140008) - -/***************************/ -/* PWM Timer Registers */ -/***************************/ - -#define TCFG0 REGL(0x150000) -#define TCFG1 REGL(0x150004) -#define TCON REGL(0x150008) -#define TCNTB0 REGL(0x15000c) -#define TCMPB0 REGL(0x150010) -#define TCNTO0 REGL(0x150014) -#define TCNTB1 REGL(0x150018) -#define TCMPB1 REGL(0x15001c) -#define TCNTO1 REGL(0x150020) -#define TCNTB2 REGL(0x150024) -#define TCMPB2 REGL(0x150028) -#define TCNTO2 REGL(0x15002c) -#define TCNTB3 REGL(0x150030) -#define TCMPB3 REGL(0x150034) -#define TCNTO3 REGL(0x150038) -#define TCNTB4 REGL(0x15003c) -#define TCMPB4 REGL(0x150040) -#define TCNTO4 REGL(0x150044) -#define TCNTB5 REGL(0x150048) -#define TCNTO5 REGL(0x15004c) - -/*********************/ -/* IIC Registers */ -/*********************/ - -#define IICCON REGL(0x160000) -#define IICSTAT REGL(0x160004) -#define IICADD REGL(0x160008) -#define IICDS REGL(0x16000c) - -/*********************/ -/* RTC Registers */ -/*********************/ - -#define RTCCON REGB(0x170040) -#define RTCALM REGB(0x170050) -#define ALMSEC REGB(0x170054) -#define ALMMIN REGB(0x170058) -#define ALMHOUR REGB(0x17005c) -#define ALMDAY REGB(0x170060) -#define ALMMON REGB(0x170064) -#define ALMYEAR REGB(0x170068) -#define RTCRST REGB(0x17006c) -#define BCDSEC REGB(0x170070) -#define BCDMIN REGB(0x170074) -#define BCDHOUR REGB(0x170078) -#define BCDDAY REGB(0x17007c) -#define BCDDATE REGB(0x170080) -#define BCDMON REGB(0x170084) -#define BCDYEAR REGB(0x170088) -#define TICINT REGB(0x17008c) - -/*********************************/ -/* Clock & Power Registers */ -/*********************************/ - -#define PLLCON REGL(0x180000) -#define CLKCON REGL(0x180004) -#define CLKSLOW REGL(0x180008) -#define LOCKTIME REGL(0x18000c) - -/**************************************/ -/* Interrupt Controller Registers */ -/**************************************/ - -#define INTCON REGL(0x200000) -#define INTPND REGL(0x200004) -#define INTMOD REGL(0x200008) -#define INTMSK REGL(0x20000c) -#define I_PSLV REGL(0x200010) -#define I_PMST REGL(0x200014) -#define I_CSLV REGL(0x200018) -#define I_CMST REGL(0x20001c) -#define I_ISPR REGL(0x200020) -#define I_ISPC REGL(0x200024) -#define F_ISPR REGL(0x200038) -#define F_ISPC REGL(0x20003c) - -/********************************/ -/* LCD Controller Registers */ -/********************************/ - -#define LCDCON1 REGL(0x300000) -#define LCDCON2 REGL(0x300004) -#define LCDSADDR1 REGL(0x300008) -#define LCDSADDR2 REGL(0x30000c) -#define LCDSADDR3 REGL(0x300010) -#define REDLUT REGL(0x300014) -#define GREENLUT REGL(0x300018) -#define BLUELUT REGL(0x30001c) -#define DP1_2 REGL(0x300020) -#define DP4_7 REGL(0x300024) -#define DP3_5 REGL(0x300028) -#define DP2_3 REGL(0x30002c) -#define DP5_7 REGL(0x300030) -#define DP3_4 REGL(0x300034) -#define DP4_5 REGL(0x300038) -#define DP6_7 REGL(0x30003c) -#define LCDCON3 REGL(0x300040) -#define DITHMODE REGL(0x300044) - -/*********************/ -/* DMA Registers */ -/*********************/ - -#define ZDCON0 REGL(0x280000) -#define ZDISRC0 REGL(0x280004) -#define ZDIDES0 REGL(0x280008) -#define ZDICNT0 REGL(0x28000c) -#define ZDCSRC0 REGL(0x280010) -#define ZDCDES0 REGL(0x280014) -#define ZDCCNT0 REGL(0x280018) - -#define ZDCON1 REGL(0x280020) -#define ZDISRC1 REGL(0x280024) -#define ZDIDES1 REGL(0x280028) -#define ZDICNT1 REGL(0x28002c) -#define ZDCSRC1 REGL(0x280030) -#define ZDCDES1 REGL(0x280034) -#define ZDCCNT1 REGL(0x280038) - -#define BDCON0 REGL(0x380000) -#define BDISRC0 REGL(0x380004) -#define BDIDES0 REGL(0x380008) -#define BDICNT0 REGL(0x38000c) -#define BDCSRC0 REGL(0x380010) -#define BDCDES0 REGL(0x380014) -#define BDCCNT0 REGL(0x380018) - -#define BDCON1 REGL(0x380020) -#define BDISRC1 REGL(0x380024) -#define BDIDES1 REGL(0x380028) -#define BDICNT1 REGL(0x38002c) -#define BDCSRC1 REGL(0x380030) -#define BDCDES1 REGL(0x380034) -#define BDCCNT1 REGL(0x380038) - - -#define CLEAR_PEND_INT(n) I_ISPC = (1<<(n)) -#define INT_ENABLE(n) INTMSK &= ~(1<<(n)) -#define INT_DISABLE(n) INTMSK |= (1<<(n)) - -#define HARD_RESET_NOW() - -#endif /* __ASM_ARCH_HARDWARE_H */
Since commit 5dc5f36 removed B2 board support, there are no boards enabling s3c44b0_i2c.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Wolfgang Denk wd@denx.de Cc: Andrea Scian andrea.scian@dave-tech.it --- drivers/i2c/Makefile | 1 - drivers/i2c/s3c44b0_i2c.c | 299 --------------------------------------------- 2 files changed, 300 deletions(-) delete mode 100644 drivers/i2c/s3c44b0_i2c.c
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 37ccbd1..df3092e 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -21,7 +21,6 @@ COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o -COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o COBJS-$(CONFIG_SH_I2C) += sh_i2c.o diff --git a/drivers/i2c/s3c44b0_i2c.c b/drivers/i2c/s3c44b0_i2c.c deleted file mode 100644 index 8445e01..0000000 --- a/drivers/i2c/s3c44b0_i2c.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/hardware.h> - -/* - * Initialization, must be called once on start up, may be called - * repeatedly to change the speed and slave addresses. - */ -void i2c_init(int speed, int slaveaddr) -{ - /* - setting up I2C support - */ - unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF; - - save_F = PCONF; - save_PF = PUPF; - - rPCONF = ((save_F & ~(0xF))| 0xa); - rPUPF = (save_PF | 0x3); - PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/ - PUPF = rPUPF; /* Disable pull-up */ - - /* Configuring pin for WC pin of EEprom */ - rPCONA = PCONA; - rPCONA &= ~(1<<9); - PCONA = rPCONA; - - rPDATA = PDATA; - rPDATA &= ~(1<<9); - PDATA = rPDATA; - - /* - Enable ACK, IICCLK=MCLK/16, enable interrupt - 75MHz/16/(12+1) = 390625 Hz - */ - rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC); - IICCON = rIICCON; - - IICADD = slaveaddr; -} - -/* - * Probe the given I2C chip address. Returns 0 if a chip responded, - * not 0 on failure. - */ -int i2c_probe(uchar chip) -{ - /* - not implemented - */ - - printf("i2c_probe chip %d\n", (int) chip); - return -1; -} - -/* - * Read/Write interface: - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ - -#define S3C44B0X_rIIC_INTPEND (1<<4) -#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0) -#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5) -#define S3C44B0_IIC_TIMEOUT 100 - -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - - int k, j, temp; - u32 rIICSTAT; - - /* - send the device offset - */ - - rIICSTAT = 0xD0; - IICSTAT = rIICSTAT; - - IICDS = chip; /* this is a write operation... */ - - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - /* wait and check ACK */ - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - IICDS = addr; - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - /* - now we can start with the read operation... - */ - - IICDS = chip | 0x01; /* this is a read operation... */ - - rIICSTAT = 0x90; /*master recv*/ - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - for (j=0; j<len-1; j++) { - - /*clear pending bit to resume */ - - temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); - IICCON = temp; - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - - buffer[j] = IICDS; /*save readed data*/ - - } /*end for(j)*/ - - /* - reading the last data - unset ACK generation - */ - temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7)); - IICCON = temp; - - /* wait but NOT check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - buffer[j] = IICDS; /*save readed data*/ - - rIICSTAT = 0x90; /*master recv*/ - - /* Write operation Terminate sending STOP */ - IICSTAT = rIICSTAT; - /*Clear Int Pending Bit to RESUME*/ - temp = IICCON; - IICCON = temp & (~S3C44B0X_rIIC_INTPEND); - - IICCON = IICCON | (1<<7); /*restore ACK generation*/ - - return 0; -} - -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - int j, k; - u32 rIICSTAT, temp; - - - /* - send the device offset - */ - - rIICSTAT = 0xD0; - IICSTAT = rIICSTAT; - - IICDS = chip; /* this is a write operation... */ - - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - IICDS = addr; - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - /* - now we can start with the read write operation - */ - for (j=0; j<len; j++) { - - IICDS = buffer[j]; /*prerare data to write*/ - - /*clear pending bit to resume*/ - - temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); - IICCON = temp; - - /* wait but NOT check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - - udelay(2000); - } - - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - } /* end for(j) */ - - /* sending stop to terminate */ - rIICSTAT = 0xD0; /*master send*/ - IICSTAT = rIICSTAT; - /*Clear Int Pending Bit to RESUME*/ - temp = IICCON; - IICCON = temp & (~S3C44B0X_rIIC_INTPEND); - - return 0; -}
Hello Masahiro,
Am 19.08.2013 08:01, schrieb Masahiro Yamada:
Since commit 5dc5f36 removed B2 board support, there are no boards enabling s3c44b0_i2c.
Signed-off-by: Masahiro Yamadayamada.m@jp.panasonic.com Cc: Wolfgang Denkwd@denx.de Cc: Andrea Scianandrea.scian@dave-tech.it
drivers/i2c/Makefile | 1 - drivers/i2c/s3c44b0_i2c.c | 299 --------------------------------------------- 2 files changed, 300 deletions(-) delete mode 100644 drivers/i2c/s3c44b0_i2c.c
Thanks!
Acked-by: Heiko Schocher hs@denx.de
bye, Heiko
Since commit 5dc5f36 removed B2 board support, there are no boards enabling serial_s3c44b0.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Wolfgang Denk wd@denx.de Cc: Andrea Scian andrea.scian@dave-tech.it --- doc/driver-model/UDM-serial.txt | 16 ++- drivers/serial/Makefile | 1 - drivers/serial/serial.c | 2 - drivers/serial/serial_s3c44b0.c | 216 --------------------------------------- 4 files changed, 6 insertions(+), 229 deletions(-) delete mode 100644 drivers/serial/serial_s3c44b0.c
diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt index 1011c32..54f853e 100644 --- a/doc/driver-model/UDM-serial.txt +++ b/doc/driver-model/UDM-serial.txt @@ -148,32 +148,28 @@ III) Analysis of in-tree drivers -------------------- This driver, being quite ad-hoc might need some work to bring back to shape.
- 22) serial_s3c44b0.c - -------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 23) serial_s5p.c + 22) serial_s5p.c ---------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 24) serial_sa1100.c + 23) serial_sa1100.c ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 25) serial_sh.c + 24) serial_sh.c --------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 26) serial_xuartlite.c + 25) serial_xuartlite.c ---------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 27) usbtty.c + 26) usbtty.c ------------ This driver seems very complicated and entangled with USB framework. The conversion might be complicated here.
- 28) arch/powerpc/cpu/mpc512x/serial.c + 27) arch/powerpc/cpu/mpc512x/serial.c ------------------------------------- This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to proper place. diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 697f2bb..bcf7a1d 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -31,7 +31,6 @@ COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o COBJS-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o -COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 118fbc3..cd23ff8 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -156,7 +156,6 @@ serial_initfunc(lh7a40x_serial_initialize); serial_initfunc(max3100_serial_initialize); serial_initfunc(mxc_serial_initialize); serial_initfunc(pl01x_serial_initialize); -serial_initfunc(s3c44b0_serial_initialize); serial_initfunc(sa1100_serial_initialize); serial_initfunc(sh_serial_initialize); serial_initfunc(arm_dcc_initialize); @@ -249,7 +248,6 @@ void serial_initialize(void) max3100_serial_initialize(); mxc_serial_initialize(); pl01x_serial_initialize(); - s3c44b0_serial_initialize(); sa1100_serial_initialize(); sh_serial_initialize(); arm_dcc_initialize(); diff --git a/drivers/serial/serial_s3c44b0.c b/drivers/serial/serial_s3c44b0.c deleted file mode 100644 index 2a07498..0000000 --- a/drivers/serial/serial_s3c44b0.c +++ /dev/null @@ -1,216 +0,0 @@ -pyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002 - * ght 2002-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke azu@sysgo.de - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* flush serial input queue. returns 0 on success or negative error - * number otherwise - */ -static int serial_flush_input(void) -{ - volatile u32 tmp; - - /* keep on reading as long as the receiver is not empty */ - while(UTRSTAT0&0x01) { - tmp = REGB(URXH0); - } - - return 0; -} - - -/* flush output queue. returns 0 on success or negative error number - * otherwise - */ -static int serial_flush_output(void) -{ - /* wait until the transmitter is no longer busy */ - while(!(UTRSTAT0 & 0x02)) { - } - - return 0; -} - - -static void s3c44b0_serial_setbrg(void) -{ - u32 divisor = 0; - - /* get correct divisor */ - switch(gd->baudrate) { - - case 1200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 3124; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 3905; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 9600: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 390; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 487; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 19200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 194; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 243; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 38400: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 97; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 121; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - - case 57600: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 64; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 80; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - - case 115200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 32; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 40; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - } - - serial_flush_output(); - serial_flush_input(); - UFCON0 = 0x0; - ULCON0 = 0x03; - UCON0 = 0x05; - UBRDIV0 = divisor; - - UFCON1 = 0x0; - ULCON1 = 0x03; - UCON1 = 0x05; - UBRDIV1 = divisor; - - for(divisor=0; divisor<100; divisor++) { - /* NOP */ - } -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -static int s3c44b0_serial_init(void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -static void s3c44b0_serial_putc(const char c) -{ - /* wait for room in the transmit FIFO */ - while(!(UTRSTAT0 & 0x02)); - - UTXH0 = (unsigned char)c; - - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n') - serial_putc('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int s3c44b0_serial_tstc(void) -{ - return (UTRSTAT0 & 0x01); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int s3c44b0_serial_getc(void) -{ - int rv; - - for(;;) { - rv = s3c44b0_serial_tstc(); - - if(rv > 0) - return URXH0; - } -} - -static struct serial_device s3c44b0_serial_drv = { - .name = "s3c44b0_serial", - .start = s3c44b0_serial_init, - .stop = NULL, - .setbrg = s3c44b0_serial_setbrg, - .putc = s3c44b0_serial_putc, - .puts = default_serial_puts, - .getc = s3c44b0_serial_getc, - .tstc = s3c44b0_serial_tstc, -}; - -void s3c44b0_serial_initialize(void) -{ - serial_register(&s3c44b0_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &s3c44b0_serial_drv; -}
Since commit 5dc5f36 removed B2 board support, there are no boards enabling s3c44b0_rtc.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Wolfgang Denk wd@denx.de Cc: Andrea Scian andrea.scian@dave-tech.it --- doc/driver-model/UDM-rtc.txt | 15 +++----- drivers/rtc/Makefile | 1 - drivers/rtc/s3c44b0_rtc.c | 84 ------------------------------------------ 3 files changed, 5 insertions(+), 95 deletions(-) delete mode 100644 drivers/rtc/s3c44b0_rtc.c
diff --git a/doc/driver-model/UDM-rtc.txt b/doc/driver-model/UDM-rtc.txt index 5d9fb33..6aaeb86 100644 --- a/doc/driver-model/UDM-rtc.txt +++ b/doc/driver-model/UDM-rtc.txt @@ -228,31 +228,26 @@ III) Analysis of in-tree drivers The driver is standard rtc. Simple conversion is possible.
- 34) drivers/rtc/s3c44b0_rtc.c - ----------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 35) drivers/rtc/ds1337.c + 34) drivers/rtc/ds1337.c ------------------------ The driver is standard rtc. Simple conversion is possible.
- 36) drivers/rtc/isl1208.c + 35) drivers/rtc/isl1208.c ------------------------- The driver is standard rtc. Simple conversion is possible.
- 37) drivers/rtc/max6900.c + 36) drivers/rtc/max6900.c ------------------------- The driver is standard rtc. Simple conversion is possible.
- 38) drivers/rtc/mc146818.c + 37) drivers/rtc/mc146818.c -------------------------- The driver is standard rtc. Simple conversion is possible.
- 39) drivers/rtc/at91sam9_rtt.c + 38) drivers/rtc/at91sam9_rtt.c ------------------------------ The driver is standard rtc. Simple conversion is possible. diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index b477c23..dcc0632 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -53,7 +53,6 @@ COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o COBJS-$(CONFIG_RTC_RV3029) += rv3029.o COBJS-$(CONFIG_RTC_RX8025) += rx8025.o COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o -COBJS-$(CONFIG_RTC_S3C44B0) += s3c44b0_rtc.o COBJS-$(CONFIG_RTC_X1205) += x1205.o
COBJS := $(sort $(COBJS-y)) diff --git a/drivers/rtc/s3c44b0_rtc.c b/drivers/rtc/s3c44b0_rtc.c deleted file mode 100644 index de7898c..0000000 --- a/drivers/rtc/s3c44b0_rtc.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * S3C44B0 CPU specific code - */ - -#include <common.h> -#include <command.h> -#include <asm/hardware.h> -#include <rtc.h> - -int rtc_get (struct rtc_time* tm) -{ - RTCCON |= 1; - tm->tm_year = bcd2bin(BCDYEAR); - tm->tm_mon = bcd2bin(BCDMON); - tm->tm_wday = bcd2bin(BCDDATE); - tm->tm_mday = bcd2bin(BCDDAY); - tm->tm_hour = bcd2bin(BCDHOUR); - tm->tm_min = bcd2bin(BCDMIN); - tm->tm_sec = bcd2bin(BCDSEC); - - if (tm->tm_sec==0) { - /* we have to re-read the rtc data because of the "one second deviation" problem */ - /* see RTC datasheet for more info about it */ - tm->tm_year = bcd2bin(BCDYEAR); - tm->tm_mon = bcd2bin(BCDMON); - tm->tm_mday = bcd2bin(BCDDAY); - tm->tm_wday = bcd2bin(BCDDATE); - tm->tm_hour = bcd2bin(BCDHOUR); - tm->tm_min = bcd2bin(BCDMIN); - tm->tm_sec = bcd2bin(BCDSEC); - } - - RTCCON &= ~1; - - if(tm->tm_year >= 70) - tm->tm_year += 1900; - else - tm->tm_year += 2000; - - return 0; -} - -int rtc_set (struct rtc_time* tm) -{ - if(tm->tm_year < 2000) - tm->tm_year -= 1900; - else - tm->tm_year -= 2000; - - RTCCON |= 1; - BCDYEAR = bin2bcd(tm->tm_year); - BCDMON = bin2bcd(tm->tm_mon); - BCDDAY = bin2bcd(tm->tm_mday); - BCDDATE = bin2bcd(tm->tm_wday); - BCDHOUR = bin2bcd(tm->tm_hour); - BCDMIN = bin2bcd(tm->tm_min); - BCDSEC = bin2bcd(tm->tm_sec); - RTCCON &= 1; - - return 0; -} - -void rtc_reset (void) -{ - RTCCON |= 1; - BCDYEAR = 0; - BCDMON = 0; - BCDDAY = 0; - BCDDATE = 0; - BCDHOUR = 0; - BCDMIN = 0; - BCDSEC = 0; - RTCCON &= 1; -}
Hi Masahiro,
On Mon, 19 Aug 2013 15:01:21 +0900, Masahiro Yamada yamada.m@jp.panasonic.com wrote:
Commit 5dc5f36 removed the support for B2 board, which was the last S3C44B0 SoC board.
These series of patches remove s3c44b0-specific code and drivers:
- arch/arm/cpu/s3c44b0/*
- arch/arm/include/asm/arch-s3c44b0/*
- drivers/i2c/s3c44b0_i2c.c
- drivers/serial/serial_s3c44b0.c
- drivers/rtc/s3c44b0_rtc.c
Cc: Wolfgang Denk wd@denx.de Cc: Andrea Scian andrea.scian@dave-tech.it
Masahiro Yamada (4): ARM: s3c44b0: remove remainders of dead board drivers: s3c44b0_i2c: delete an unused driver drivers: serial_s3c44b0: delete an unused driver drivers: s3c44b0_rtc: delete an unused driver
README | 1 - arch/arm/cpu/s3c44b0/Makefile | 34 --- arch/arm/cpu/s3c44b0/cache.c | 74 ------- arch/arm/cpu/s3c44b0/config.mk | 18 -- arch/arm/cpu/s3c44b0/cpu.c | 58 ----- arch/arm/cpu/s3c44b0/start.S | 228 -------------------- arch/arm/cpu/s3c44b0/timer.c | 102 --------- arch/arm/include/asm/arch-s3c44b0/hardware.h | 281 ------------------------ doc/driver-model/UDM-rtc.txt | 15 +- doc/driver-model/UDM-serial.txt | 16 +- drivers/i2c/Makefile | 1 - drivers/i2c/s3c44b0_i2c.c | 299 -------------------------- drivers/rtc/Makefile | 1 - drivers/rtc/s3c44b0_rtc.c | 84 -------- drivers/serial/Makefile | 1 - drivers/serial/serial.c | 2 - drivers/serial/serial_s3c44b0.c | 216 ------------------- 17 files changed, 11 insertions(+), 1420 deletions(-) delete mode 100644 arch/arm/cpu/s3c44b0/Makefile delete mode 100644 arch/arm/cpu/s3c44b0/cache.c delete mode 100644 arch/arm/cpu/s3c44b0/config.mk delete mode 100644 arch/arm/cpu/s3c44b0/cpu.c delete mode 100644 arch/arm/cpu/s3c44b0/start.S delete mode 100644 arch/arm/cpu/s3c44b0/timer.c delete mode 100644 arch/arm/include/asm/arch-s3c44b0/hardware.h delete mode 100644 drivers/i2c/s3c44b0_i2c.c delete mode 100644 drivers/rtc/s3c44b0_rtc.c delete mode 100644 drivers/serial/serial_s3c44b0.c
Applied the whole series to u-boot-arm/master, thanks!
Amicalement,
participants (3)
-
Albert ARIBAUD -
Heiko Schocher -
Masahiro Yamada