[U-Boot] Problems booting without BDI
Hi all,
I made a port of u-boot for my board, with MPC8343.
The problem is that when i run u-boot with the BDI2000 (using "reset run" command), u-boot loads normally, but when i take off the BDI nothing appears on serial.
BDI is setting the reset configuration word, and is the same word found in u-boot image. I commented the line wich BDI sets the reset word, and tried to read it from the BDI, its seems ok _BUT_, nothing appears on serial.
Any ideas about what could be happening?
Here is the reset configuration word that BDI and U-Boot are using:
BDI: ====
RCW 0xA0602000 0x04030000
U-Boot: =======
00000000 - 04 04 04 04 04 04 04 04 03 03 03 03 03 03 03 03 ................ 00000010 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00000020 - a0 a0 a0 a0 a0 a0 a0 a0 60 60 60 60 60 60 60 60 ................ 00000030 - 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 ................ 00000040 - 27 05 19 56 42 6f 6f 74 6c 6f 61 64 65 72 20 34 '..VBootloader 4 00000050 - 20 28 53 65 70 20 31 35 20 32 30 30 38 20 2d 20 (Nov 20 2008 - 00000060 - 31 37 3a 32 39 3a 33 38 29 20 4d 50 43 38 33 58 10:29:38) MPC83X 00000070 - 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 X...............
Thanks in advance,
-- Alemao
Hi Alemao,
I made a port of u-boot for my board, with MPC8343.
The problem is that when i run u-boot with the BDI2000 (using "reset run" command), u-boot loads normally, but when i take off the BDI nothing appears on serial.
BDI is setting the reset configuration word, and is the same word found in u-boot image. I commented the line wich BDI sets the reset word, and tried to read it from the BDI, its seems ok _BUT_, nothing appears on serial.
Any ideas about what could be happening?
Perhaps your processor is not being driven with the correct pin strapping values to cause it to read configuration reset words from Flash.
Check the schematic connections for the configuration reset words source pins (they're LGPL pins that do dual duty during boot).
The assignments for the 8349 are:
CFG_RS[0:2] = LGPL[0, 1, 3] CFG_CLKIN_DIV = LGPL[5]
Look in the reference manual for your processor. Now that you know what you are looking for, it should be easy to locate.
The CFG_xx pins need to be driven at reset, they're captured by the processing on the rising edge of PRST#. You may find that the design has a tri-state buffer being controlled by the HRST# pin; when HRST# is low, the signals are driven, when high, they're disabled and used as GPIO/LBC signals.
These comments are based on my experience with the 8349, but the 8343 should be similar.
Cheers, Dave
David Hawkins wrote:
Hi Alemao,
I made a port of u-boot for my board, with MPC8343.
The problem is that when i run u-boot with the BDI2000 (using "reset run" command), u-boot loads normally, but when i take off the BDI nothing appears on serial.
BDI is setting the reset configuration word, and is the same word found in u-boot image. I commented the line wich BDI sets the reset word, and tried to read it from the BDI, its seems ok _BUT_, nothing appears on serial.
Any ideas about what could be happening?
Perhaps your processor is not being driven with the correct pin strapping values to cause it to read configuration reset words from Flash.
Check the schematic connections for the configuration reset words source pins (they're LGPL pins that do dual duty during boot).
The assignments for the 8349 are:
CFG_RS[0:2] = LGPL[0, 1, 3] CFG_CLKIN_DIV = LGPL[5]
Look in the reference manual for your processor. Now that you know what you are looking for, it should be easy to locate.
The CFG_xx pins need to be driven at reset, they're captured by the processing on the rising edge of PRST#. You may find that the design has a tri-state buffer being controlled by the HRST# pin; when HRST# is low, the signals are driven, when high, they're disabled and used as GPIO/LBC signals.
These comments are based on my experience with the 8349, but the 8343 should be similar.
Cheers, Dave
To somewhat re-phrase what Dave mentioned, one common issue is that at boot time, the four least-significant local bus address bits are driven by different signals than the standard local bus address bits (sorry, don't have the documentation here so don't know the exact names). Without this you can't red the RCW words from NOR flash. Compare your schematic to the one for the MPC8349EMDS to make sure you got this right.
regards, Ben
Hi Alemao,
Ben's comment is in addition to my comment:
The assignments for the 8349 are:
CFG_RS[0:2] = LGPL[0, 1, 3] CFG_CLKIN_DIV = LGPL[5]
These need to be setup to tell the processor to load from local bus flash, and then ...
To somewhat re-phrase what Dave mentioned, one common issue is that at boot time, the four least-significant local bus address bits are driven by different signals than the standard local bus address bits (sorry, don't have the documentation here so don't know the exact names). Without this you can't red the RCW words from NOR flash. Compare your schematic to the one for the MPC8349EMDS to make sure you got this right.
During the boot sequence from local bus flash, the LA[27:31] lines carry the boot addresses, and the lower-addresses cycle without pulsing the LALE (local bus address latch enable) signal, so if your schematic drives the flash address lines with *latched* versions of LA[27:31] then you're also in trouble.
Hopefully thats not your problem though ...
Cheers, Dave
participants (3)
-
Alemao -
Ben Warren -
David Hawkins