[U-Boot-Users] Software watchdog on mpc8247
Hello,
I have a custom board with mpc8247 processor. I'd like to use it's internal watchdog capability in u-boot (and linux). I've tried to use the folliwing defines in my board config file (include/configs/my_board.h):
#define CONFIG_WATCHDOG 1 #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) #else #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ SYPCR_SWRI|SYPCR_SWP) #endif /* CONFIG_WATCHDOG */
but the board does not boot when the watchdog is enabled. I use u-boot 1.1.3 release.
-- Sincerely yours, Mike Rapoport
In message f870da180508242246126ce433@mail.gmail.com you wrote:
but the board does not boot when the watchdog is enabled. I use u-boot 1.1.3 release.
How far does it get, and what exactly happens? "Does not boot" is not exactly a precise description...
Best regards,
Wolfgang Denk
On 8/25/05, Wolfgang Denk wd@denx.de wrote:
How far does it get, and what exactly happens? "Does not boot" is not exactly a precise description...
Best regards,
Wolfgang Denk
Unfortunately I don't have BDI so the only "debug" available is on-board led and scope. Using this I determined that u-boot starts initialization sequence in board_init_f (lib_ppc/board.c) and then restarts.
Mike Rapoport wrote:
Hello,
I have a custom board with mpc8247 processor. I'd like to use it's internal watchdog capability in u-boot (and linux). I've tried to use the folliwing defines in my board config file (include/configs/my_board.h):
#define CONFIG_WATCHDOG 1 #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) #else #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ SYPCR_SWRI|SYPCR_SWP) #endif /* CONFIG_WATCHDOG */
but the board does not boot when the watchdog is enabled. I use u-boot 1.1.3 release.
-- Sincerely yours, Mike Rapoport
What did you set the SYPCR to (actual values, preferably from a disassembly/dump)? What is your bus clock? What do you figure your timeout to be? Do you write to the SYPCR only once to set up the WDT (only the first write to the SYPCR "works").
gvb
On 8/25/05, Jerry Van Baren gerald.vanbaren@smiths-aerospace.com wrote:
What did you set the SYPCR to (actual values, preferably from a disassembly/dump)?
Here's the output of "objdump -dS u-boot" : /* Initialise the SYPCR early, and reset the watchdog (if req) */ /*--------------------------------------------------------------*/
lis r3, (CFG_IMMR+IM_REGBASE)@h fff03198: 3c 60 f0 01 lis r3,-4095 #if !defined(CONFIG_COGENT) lis r4, CFG_SYPCR@h fff0319c: 3c 80 ff ff lis r4,-1 ori r4, r4, CFG_SYPCR@l fff031a0: 60 84 ff c3 ori r4,r4,65479 stw r4, IM_SYPCR@l(r3) fff031a4: 90 83 00 04 stw r4,4(r3) #endif /* !CONFIG_COGENT */ #if defined(CONFIG_WATCHDOG) li r4, 21868 /* = 0x556c */ sth r4, IM_SWSR@l(r3) li r4, -21959 /* = 0xaa39 */ sth r4, IM_SWSR@l(r3)
Actual SYPCR setting is 0xFFFFFFC7 I verified that this code is executed.
I've tried to add WATCHDOG_RESET() call in board_init_f just before the initialization sequence was run, but it didn't change anything.
What is your bus clock?
66MHz
What do you figure your timeout to be?
2 sec
Do you write to the SYPCR only once to set up the WDT (only the first write to the SYPCR "works").
Yes
Mike Rapoport wrote:
On 8/25/05, Jerry Van Baren gerald.vanbaren@smiths-aerospace.com wrote:
What did you set the SYPCR to (actual values, preferably from a disassembly/dump)?
Here's the output of "objdump -dS u-boot" : /* Initialise the SYPCR early, and reset the watchdog (if req) */ /*--------------------------------------------------------------*/
lis r3, (CFG_IMMR+IM_REGBASE)@hfff03198: 3c 60 f0 01 lis r3,-4095 #if !defined(CONFIG_COGENT) lis r4, CFG_SYPCR@h fff0319c: 3c 80 ff ff lis r4,-1 ori r4, r4, CFG_SYPCR@l fff031a0: 60 84 ff c3 ori r4,r4,65479 stw r4, IM_SYPCR@l(r3) fff031a4: 90 83 00 04 stw r4,4(r3) #endif /* !CONFIG_COGENT */ #if defined(CONFIG_WATCHDOG) li r4, 21868 /* = 0x556c */ sth r4, IM_SWSR@l(r3) li r4, -21959 /* = 0xaa39 */ sth r4, IM_SWSR@l(r3)
Actual SYPCR setting is 0xFFFFFFC7 I verified that this code is executed.
I've tried to add WATCHDOG_RESET() call in board_init_f just before the initialization sequence was run, but it didn't change anything.
What is your bus clock?
66MHz
What do you figure your timeout to be?
2 sec
Do you write to the SYPCR only once to set up the WDT (only the first write to the SYPCR "works").
Yes
Pointing out the obvious... looking at the disassembly, it isn't enabling the watchdog (SWE). I'm guessing that you disassembled code where you had the watchdog disabled?
I see you have PBME and LBME enabled (I'm looking at an 8260 manual, assuming the 8247 is the same - feel free to correct me :-). Do you have a 60x bus and a local bus? Is it possible you are having an inadvertant bus error? This wouldn't explain why it only happens when you enable the WDT, however. Puzzling.
gvb
On 8/25/05, Jerry Van Baren gerald.vanbaren@smiths-aerospace.com wrote:
Pointing out the obvious... looking at the disassembly, it isn't enabling the watchdog (SWE). I'm guessing that you disassembled code where you had the watchdog disabled?
The instruction fff031a0: 60 84 ff c3 ori r4,r4,65479 actually enables watchdog (65479 dec = ffc7 hex) and SWE is bit 29 of SYPCR.
I see you have PBME and LBME enabled (I'm looking at an 8260 manual, assuming the 8247 is the same - feel free to correct me :-). Do you have a 60x bus and a local bus? Is it possible you are having an inadvertant bus error? This wouldn't explain why it only happens when you enable the WDT, however. Puzzling.
The 8247 does not have local bus, only 60x, but setting/clearing LBME does not affect the operation. If I don't enable the watchdog the system works fine.
Another thing I've noticed, most or even all 8260 based systems have #undef CONFIG_WATCHDOG in their config
Mike Rapoport wrote:
On 8/25/05, Jerry Van Baren gerald.vanbaren@smiths-aerospace.com wrote:
Pointing out the obvious... looking at the disassembly, it isn't enabling the watchdog (SWE). I'm guessing that you disassembled code where you had the watchdog disabled?
The instruction fff031a0: 60 84 ff c3 ori r4,r4,65479 actually enables watchdog (65479 dec = ffc7 hex) and SWE is bit 29 of SYPCR.
Well... yes and no. 65479 == 0xFFC7 as you point out, however the instruction has 0xFFC3 in it. That's pretty odd. Compiler problem?
I see you have PBME and LBME enabled (I'm looking at an 8260 manual, assuming the 8247 is the same - feel free to correct me :-). Do you have a 60x bus and a local bus? Is it possible you are having an inadvertant bus error? This wouldn't explain why it only happens when you enable the WDT, however. Puzzling.
The 8247 does not have local bus, only 60x, but setting/clearing LBME does not affect the operation. If I don't enable the watchdog the system works fine.
Another thing I've noticed, most or even all 8260 based systems have #undef CONFIG_WATCHDOG in their config
Well, they are a real pain, generally more than they are worth. My co-worker says we had it working on our 8260 board at one point, but Things Changed and it stopped working (it was a never-ending battle to sprinkle enough kick-the-dogs in the start up code) and so it ended up turned off. He said it worked fine once we got through initialization and the was kernel running...
gvb
participants (3)
-
Jerry Van Baren -
Mike Rapoport -
Wolfgang Denk