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From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] Sent: Friday, January 04, 2019 8:37 AM To: u-boot@lists.denx.de Cc: Anup Patel; Lukas Auer; Rick Jian-Zhi Chen(陳建志); Bin Meng; Greentime Hu Subject: [PATCH v2 2/7] riscv: move the AX25-specific implementation of flush_dcache_all

The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/.

This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c.

Signed-off-by: Lukas Auer lukas.auer@aisec.fraunhofer.de

Changes in v2:

• Replace patch "riscv: remove invalid dcache flush implementation" with new

patch "riscv: move the AX25-specific implementation of flush_dcache_all"

arch/riscv/cpu/ax25/cache.c | 22 ++++++++++++++++++++++ arch/riscv/lib/cache.c | 10 ++++------ 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 8d6ae170b8..228fc55f56 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -6,6 +6,28 @@

#include <common.h>

+void flush_dcache_all(void) +{

• /*
  

•  * Andes' AX25 does not have a coherence agent. U-Boot must use data
  

•  * cache flush and invalidate functions to keep data in the system
  

•  * coherent.
  

•  * The implementation of the fence instruction in the AX25 flushes the
  

•  * data cache and is used for this purpose.
  

•  */
  

• asm volatile ("fence" ::: "memory");
  

+}

+void flush_dcache_range(unsigned long start, unsigned long end) {

• flush_dcache_all();
  

+}

+void invalidate_dcache_range(unsigned long start, unsigned long end) {

• flush_dcache_all();
  

+}

void icache_enable(void) { #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index ae5c60716f..78b19da2c5 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -11,13 +11,12 @@ void invalidate_icache_all(void) asm volatile ("fence.i" ::: "memory"); }

-void flush_dcache_all(void) +__weak void flush_dcache_all(void) {

• asm volatile ("fence" :::"memory");
  

} -void flush_dcache_range(unsigned long start, unsigned long end)

+__weak void flush_dcache_range(unsigned long start, unsigned long end) {

• flush_dcache_all();
  

}

void invalidate_icache_range(unsigned long start, unsigned long end) @@ -29,9 +28,8 @@ void invalidate_icache_range(unsigned long start, unsigned long end) invalidate_icache_all(); }

-void invalidate_dcache_range(unsigned long start, unsigned long end) +__weak void invalidate_dcache_range(unsigned long start, unsigned long +end) {

• flush_dcache_all();
  

}

void cache_flush(void)

Reviewed-by: Rick Chen rick@andestech.com