[U-Boot] [PATCH 1/2] cmd_i2c: rename EDO, DDR and SDRAM to avoid conflict with at91 memory setup
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com Cc: Timo Tuunainen timo.tuunainen@sysart.fi --- common/cmd_i2c.c | 58 +++++++++++++++++++++++++++--------------------------- 1 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 448f2fe..a662b53 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -712,7 +712,7 @@ static void decode_bits (u_char const b, char const *str[], int const do_once) */ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - enum { unknown, EDO, SDRAM, DDR2 } type; + enum { unknown, _EDO, _SDRAM, _DDR2 } type;
u_char chip; u_char data[128]; @@ -793,15 +793,15 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) puts ("Memory type "); switch (data[2]) { case 2: - type = EDO; + type = _EDO; puts ("EDO\n"); break; case 4: - type = SDRAM; + type = _SDRAM; puts ("SDRAM\n"); break; case 8: - type = DDR2; + type = _DDR2; puts ("DDR2\n"); break; default: @@ -823,7 +823,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
switch (type) { - case DDR2: + case _DDR2: printf ("Number of ranks %d\n", (data[5] & 0x07) + 1); break; @@ -833,7 +833,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("Module data width %d bits\n", data[6]); break; default: @@ -854,7 +854,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("SDRAM cycle time "); print_ddr2_tcyc (data[9]); break; @@ -865,7 +865,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("SDRAM access time 0.%d%d ns\n", (data[10] >> 4) & 0x0F, data[10] & 0x0F); break; @@ -899,7 +899,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("SDRAM width (primary) %d\n", data[13]); break; default: @@ -912,7 +912,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: if (data[14] != 0) printf ("EDC width %d\n", data[14]); break; @@ -929,7 +929,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) break; }
- if (DDR2 != type) { + if (_DDR2 != type) { printf ("Min clock delay, back-to-back random column addresses " "%d\n", data[15]); } @@ -944,7 +944,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf ("Number of banks %d\n", data[17]);
switch (type) { - case DDR2: + case _DDR2: puts ("CAS latency(s) "); decode_bits (data[18], decode_CAS_DDR2, 0); putc ('\n'); @@ -956,20 +956,20 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) break; }
- if (DDR2 != type) { + if (_DDR2 != type) { puts ("CS latency(s) "); decode_bits (data[19], decode_CS_WE_default, 0); putc ('\n'); }
- if (DDR2 != type) { + if (_DDR2 != type) { puts ("WE latency(s) "); decode_bits (data[20], decode_CS_WE_default, 0); putc ('\n'); }
switch (type) { - case DDR2: + case _DDR2: puts ("Module attributes:\n"); if (data[21] & 0x80) puts (" TBD (bit 7)\n"); @@ -995,7 +995,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: decode_bits (data[22], decode_byte22_DDR2, 0); break; default: @@ -1014,7 +1014,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("SDRAM cycle time (2nd highest CAS latency) "); print_ddr2_tcyc (data[23]); break; @@ -1025,7 +1025,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("SDRAM access from clock (2nd highest CAS latency) 0." "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); break; @@ -1036,7 +1036,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("SDRAM cycle time (3rd highest CAS latency) "); print_ddr2_tcyc (data[25]); break; @@ -1047,7 +1047,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("SDRAM access from clock (3rd highest CAS latency) 0." "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); break; @@ -1058,7 +1058,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("Minimum row precharge %d.%02d ns\n", (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03)); break; @@ -1068,7 +1068,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("Row active to row active min %d.%02d ns\n", (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03)); break; @@ -1078,7 +1078,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("RAS to CAS delay min %d.%02d ns\n", (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03)); break; @@ -1090,7 +1090,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf ("Minimum RAS pulse width %d ns\n", data[30]);
switch (type) { - case DDR2: + case _DDR2: puts ("Density of each row "); decode_bits (data[31], decode_row_density_DDR2, 1); putc ('\n'); @@ -1103,7 +1103,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: puts ("Command and Address setup "); if (data[32] >= 0xA0) { printf ("1.%d%d ns\n", @@ -1121,7 +1121,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: puts ("Command and Address hold "); if (data[33] >= 0xA0) { printf ("1.%d%d ns\n", @@ -1139,7 +1139,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("Data signal input setup 0.%d%d ns\n", (data[34] >> 4) & 0x0F, data[34] & 0x0F); break; @@ -1151,7 +1151,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case _DDR2: printf ("Data signal input hold 0.%d%d ns\n", (data[35] >> 4) & 0x0F, data[35] & 0x0F); break; @@ -1178,7 +1178,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf ("%02X ", data[j]); putc ('\n');
- if (DDR2 != type) { + if (_DDR2 != type) { printf ("Speed rating PC%d\n", data[126] == 0x66 ? 66 : data[126]); }
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com Cc: Timo Tuunainen timo.tuunainen@sysart.fi --- could you test this patch please?
this patch will normaly fix yhe m501sk support against mainline
Best Regards, J. board/m501sk/Makefile | 2 - board/m501sk/memsetup.S | 200 ---------------------------------------------- include/configs/m501sk.h | 33 ++++++++ 3 files changed, 33 insertions(+), 202 deletions(-) delete mode 100644 board/m501sk/memsetup.S
diff --git a/board/m501sk/Makefile b/board/m501sk/Makefile index c562c60..aec3d1c 100644 --- a/board/m501sk/Makefile +++ b/board/m501sk/Makefile @@ -27,8 +27,6 @@ LIB = $(obj)lib$(BOARD).a
COBJS := m501sk.o eeprom.o
-SOBJS := memsetup.o - SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S deleted file mode 100644 index 6aea723..0000000 --- a/board/m501sk/memsetup.S +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the at91rm9200dk board by - * (C) Copyright 2004 - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> - -#ifdef CONFIG_BOOTBINFUNC -/* - * some parameters for the board - * - * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in - * turn is based on the boot.bin code from ATMEL - * - */ - -/* flash */ -#define MC_PUIA 0xFFFFFF10 -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP 0xFFFFFF50 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER 0xFFFFFF54 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR 0xFFFFFF04 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR 0xFFFFFF08 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR 0xFFFFFF64 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0 0xFFFFFF70 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define PLLAR 0xFFFFFC28 -#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define PLLBR 0xFFFFFC2C -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define MCKR 0xFFFFFC30 -/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ -#define MCKR_VAL 0x00000202 - -/* sdram */ -#define PIOC_ASR 0xFFFFF870 -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ -#define PIOC_BSR 0xFFFFF874 -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR 0xFFFFF804 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA 0xFFFFFF60 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR 0xFFFFFF98 -#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR 0xFFFFFF90 -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR 0xFFFFFF94 -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl lowlevelinit -lowlevelinit: - /* memory control configuration */ - /* this isn't very elegant, but what the heck */ - ldr r0, =SMRDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - add r2, r0, #80 -0: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 0b - /* delay - this is all done by guess */ - ldr r0, =0x00010000 -1: - subs r0, r0, #1 - bhi 1b - ldr r0, =SMRDATA1 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - add r2, r0, #176 -2: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 2b - - /* everything is fine now */ - mov pc, lr - - .ltorg - -SMRDATA: - .word MC_PUIA - .word MC_PUIA_VAL - .word MC_PUP - .word MC_PUP_VAL - .word MC_PUER - .word MC_PUER_VAL - .word MC_ASR - .word MC_ASR_VAL - .word MC_AASR - .word MC_AASR_VAL - .word EBI_CFGR - .word EBI_CFGR_VAL - .word SMC_CSR0 - .word SMC_CSR0_VAL - .word PLLAR - .word PLLAR_VAL - .word PLLBR - .word PLLBR_VAL - .word MCKR - .word MCKR_VAL - /* SMRDATA is 80 bytes long */ - /* here there's a delay of 100 */ -SMRDATA1: - .word PIOC_ASR - .word PIOC_ASR_VAL - .word PIOC_BSR - .word PIOC_BSR_VAL - .word PIOC_PDR - .word PIOC_PDR_VAL - .word EBI_CSA - .word EBI_CSA_VAL - .word SDRC_CR - .word SDRC_CR_VAL - .word SDRC_MR - .word SDRC_MR_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRC_MR - .word SDRC_MR_VAL1 - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRC_MR - .word SDRC_MR_VAL2 - .word SDRAM1 - .word SDRAM_VAL - .word SDRC_TR - .word SDRC_TR_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRC_MR - .word SDRC_MR_VAL3 - .word SDRAM - .word SDRAM_VAL - /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_BOOTBINFUNC */ diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h index f09214d..6cdc58a 100644 --- a/include/configs/m501sk.h +++ b/include/configs/m501sk.h @@ -41,6 +41,39 @@ #define CONFIG_INITRD_TAG 1
#define CONFIG_MENUPROMPT "." +/* + * LowLevel Init + */ +#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define MC_PUIA_VAL 0x00000000 +#define MC_PUP_VAL 0x00000000 +#define MC_PUER_VAL 0x00000000 +#define MC_ASR_VAL 0x00000000 +#define MC_AASR_VAL 0x00000000 +#define EBI_CFGR_VAL 0x00000000 +#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ +#define MCKR_VAL 0x00000202 + +/* sdram */ +#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define PIOC_BSR_VAL 0x00000000 +#define PIOC_PDR_VAL 0xFFFF0000 +#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ +#define SDRAM 0x20000000 /* address of the SDRAM */ +#define SDRAM1 0x20000080 /* address of the SDRAM */ +#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define SDRC_MR_VAL1 0x00000004 /* refresh */ +#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
/* * Size of malloc() pool
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 1229469026-7344-1-git-send-email-plagnioj@jcrosoft.com you wrote:
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com Cc: Timo Tuunainen timo.tuunainen@sysart.fi
common/cmd_i2c.c | 58 +++++++++++++++++++++++++++--------------------------- 1 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 448f2fe..a662b53 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -712,7 +712,7 @@ static void decode_bits (u_char const b, char const *str[], int const do_once) */ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) {
- enum { unknown, EDO, SDRAM, DDR2 } type;
- enum { unknown, _EDO, _SDRAM, _DDR2 } type;
Please do not use leading underscores in regular variable names. They are reserved in C.
Best regards,
Wolfgang Denk
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com --- common/cmd_i2c.c | 58 ++++++++++++++++++++++++++--------------------------- 1 files changed, 28 insertions(+), 30 deletions(-)
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 448f2fe..9f7a1ea 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -712,7 +712,7 @@ static void decode_bits (u_char const b, char const *str[], int const do_once) */ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - enum { unknown, EDO, SDRAM, DDR2 } type; + enum { unknown, edo, sdram, ddr2 } type;
u_char chip; u_char data[128]; @@ -793,15 +793,15 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) puts ("Memory type "); switch (data[2]) { case 2: - type = EDO; + type = edo; puts ("EDO\n"); break; case 4: - type = SDRAM; + type = sdram; puts ("SDRAM\n"); break; case 8: - type = DDR2; + type = ddr2; puts ("DDR2\n"); break; default: @@ -823,7 +823,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
switch (type) { - case DDR2: + case ddr2: printf ("Number of ranks %d\n", (data[5] & 0x07) + 1); break; @@ -833,7 +833,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("Module data width %d bits\n", data[6]); break; default: @@ -854,7 +854,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("SDRAM cycle time "); print_ddr2_tcyc (data[9]); break; @@ -865,7 +865,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("SDRAM access time 0.%d%d ns\n", (data[10] >> 4) & 0x0F, data[10] & 0x0F); break; @@ -899,7 +899,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("SDRAM width (primary) %d\n", data[13]); break; default: @@ -912,7 +912,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: if (data[14] != 0) printf ("EDC width %d\n", data[14]); break; @@ -929,7 +929,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) break; }
- if (DDR2 != type) { + if (type != ddr2) { printf ("Min clock delay, back-to-back random column addresses " "%d\n", data[15]); } @@ -944,7 +944,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf ("Number of banks %d\n", data[17]);
switch (type) { - case DDR2: + case ddr2: puts ("CAS latency(s) "); decode_bits (data[18], decode_CAS_DDR2, 0); putc ('\n'); @@ -956,20 +956,18 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) break; }
- if (DDR2 != type) { + if (type != ddr2) { puts ("CS latency(s) "); decode_bits (data[19], decode_CS_WE_default, 0); putc ('\n'); - }
- if (DDR2 != type) { puts ("WE latency(s) "); decode_bits (data[20], decode_CS_WE_default, 0); putc ('\n'); }
switch (type) { - case DDR2: + case ddr2: puts ("Module attributes:\n"); if (data[21] & 0x80) puts (" TBD (bit 7)\n"); @@ -995,7 +993,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: decode_bits (data[22], decode_byte22_DDR2, 0); break; default: @@ -1014,7 +1012,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("SDRAM cycle time (2nd highest CAS latency) "); print_ddr2_tcyc (data[23]); break; @@ -1025,7 +1023,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("SDRAM access from clock (2nd highest CAS latency) 0." "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); break; @@ -1036,7 +1034,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("SDRAM cycle time (3rd highest CAS latency) "); print_ddr2_tcyc (data[25]); break; @@ -1047,7 +1045,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("SDRAM access from clock (3rd highest CAS latency) 0." "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); break; @@ -1058,7 +1056,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("Minimum row precharge %d.%02d ns\n", (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03)); break; @@ -1068,7 +1066,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("Row active to row active min %d.%02d ns\n", (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03)); break; @@ -1078,7 +1076,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("RAS to CAS delay min %d.%02d ns\n", (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03)); break; @@ -1090,7 +1088,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf ("Minimum RAS pulse width %d ns\n", data[30]);
switch (type) { - case DDR2: + case ddr2: puts ("Density of each row "); decode_bits (data[31], decode_row_density_DDR2, 1); putc ('\n'); @@ -1103,7 +1101,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: puts ("Command and Address setup "); if (data[32] >= 0xA0) { printf ("1.%d%d ns\n", @@ -1121,7 +1119,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: puts ("Command and Address hold "); if (data[33] >= 0xA0) { printf ("1.%d%d ns\n", @@ -1139,7 +1137,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("Data signal input setup 0.%d%d ns\n", (data[34] >> 4) & 0x0F, data[34] & 0x0F); break; @@ -1151,7 +1149,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }
switch (type) { - case DDR2: + case ddr2: printf ("Data signal input hold 0.%d%d ns\n", (data[35] >> 4) & 0x0F, data[35] & 0x0F); break; @@ -1178,7 +1176,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf ("%02X ", data[j]); putc ('\n');
- if (DDR2 != type) { + if (type != ddr2) { printf ("Speed rating PC%d\n", data[126] == 0x66 ? 66 : data[126]); }
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 1229513662-2128-1-git-send-email-plagnioj@jcrosoft.com you wrote:
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com
common/cmd_i2c.c | 58 ++++++++++++++++++++++++++--------------------------- 1 files changed, 28 insertions(+), 30 deletions(-)
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 448f2fe..9f7a1ea 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -712,7 +712,7 @@ static void decode_bits (u_char const b, char const *str[], int const do_once) */ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) {
- enum { unknown, EDO, SDRAM, DDR2 } type;
- enum { unknown, edo, sdram, ddr2 } type;
Sorry again, but lower case enum labels violate the coding style either:
Chapter 12: Macros, Enums and RTL
Names of macros defining constants and labels in enums are capitalized.
Best regards,
Wolfgang Denk
On 12:56 Wed 17 Dec , Wolfgang Denk wrote:
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 1229513662-2128-1-git-send-email-plagnioj@jcrosoft.com you wrote:
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com
common/cmd_i2c.c | 58 ++++++++++++++++++++++++++--------------------------- 1 files changed, 28 insertions(+), 30 deletions(-)
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 448f2fe..9f7a1ea 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -712,7 +712,7 @@ static void decode_bits (u_char const b, char const *str[], int const do_once) */ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) {
- enum { unknown, EDO, SDRAM, DDR2 } type;
- enum { unknown, edo, sdram, ddr2 } type;
Sorry again, but lower case enum labels violate the coding style either:
Chapter 12: Macros, Enums and RTL
Names of macros defining constants and labels in enums are capitalized.
so could you tell what do you wish to have (an example) __DDR2?
Best Regards, J.
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 20081217115717.GD26222@game.jcrosoft.org you wrote:
- enum { unknown, EDO, SDRAM, DDR2 } type;
- enum { unknown, edo, sdram, ddr2 } type;
Sorry again, but lower case enum labels violate the coding style either:
Chapter 12: Macros, Enums and RTL
Names of macros defining constants and labels in enums are capitalized.
so could you tell what do you wish to have (an example) __DDR2?
I don't really care about the exact variable name as long as it's standard conforming and does not violate the coding style.
__DDR2 would be obviuosly a very bad choice. Prefixing names with "_" or "__" is used only to reserve name spaces - which is not waht you're doing here.
Actually I don't understand at all why you want to change this file. Using "DDR2" as a local variable name is perfectly valid.
If there are problems because some stupid header file with global scope #defines a "DDR2" name that include file needs fixing, but not the C file here.
Best regards,
Wolfgang Denk
On 15:15 Wed 17 Dec , Wolfgang Denk wrote:
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 20081217115717.GD26222@game.jcrosoft.org you wrote:
- enum { unknown, EDO, SDRAM, DDR2 } type;
- enum { unknown, edo, sdram, ddr2 } type;
Sorry again, but lower case enum labels violate the coding style either:
Chapter 12: Macros, Enums and RTL
Names of macros defining constants and labels in enums are capitalized.
so could you tell what do you wish to have (an example) __DDR2?
I don't really care about the exact variable name as long as it's standard conforming and does not violate the coding style.
__DDR2 would be obviuosly a very bad choice. Prefixing names with "_" or "__" is used only to reserve name spaces - which is not waht you're doing here.
Actually I don't understand at all why you want to change this file. Using "DDR2" as a local variable name is perfectly valid.
If there are problems because some stupid header file with global scope #defines a "DDR2" name that include file needs fixing, but not the C file here.
Yes that is the problem SDRAM is already use for other configuration
Maybe I need to rename the at91 to CONFIG_SYS_SDRAM
Best Regards, J.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com Cc: Sami Nurmenniemi sanurmen@sysart.fi --- board/m501sk/memsetup.S | 134 ++++++++++++++++---------------- cpu/arm920t/at91rm9200/lowlevel_init.S | 88 +++++++++++----------- include/configs/at91rm9200dk.h | 46 ++++++------ include/configs/cmc_pu2.h | 46 ++++++------ include/configs/csb637.h | 46 ++++++------ include/configs/mp2usb.h | 46 ++++++------ 6 files changed, 203 insertions(+), 203 deletions(-)
diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S index 6aea723..1a3ca4b 100644 --- a/board/m501sk/memsetup.S +++ b/board/m501sk/memsetup.S @@ -41,50 +41,50 @@
/* flash */ #define MC_PUIA 0xFFFFFF10 -#define MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 #define MC_PUP 0xFFFFFF50 -#define MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 #define MC_PUER 0xFFFFFF54 -#define MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 #define MC_ASR 0xFFFFFF04 -#define MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 #define MC_AASR 0xFFFFFF08 -#define MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 #define EBI_CFGR 0xFFFFFF64 -#define EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 #define SMC_CSR0 0xFFFFFF70 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */ #define PLLAR 0xFFFFFC28 -#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ #define PLLBR 0xFFFFFC2C -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ #define MCKR 0xFFFFFC30 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ -#define MCKR_VAL 0x00000202 +#define CONFIG_SYS_MCKR_VAL 0x00000202
/* sdram */ #define PIOC_ASR 0xFFFFF870 -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ #define PIOC_BSR 0xFFFFF874 -#define PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 #define PIOC_PDR 0xFFFFF804 -#define PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 #define EBI_CSA 0xFFFFFF60 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ #define SDRC_CR 0xFFFFFF98 -#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ #define SDRC_MR 0xFFFFFF90 -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define SDRC_TR 0xFFFFFF94 -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
_TEXT_BASE: .word TEXT_BASE @@ -130,71 +130,71 @@ lowlevelinit:
SMRDATA: .word MC_PUIA - .word MC_PUIA_VAL + .word CONFIG_SYS_MC_PUIA_VAL .word MC_PUP - .word MC_PUP_VAL + .word CONFIG_SYS_MC_PUP_VAL .word MC_PUER - .word MC_PUER_VAL + .word CONFIG_SYS_MC_PUER_VAL .word MC_ASR - .word MC_ASR_VAL + .word CONFIG_SYS_MC_ASR_VAL .word MC_AASR - .word MC_AASR_VAL + .word CONFIG_SYS_MC_AASR_VAL .word EBI_CFGR - .word EBI_CFGR_VAL + .word CONFIG_SYS_EBI_CFGR_VAL .word SMC_CSR0 - .word SMC_CSR0_VAL + .word CONFIG_SYS_SMC_CSR0_VAL .word PLLAR - .word PLLAR_VAL + .word CONFIG_SYS_PLLAR_VAL .word PLLBR - .word PLLBR_VAL + .word CONFIG_SYS_PLLBR_VAL .word MCKR - .word MCKR_VAL + .word CONFIG_SYS_MCKR_VAL /* SMRDATA is 80 bytes long */ /* here there's a delay of 100 */ SMRDATA1: .word PIOC_ASR - .word PIOC_ASR_VAL + .word CONFIG_SYS_PIOC_ASR_VAL .word PIOC_BSR - .word PIOC_BSR_VAL + .word CONFIG_SYS_PIOC_BSR_VAL .word PIOC_PDR - .word PIOC_PDR_VAL + .word CONFIG_SYS_PIOC_PDR_VAL .word EBI_CSA - .word EBI_CSA_VAL + .word CONFIG_SYS_EBI_CSA_VAL .word SDRC_CR - .word SDRC_CR_VAL + .word CONFIG_SYS_SDRC_CR_VAL .word SDRC_MR - .word SDRC_MR_VAL - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL .word SDRC_MR - .word SDRC_MR_VAL1 - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL1 + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL .word SDRC_MR - .word SDRC_MR_VAL2 - .word SDRAM1 - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL2 + .word CONFIG_SYS_SDRAM1 + .word CONFIG_SYS_SDRAM_VAL .word SDRC_TR - .word SDRC_TR_VAL - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_TR_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL .word SDRC_MR - .word SDRC_MR_VAL3 - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL3 + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL /* SMRDATA1 is 176 bytes long */ #endif /* CONFIG_BOOTBINFUNC */ diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S index 66b07da..736f1ea 100644 --- a/cpu/arm920t/at91rm9200/lowlevel_init.S +++ b/cpu/arm920t/at91rm9200/lowlevel_init.S @@ -135,71 +135,71 @@ LoopOsc:
SMRDATA: .word MC_PUIA - .word MC_PUIA_VAL + .word CONFIG_SYS_MC_PUIA_VAL .word MC_PUP - .word MC_PUP_VAL + .word CONFIG_SYS_MC_PUP_VAL .word MC_PUER - .word MC_PUER_VAL + .word CONFIG_SYS_MC_PUER_VAL .word MC_ASR - .word MC_ASR_VAL + .word CONFIG_SYS_MC_ASR_VAL .word MC_AASR - .word MC_AASR_VAL + .word CONFIG_SYS_MC_AASR_VAL .word EBI_CFGR - .word EBI_CFGR_VAL + .word CONFIG_SYS_EBI_CFGR_VAL .word SMC_CSR0 - .word SMC_CSR0_VAL + .word CONFIG_SYS_SMC_CSR0_VAL .word PLLAR - .word PLLAR_VAL + .word CONFIG_SYS_PLLAR_VAL .word PLLBR - .word PLLBR_VAL + .word CONFIG_SYS_PLLBR_VAL .word MCKR - .word MCKR_VAL + .word CONFIG_SYS_MCKR_VAL /* SMRDATA is 80 bytes long */ /* here there's a delay of 100 */ SMRDATA1: .word PIOC_ASR - .word PIOC_ASR_VAL + .word CONFIG_SYS_PIOC_ASR_VAL .word PIOC_BSR - .word PIOC_BSR_VAL + .word CONFIG_SYS_PIOC_BSR_VAL .word PIOC_PDR - .word PIOC_PDR_VAL + .word CONFIG_SYS_PIOC_PDR_VAL .word EBI_CSA - .word EBI_CSA_VAL + .word CONFIG_SYS_EBI_CSA_VAL .word SDRC_CR - .word SDRC_CR_VAL + .word CONFIG_SYS_SDRC_CR_VAL .word SDRC_MR - .word SDRC_MR_VAL - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL .word SDRC_MR - .word SDRC_MR_VAL1 - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL1 + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL .word SDRC_MR - .word SDRC_MR_VAL2 - .word SDRAM1 - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL2 + .word CONFIG_SYS_SDRAM1 + .word CONFIG_SYS_SDRAM_VAL .word SDRC_TR - .word SDRC_TR_VAL - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_TR_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL .word SDRC_MR - .word SDRC_MR_VAL3 - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL3 + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL /* SMRDATA1 is 176 bytes long */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 746f0ef..c7e83cc 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -45,33 +45,33 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */ -#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
/* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #else #define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index cdd308d..d9acb47 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -44,33 +44,33 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
/* clocks */ -#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ +#define CONFIG_SYS_PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
/* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #else #define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/include/configs/csb637.h b/include/configs/csb637.h index 682db44..2df77cf 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -45,33 +45,33 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */ -#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ -#define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */ +#define CONFIG_SYS_PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
/* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x21914159 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #else #define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index cbbdb0c..fb10616 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -49,33 +49,33 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
/* clocks */ -#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ -#define PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
/* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x3211295A /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000020 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x3211295A /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000020 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #else #define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com Cc: Sami Nurmenniemi sanurmen@sysart.fi --- board/m501sk/Makefile | 2 - board/m501sk/memsetup.S | 200 ---------------------------------------------- include/configs/m501sk.h | 33 ++++++++ 3 files changed, 33 insertions(+), 202 deletions(-) delete mode 100644 board/m501sk/memsetup.S
diff --git a/board/m501sk/Makefile b/board/m501sk/Makefile index c562c60..aec3d1c 100644 --- a/board/m501sk/Makefile +++ b/board/m501sk/Makefile @@ -27,8 +27,6 @@ LIB = $(obj)lib$(BOARD).a
COBJS := m501sk.o eeprom.o
-SOBJS := memsetup.o - SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S deleted file mode 100644 index 1a3ca4b..0000000 --- a/board/m501sk/memsetup.S +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the at91rm9200dk board by - * (C) Copyright 2004 - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> - -#ifdef CONFIG_BOOTBINFUNC -/* - * some parameters for the board - * - * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in - * turn is based on the boot.bin code from ATMEL - * - */ - -/* flash */ -#define MC_PUIA 0xFFFFFF10 -#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 -#define MC_PUP 0xFFFFFF50 -#define CONFIG_SYS_MC_PUP_VAL 0x00000000 -#define MC_PUER 0xFFFFFF54 -#define CONFIG_SYS_MC_PUER_VAL 0x00000000 -#define MC_ASR 0xFFFFFF04 -#define CONFIG_SYS_MC_ASR_VAL 0x00000000 -#define MC_AASR 0xFFFFFF08 -#define CONFIG_SYS_MC_AASR_VAL 0x00000000 -#define EBI_CFGR 0xFFFFFF64 -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0 0xFFFFFF70 -#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define PLLAR 0xFFFFFC28 -#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define PLLBR 0xFFFFFC2C -#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define MCKR 0xFFFFFC30 -/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ -#define CONFIG_SYS_MCKR_VAL 0x00000202 - -/* sdram */ -#define PIOC_ASR 0xFFFFF870 -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ -#define PIOC_BSR 0xFFFFF874 -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR 0xFFFFF804 -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA 0xFFFFFF60 -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ -#define SDRC_CR 0xFFFFFF98 -#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ -#define SDRC_MR 0xFFFFFF90 -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR 0xFFFFFF94 -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl lowlevelinit -lowlevelinit: - /* memory control configuration */ - /* this isn't very elegant, but what the heck */ - ldr r0, =SMRDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - add r2, r0, #80 -0: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 0b - /* delay - this is all done by guess */ - ldr r0, =0x00010000 -1: - subs r0, r0, #1 - bhi 1b - ldr r0, =SMRDATA1 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - add r2, r0, #176 -2: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 2b - - /* everything is fine now */ - mov pc, lr - - .ltorg - -SMRDATA: - .word MC_PUIA - .word CONFIG_SYS_MC_PUIA_VAL - .word MC_PUP - .word CONFIG_SYS_MC_PUP_VAL - .word MC_PUER - .word CONFIG_SYS_MC_PUER_VAL - .word MC_ASR - .word CONFIG_SYS_MC_ASR_VAL - .word MC_AASR - .word CONFIG_SYS_MC_AASR_VAL - .word EBI_CFGR - .word CONFIG_SYS_EBI_CFGR_VAL - .word SMC_CSR0 - .word CONFIG_SYS_SMC_CSR0_VAL - .word PLLAR - .word CONFIG_SYS_PLLAR_VAL - .word PLLBR - .word CONFIG_SYS_PLLBR_VAL - .word MCKR - .word CONFIG_SYS_MCKR_VAL - /* SMRDATA is 80 bytes long */ - /* here there's a delay of 100 */ -SMRDATA1: - .word PIOC_ASR - .word CONFIG_SYS_PIOC_ASR_VAL - .word PIOC_BSR - .word CONFIG_SYS_PIOC_BSR_VAL - .word PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL - .word EBI_CSA - .word CONFIG_SYS_EBI_CSA_VAL - .word SDRC_CR - .word CONFIG_SYS_SDRC_CR_VAL - .word SDRC_MR - .word CONFIG_SYS_SDRC_MR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word SDRC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word SDRC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM1 - .word CONFIG_SYS_SDRAM_VAL - .word SDRC_TR - .word CONFIG_SYS_SDRC_TR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word SDRC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_BOOTBINFUNC */ diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h index f09214d..eab37df 100644 --- a/include/configs/m501sk.h +++ b/include/configs/m501sk.h @@ -41,6 +41,39 @@ #define CONFIG_INITRD_TAG 1
#define CONFIG_MENUPROMPT "." +/* + * LowLevel Init + */ +#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 + +/* sdram */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
/* * Size of malloc() pool
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 1229547702-20400-1-git-send-email-plagnioj@jcrosoft.com you wrote:
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com Cc: Sami Nurmenniemi sanurmen@sysart.fi
board/m501sk/memsetup.S | 134 ++++++++++++++++---------------- cpu/arm920t/at91rm9200/lowlevel_init.S | 88 +++++++++++----------- include/configs/at91rm9200dk.h | 46 ++++++------ include/configs/cmc_pu2.h | 46 ++++++------ include/configs/csb637.h | 46 ++++++------ include/configs/mp2usb.h | 46 ++++++------ 6 files changed, 203 insertions(+), 203 deletions(-)
diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S index 6aea723..1a3ca4b 100644 --- a/board/m501sk/memsetup.S +++ b/board/m501sk/memsetup.S @@ -41,50 +41,50 @@
/* flash */ #define MC_PUIA 0xFFFFFF10 -#define MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 #define MC_PUP 0xFFFFFF50 -#define MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 #define MC_PUER 0xFFFFFF54 -#define MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 #define MC_ASR 0xFFFFFF04 -#define MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 #define MC_AASR 0xFFFFFF08 -#define MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 #define EBI_CFGR 0xFFFFFF64 -#define EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 #define SMC_CSR0 0xFFFFFF70 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */ #define PLLAR 0xFFFFFC28 -#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ #define PLLBR 0xFFFFFC2C -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ #define MCKR 0xFFFFFC30 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ -#define MCKR_VAL 0x00000202 +#define CONFIG_SYS_MCKR_VAL 0x00000202
/* sdram */ #define PIOC_ASR 0xFFFFF870 -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ #define PIOC_BSR 0xFFFFF874 -#define PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 #define PIOC_PDR 0xFFFFF804 -#define PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 #define EBI_CSA 0xFFFFFF60 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ #define SDRC_CR 0xFFFFFF98 -#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ #define SDRC_MR 0xFFFFFF90 -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define SDRC_TR 0xFFFFFF94 -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
I think it is fundamentally wrong to put these #defines in the board's memsetup.S file. The do not belong into some source file, but into the board config file, include/configs/<name>
If we touch this part, should we not do it right, then?
Best regards,
Wolfgang Denk
On 22:41 Wed 17 Dec , Wolfgang Denk wrote:
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 1229547702-20400-1-git-send-email-plagnioj@jcrosoft.com you wrote:
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com Cc: Sami Nurmenniemi sanurmen@sysart.fi
board/m501sk/memsetup.S | 134 ++++++++++++++++---------------- cpu/arm920t/at91rm9200/lowlevel_init.S | 88 +++++++++++----------- include/configs/at91rm9200dk.h | 46 ++++++------ include/configs/cmc_pu2.h | 46 ++++++------ include/configs/csb637.h | 46 ++++++------ include/configs/mp2usb.h | 46 ++++++------ 6 files changed, 203 insertions(+), 203 deletions(-)
diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S index 6aea723..1a3ca4b 100644 --- a/board/m501sk/memsetup.S +++ b/board/m501sk/memsetup.S @@ -41,50 +41,50 @@
/* flash */ #define MC_PUIA 0xFFFFFF10 -#define MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 #define MC_PUP 0xFFFFFF50 -#define MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 #define MC_PUER 0xFFFFFF54 -#define MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 #define MC_ASR 0xFFFFFF04 -#define MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 #define MC_AASR 0xFFFFFF08 -#define MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 #define EBI_CFGR 0xFFFFFF64 -#define EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 #define SMC_CSR0 0xFFFFFF70 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */ #define PLLAR 0xFFFFFC28 -#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ #define PLLBR 0xFFFFFC2C -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ #define MCKR 0xFFFFFC30 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ -#define MCKR_VAL 0x00000202 +#define CONFIG_SYS_MCKR_VAL 0x00000202
/* sdram */ #define PIOC_ASR 0xFFFFF870 -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ #define PIOC_BSR 0xFFFFF874 -#define PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 #define PIOC_PDR 0xFFFFF804 -#define PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 #define EBI_CSA 0xFFFFFF60 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ #define SDRC_CR 0xFFFFFF98 -#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ #define SDRC_MR 0xFFFFFF90 -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define SDRC_TR 0xFFFFFF94 -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
I think it is fundamentally wrong to put these #defines in the board's memsetup.S file. The do not belong into some source file, but into the board config file, include/configs/<name>
If we touch this part, should we not do it right, then?
It's done in the second patch
Best Regards, J.
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 20081217214818.GC10620@game.jcrosoft.org you wrote:
+#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define SDRC_TR 0xFFFFFF94 -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
I think it is fundamentally wrong to put these #defines in the board's memsetup.S file. The do not belong into some source file, but into the board config file, include/configs/<name>
If we touch this part, should we not do it right, then?
It's done in the second patch
Not really.
Your patch leaves #defines like MC_PUIA, MC_PUP, MC_PUER, MC_ASR, MC_AASR, ... untouched. These shouldbe fixed, too.
And your patch fixes only this board. We have the same cruft for example in cpu/arm920t/at91rm9200/lowlevel_init.S
Best regards,
Wolfgang Denk
On 23:30 Wed 17 Dec , Wolfgang Denk wrote:
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 20081217214818.GC10620@game.jcrosoft.org you wrote:
+#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define SDRC_TR 0xFFFFFF94 -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
I think it is fundamentally wrong to put these #defines in the board's memsetup.S file. The do not belong into some source file, but into the board config file, include/configs/<name>
If we touch this part, should we not do it right, then?
It's done in the second patch
Not really.
Your patch leaves #defines like MC_PUIA, MC_PUP, MC_PUER, MC_ASR, MC_AASR, ... untouched. These shouldbe fixed, too.
And your patch fixes only this board. We have the same cruft for example in cpu/arm920t/at91rm9200/lowlevel_init.S
the register cleanup will be done in a third path (the lowlevel_init.S)
Best Regards, J.
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 20081217224624.GE10620@game.jcrosoft.org you wrote:
Your patch leaves #defines like MC_PUIA, MC_PUP, MC_PUER, MC_ASR, MC_AASR, ... untouched. These shouldbe fixed, too.
And your patch fixes only this board. We have the same cruft for example in cpu/arm920t/at91rm9200/lowlevel_init.S
the register cleanup will be done in a third path (the lowlevel_init.S)
And cpu/arm920t/at91rm9200/lowlevel_init.S in another one?
Well, I think it is best then that we wait until you have all parts of that patch series together and submit (and apply) them in a bunch.
Best regards,
Wolfgang Denk
participants (2)
-
Jean-Christophe PLAGNIOL-VILLARD -
Wolfgang Denk