From: Ye Li ye.li@nxp.com

S400 enables RDC only when the DBD_EN is fused. Otherwise, the RDC is allowed by all masters.

Current S400 has issue if the XRDC has released to A35, then A35 reset will fail in ROM due to S400 fails to get XRDC. So temp work around is checking the DBD_EN, if it is not fused, we don't need to call release XRDC or TRDC.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8ulp/soc.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index bba6323f96..b25f5f2521 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -23,6 +23,7 @@ #include <dm/uclass.h> #include <dm/device.h> #include <dm/uclass-internal.h> +#include <fuse.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -468,11 +469,22 @@ static int trdc_set_access(void) int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { + u32 val = 0; + int ret; + bool rdc_en = true; /* Default assume DBD_EN is set */ + /* Disable wdog */ init_wdog();

+ /* Read DBD_EN fuse */ + ret = fuse_read(8, 1, &val); + if (!ret) + rdc_en = !!(val & 0x4000); + if (get_boot_mode() == SINGLE_BOOT) { - release_rdc(RDC_TRDC); + if (rdc_en) + release_rdc(RDC_TRDC); + trdc_set_access(); /* LPAV to APD */ setbits_le32(0x2802B044, BIT(7)); @@ -482,8 +494,10 @@ int arch_cpu_init(void) setbits_le32(0x2802B04C, BIT(1) | BIT(2) | BIT(3) | BIT(4)); }

- /* release xrdc, then allow A35 to write SRAM2 */ - release_rdc(RDC_XRDC); + /* Release xrdc, then allow A35 to write SRAM2 */ + if (rdc_en) + release_rdc(RDC_XRDC); + xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);

clock_init();

From: Ye Li ye.li@nxp.com

When single boot, assign AP domain as the master domain of the LPAV. Allocates LPAV master and slave resources like GPU, DCNano, MIPI-DSI eDMA channel and eDMA request to APD

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8ulp/soc.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index b25f5f2521..7898cb0ed9 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -466,6 +466,20 @@ static int trdc_set_access(void) return 0; }

+void lpav_configure(void) +{ + /* LPAV to APD */ + setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7)); + + /* GPU 2D/3D/DCNANO/MIPI_DSI to APD */ + setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, BIT(1) | BIT(2) | BIT(3) | BIT(4)); + + /* LPAV slave/dma2 ch allocation and request allocation to APD */ + writel(0x1f, SIM_SEC_BASE_ADDR + 0x50); + writel(0xffffffff, SIM_SEC_BASE_ADDR + 0x54); + writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58); +} + int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { @@ -486,12 +500,8 @@ int arch_cpu_init(void) release_rdc(RDC_TRDC);

trdc_set_access(); - /* LPAV to APD */ - setbits_le32(0x2802B044, BIT(7)); - /* GPU 2D/3D to APD */ - setbits_le32(0x2802B04C, BIT(1) | BIT(2)); - /* DCNANO and MIPI_DSI to APD */ - setbits_le32(0x2802B04C, BIT(1) | BIT(2) | BIT(3) | BIT(4)); + + lpav_configure(); }

/* Release xrdc, then allow A35 to write SRAM2 */

From: Peng Fan peng.fan@nxp.com

Assign the PXP/HIFI4/EPDC to APD domain, otherwise APD not able to receive interrupts from the modules.

Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8ulp/soc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 7898cb0ed9..e0574112cd 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -471,8 +471,8 @@ void lpav_configure(void) /* LPAV to APD */ setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7));

- /* GPU 2D/3D/DCNANO/MIPI_DSI to APD */ - setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, BIT(1) | BIT(2) | BIT(3) | BIT(4)); + /* PXP/GPU 2D/3D/DCNANO/MIPI_DSI/EPDC/HIFI4 to APD */ + setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, 0x7F);

/* LPAV slave/dma2 ch allocation and request allocation to APD */ writel(0x1f, SIM_SEC_BASE_ADDR + 0x50);

From: Ye Li ye.li@nxp.com

Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8ulp/cgc.h | 32 ++- arch/arm/include/asm/arch-imx8ulp/pcc.h | 66 ++++- arch/arm/mach-imx/imx8ulp/cgc.c | 314 ++++++++++++++++++++---- arch/arm/mach-imx/imx8ulp/clock.c | 48 +++- arch/arm/mach-imx/imx8ulp/pcc.c | 130 ++++++++-- 5 files changed, 508 insertions(+), 82 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h index 34a15fb59c..745fd7f5e8 100644 --- a/arch/arm/include/asm/arch-imx8ulp/cgc.h +++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h @@ -6,11 +6,15 @@ #ifndef _ASM_ARCH_CGC_H #define _ASM_ARCH_CGC_H

-enum cgc1_clk { +enum cgc_clk { DUMMY0_CLK, DUMMY1_CLK, LPOSC, + NIC_APCLK, + NIC_PERCLK, + XBAR_APCLK, XBAR_BUSCLK, + AD_SLOWCLK, SOSC, SOSC_DIV1, SOSC_DIV2, @@ -34,6 +38,24 @@ enum cgc1_clk { PLL3_PFD2_DIV2, PLL3_PFD3_DIV1, PLL3_PFD3_DIV2, + LVDS, + LPAV_AXICLK, + LPAV_AHBCLK, + LPAV_BUSCLK, + PLL4, + PLL4_VCODIV, + PLL4_PFD0, + PLL4_PFD1, + PLL4_PFD2, + PLL4_PFD3, + PLL4_PFD0_DIV1, + PLL4_PFD0_DIV2, + PLL4_PFD1_DIV1, + PLL4_PFD1_DIV2, + PLL4_PFD2_DIV1, + PLL4_PFD2_DIV2, + PLL4_PFD3_DIV1, + PLL4_PFD3_DIV2, };

struct cgc1_regs { @@ -119,12 +141,16 @@ struct cgc2_regs { u32 lvdscfg; };

-u32 cgc1_clk_get_rate(enum cgc1_clk clk); +u32 cgc_clk_get_rate(enum cgc_clk clk); void cgc1_pll3_init(void); void cgc1_pll2_init(void); void cgc1_soscdiv_init(void); void cgc1_init_core_clk(void); void cgc2_pll4_init(void); void cgc2_ddrclk_config(u32 src, u32 div); -u32 cgc1_sosc_div(enum cgc1_clk clk); +u32 cgc1_sosc_div(enum cgc_clk clk); +void cgc1_enet_stamp_sel(u32 clk_src); +void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd); +void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div); +void cgc2_lpav_init(enum cgc_clk clk); #endif diff --git a/arch/arm/include/asm/arch-imx8ulp/pcc.h b/arch/arm/include/asm/arch-imx8ulp/pcc.h index 091d0175dd..468015482b 100644 --- a/arch/arm/include/asm/arch-imx8ulp/pcc.h +++ b/arch/arm/include/asm/arch-imx8ulp/pcc.h @@ -90,6 +90,68 @@ enum pcc4_entry { RGPIOF_PCC4_SLOT = 31, };

+enum pcc5_entry { + DMA2_MP_PCC5_SLOT = 0, + DMA2_CH0_PCC5_SLOT = 1, + DMA2_CH1_PCC5_SLOT = 2, + DMA2_CH2_PCC5_SLOT = 3, + DMA2_CH3_PCC5_SLOT = 4, + DMA2_CH4_PCC5_SLOT = 5, + DMA2_CH5_PCC5_SLOT = 6, + DMA2_CH6_PCC5_SLOT = 7, + DMA2_CH7_PCC5_SLOT = 8, + DMA2_CH8_PCC5_SLOT = 9, + DMA2_CH9_PCC5_SLOT = 10, + DMA2_CH10_PCC5_SLOT = 11, + DMA2_CH11_PCC5_SLOT = 12, + DMA2_CH12_PCC5_SLOT = 13, + DMA2_CH13_PCC5_SLOT = 14, + DMA2_CH14_PCC5_SLOT = 15, + DMA2_CH15_PCC5_SLOT = 16, + DMA2_CH16_PCC5_SLOT = 17, + DMA2_CH17_PCC5_SLOT = 18, + DMA2_CH18_PCC5_SLOT = 19, + DMA2_CH19_PCC5_SLOT = 20, + DMA2_CH20_PCC5_SLOT = 21, + DMA2_CH21_PCC5_SLOT = 22, + DMA2_CH22_PCC5_SLOT = 23, + DMA2_CH23_PCC5_SLOT = 24, + DMA2_CH24_PCC5_SLOT = 25, + DMA2_CH25_PCC5_SLOT = 26, + DMA2_CH26_PCC5_SLOT = 27, + DMA2_CH27_PCC5_SLOT = 28, + DMA2_CH28_PCC5_SLOT = 29, + DMA2_CH29_PCC5_SLOT = 30, + DMA2_CH30_PCC5_SLOT = 31, + DMA2_CH31_PCC5_SLOT = 32, + MU2_B_PCC5_SLOT = 33, + MU3_B_PCC5_SLOT = 34, + SEMA42_2_PCC5_SLOT = 35, + CMC2_PCC5_SLOT = 36, + AVD_SIM_PCC5_SLOT = 37, + LPAV_CGC_PCC5_SLOT = 38, + PCC5_PCC5_SLOT = 39, + TPM8_PCC5_SLOT = 40, + SAI6_PCC5_SLOT = 41, + SAI7_PCC5_SLOT = 42, + SPDIF_PCC5_SLOT = 43, + ISI_PCC5_SLOT = 44, + CSI_REGS_PCC5_SLOT = 45, + CSI_PCC5_SLOT = 47, + DSI_PCC5_SLOT = 48, + WDOG5_PCC5_SLOT = 50, + EPDC_PCC5_SLOT = 51, + PXP_PCC5_SLOT = 52, + SFA2_PCC5_SLOT = 53, + GPU2D_PCC5_SLOT = 60, + GPU3D_PCC5_SLOT = 61, + DCNANO_PCC5_SLOT = 62, + LPDDR4_PCC5_SLOT = 66, + CSI_CLK_UI_PCC5_SLOT = 67, + CSI_CLK_ESC_PCC5_SLOT = 68, + RGPIOD_PCC5_SLOT = 69, +}; + /* PCC registers */ #define PCC_PR_OFFSET 31 #define PCC_PR_MASK (0x1 << PCC_PR_OFFSET) @@ -130,10 +192,10 @@ struct pcc_entry { };

int pcc_clock_enable(int pcc_controller, int pcc_clk_slot, bool enable); -int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src); +int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc_clk src); int pcc_clock_div_config(int pcc_controller, int pcc_clk_slot, bool frac, u8 div); bool pcc_clock_is_enable(int pcc_controller, int pcc_clk_slot); -int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *src); +int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc_clk *src); int pcc_reset_peripheral(int pcc_controller, int pcc_clk_slot, bool reset); u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot); #endif diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index 7bfc3862cd..fc84f3f293 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -189,8 +189,8 @@ void cgc2_pll4_init(void) ;

/* Enable all 4 PFDs */ - setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 0); /* 316.8Mhz for NIC_LPAV */ - setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 8); + setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); + setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */ setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16); setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24);

@@ -205,6 +205,68 @@ void cgc2_pll4_init(void) clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31)); }

+void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd) +{ + void __iomem *reg = &cgc2_regs->pll4div_pfd0; + u32 halt_mask = BIT(7) | BIT(15); + u32 pfd_shift = (pllpfd - PLL4_PFD0) * 8; + u32 val; + + if (pllpfd < PLL4_PFD0 || pllpfd > PLL4_PFD3) + return; + + if ((pllpfd - PLL4_PFD0) >> 1) + reg = &cgc2_regs->pll4div_pfd1; + + halt_mask = halt_mask << (((pllpfd - PLL4_PFD0) & 0x1) * 16); + + /* halt pfd div */ + setbits_le32(reg, halt_mask); + + /* gate pfd */ + setbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) << pfd_shift); + + val = readl(&cgc2_regs->pll4pfdcfg); + val &= ~(0x3f << pfd_shift); + val |= (pfd << pfd_shift); + writel(val, &cgc2_regs->pll4pfdcfg); + + /* ungate */ + clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) << pfd_shift); + + /* Wait stable */ + while ((readl(&cgc2_regs->pll4pfdcfg) & (BIT(6) << pfd_shift)) + != (BIT(6) << pfd_shift)) + ; + + /* enable pfd div */ + clrbits_le32(reg, halt_mask); +} + +void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div) +{ + void __iomem *reg = &cgc2_regs->pll4div_pfd0; + u32 shift = ((pllpfddiv - PLL4_PFD0_DIV1) & 0x3) * 8; + + if (pllpfddiv < PLL4_PFD0_DIV1 || pllpfddiv > PLL4_PFD3_DIV2) + return; + + if ((pllpfddiv - PLL4_PFD0_DIV1) >> 2) + reg = &cgc2_regs->pll4div_pfd1; + + /* Halt pfd div */ + setbits_le32(reg, BIT(7) << shift); + + /* Clear div */ + clrbits_le32(reg, 0x3f << shift); + + /* Set div*/ + setbits_le32(reg, div << shift); + + /* Enable pfd div */ + clrbits_le32(reg, BIT(7) << shift); +} + void cgc2_ddrclk_config(u32 src, u32 div) { writel((src << 28) | (div << 21), &cgc2_regs->ddrclk); @@ -213,7 +275,63 @@ void cgc2_ddrclk_config(u32 src, u32 div) ; }

-u32 decode_pll(enum cgc1_clk pll) +void cgc2_lpav_init(enum cgc_clk clk) +{ + u32 i, scs, reg; + const enum cgc_clk src[] = {FRO, PLL4_PFD1, SOSC, LVDS}; + + reg = readl(&cgc2_regs->niclpavclk); + scs = (reg >> 28) & 0x3; + + for (i = 0; i < 4; i++) { + if (clk == src[i]) { + if (scs == i) + return; + + reg &= ~(0x3 << 28); + reg |= (i << 28); + + writel(reg, &cgc2_regs->niclpavclk); + break; + } + } + + if (i == 4) + printf("Invalid clock source [%u] for LPAV\n", clk); +} + +u32 cgc2_nic_get_rate(enum cgc_clk clk) +{ + u32 reg, rate; + u32 scs, lpav_axi_clk, lpav_ahb_clk, lpav_bus_clk; + const enum cgc_clk src[] = {FRO, PLL4_PFD1, SOSC, LVDS}; + + reg = readl(&cgc2_regs->niclpavclk); + scs = (reg >> 28) & 0x3; + lpav_axi_clk = ((reg >> 21) & 0x3f) + 1; + lpav_ahb_clk = ((reg >> 14) & 0x3f) + 1; + lpav_bus_clk = ((reg >> 7) & 0x3f) + 1; + + rate = cgc_clk_get_rate(src[scs]); + + switch (clk) { + case LPAV_AXICLK: + rate = rate / lpav_axi_clk; + break; + case LPAV_AHBCLK: + rate = rate / (lpav_axi_clk * lpav_ahb_clk); + break; + case LPAV_BUSCLK: + rate = rate / (lpav_axi_clk * lpav_bus_clk); + break; + default: + return 0; + } + + return rate; +} + +u32 decode_pll(enum cgc_clk pll) { u32 reg, infreq, mult; u32 num, denom; @@ -246,6 +364,17 @@ u32 decode_pll(enum cgc1_clk pll) denom = readl(&cgc1_regs->pll3denom) & 0x3FFFFFFF; num = readl(&cgc1_regs->pll3num) & 0x3FFFFFFF;

+ return (u64)infreq * mult + (u64)infreq * num / denom; + case PLL4: + reg = readl(&cgc2_regs->pll4csr); + if (!(reg & BIT(24))) + return 0; + + reg = readl(&cgc2_regs->pll4cfg); + mult = (reg >> 16) & 0x7F; + denom = readl(&cgc2_regs->pll4denom) & 0x3FFFFFFF; + num = readl(&cgc2_regs->pll4num) & 0x3FFFFFFF; + return (u64)infreq * mult + (u64)infreq * num / denom; default: printf("Unsupported pll clocks %d\n", pll); @@ -255,93 +384,117 @@ u32 decode_pll(enum cgc1_clk pll) return 0; }

-u32 cgc1_pll3_vcodiv_rate(void) +u32 cgc_pll_vcodiv_rate(enum cgc_clk clk) { u32 reg, gate, div; + void __iomem *plldiv_vco; + enum cgc_clk pll; + + if (clk == PLL3_VCODIV) { + plldiv_vco = &cgc1_regs->pll3div_vco; + pll = PLL3; + } else { + plldiv_vco = &cgc2_regs->pll4div_vco; + pll = PLL4; + }

- reg = readl(&cgc1_regs->pll3div_vco); + reg = readl(plldiv_vco); gate = BIT(7) & reg; div = reg & 0x3F;

- return gate ? 0 : decode_pll(PLL3) / (div + 1); + return gate ? 0 : decode_pll(pll) / (div + 1); }

-u32 cgc1_pll3_pfd_rate(enum cgc1_clk clk) +u32 cgc_pll_pfd_rate(enum cgc_clk clk) { u32 index, gate, vld, reg; + void __iomem *pllpfdcfg; + enum cgc_clk pll;

switch (clk) { case PLL3_PFD0: - index = 0; - break; case PLL3_PFD1: - index = 1; - break; case PLL3_PFD2: - index = 2; - break; case PLL3_PFD3: - index = 3; + index = clk - PLL3_PFD0; + pllpfdcfg = &cgc1_regs->pll3pfdcfg; + pll = PLL3; + break; + case PLL4_PFD0: + case PLL4_PFD1: + case PLL4_PFD2: + case PLL4_PFD3: + index = clk - PLL4_PFD0; + pllpfdcfg = &cgc2_regs->pll4pfdcfg; + pll = PLL4; break; default: return 0; }

- reg = readl(&cgc1_regs->pll3pfdcfg); + reg = readl(pllpfdcfg); gate = reg & (BIT(7) << (index * 8)); vld = reg & (BIT(6) << (index * 8));

if (gate || !vld) return 0;

- return (u64)decode_pll(PLL3) * 18 / ((reg >> (index * 8)) & 0x3F); + return (u64)decode_pll(pll) * 18 / ((reg >> (index * 8)) & 0x3F); }

-u32 cgc1_pll3_pfd_div(enum cgc1_clk clk) +u32 cgc_pll_pfd_div(enum cgc_clk clk) { void __iomem *base; u32 pfd, index, gate, reg;

switch (clk) { case PLL3_PFD0_DIV1: - base = &cgc1_regs->pll3div_pfd0; - pfd = PLL3_PFD0; - index = 0; - break; case PLL3_PFD0_DIV2: base = &cgc1_regs->pll3div_pfd0; pfd = PLL3_PFD0; - index = 1; + index = clk - PLL3_PFD0_DIV1; break; case PLL3_PFD1_DIV1: - base = &cgc1_regs->pll3div_pfd0; - pfd = PLL3_PFD1; - index = 2; - break; case PLL3_PFD1_DIV2: base = &cgc1_regs->pll3div_pfd0; pfd = PLL3_PFD1; - index = 3; + index = clk - PLL3_PFD0_DIV1; break; case PLL3_PFD2_DIV1: - base = &cgc1_regs->pll3div_pfd1; - pfd = PLL3_PFD2; - index = 0; - break; case PLL3_PFD2_DIV2: base = &cgc1_regs->pll3div_pfd1; pfd = PLL3_PFD2; - index = 1; + index = clk - PLL3_PFD2_DIV1; break; case PLL3_PFD3_DIV1: - base = &cgc1_regs->pll3div_pfd1; - pfd = PLL3_PFD3; - index = 2; - break; case PLL3_PFD3_DIV2: base = &cgc1_regs->pll3div_pfd1; pfd = PLL3_PFD3; - index = 3; + index = clk - PLL3_PFD2_DIV1; + break; + case PLL4_PFD0_DIV1: + case PLL4_PFD0_DIV2: + base = &cgc2_regs->pll4div_pfd0; + pfd = PLL4_PFD0; + index = clk - PLL4_PFD0_DIV1; + break; + case PLL4_PFD1_DIV1: + case PLL4_PFD1_DIV2: + base = &cgc2_regs->pll4div_pfd0; + pfd = PLL4_PFD1; + index = clk - PLL4_PFD0_DIV1; + break; + case PLL4_PFD2_DIV1: + case PLL4_PFD2_DIV2: + base = &cgc2_regs->pll4div_pfd1; + pfd = PLL4_PFD2; + index = clk - PLL4_PFD2_DIV1; + break; + case PLL4_PFD3_DIV1: + case PLL4_PFD3_DIV2: + base = &cgc2_regs->pll4div_pfd1; + pfd = PLL4_PFD3; + index = clk - PLL4_PFD2_DIV1; break; default: return 0; @@ -353,10 +506,52 @@ u32 cgc1_pll3_pfd_div(enum cgc1_clk clk) if (gate) return 0;

- return cgc1_pll3_pfd_rate(pfd) / (((reg >> (index * 8)) & 0x3F) + 1); + return cgc_pll_pfd_rate(pfd) / (((reg >> (index * 8)) & 0x3F) + 1); +} + +u32 cgc1_nic_get_rate(enum cgc_clk clk) +{ + u32 reg, rate; + u32 scs, nic_ad_divplat, nic_per_divplat; + u32 xbar_ad_divplat, xbar_divbus, ad_slow; + const enum cgc_clk src[] = {FRO, PLL3_PFD0, SOSC, LVDS}; + + reg = readl(&cgc1_regs->nicclk); + scs = (reg >> 28) & 0x3; + nic_ad_divplat = ((reg >> 21) & 0x3f) + 1; + nic_per_divplat = ((reg >> 14) & 0x3f) + 1; + + reg = readl(&cgc1_regs->xbarclk); + xbar_ad_divplat = ((reg >> 14) & 0x3f) + 1; + xbar_divbus = ((reg >> 7) & 0x3f) + 1; + ad_slow = (reg & 0x3f) + 1; + + rate = cgc_clk_get_rate(src[scs]); + + switch (clk) { + case NIC_APCLK: + rate = rate / nic_ad_divplat; + break; + case NIC_PERCLK: + rate = rate / (nic_ad_divplat * nic_per_divplat); + break; + case XBAR_APCLK: + rate = rate / (nic_ad_divplat * xbar_ad_divplat); + break; + case XBAR_BUSCLK: + rate = rate / (nic_ad_divplat * xbar_ad_divplat * xbar_divbus); + break; + case AD_SLOWCLK: + rate = rate / (nic_ad_divplat * xbar_ad_divplat * ad_slow); + break; + default: + return 0; + } + + return rate; }

-u32 cgc1_sosc_div(enum cgc1_clk clk) +u32 cgc1_sosc_div(enum cgc_clk clk) { u32 reg, gate, index;

@@ -385,7 +580,7 @@ u32 cgc1_sosc_div(enum cgc1_clk clk) return 24000000 / (((reg >> (index * 8)) & 0x3F) + 1); }

-u32 cgc1_fro_div(enum cgc1_clk clk) +u32 cgc1_fro_div(enum cgc_clk clk) { u32 reg, gate, vld, index;

@@ -415,9 +610,11 @@ u32 cgc1_fro_div(enum cgc1_clk clk) return 24000000 / (((reg >> (index * 8)) & 0x3F) + 1); }

-u32 cgc1_clk_get_rate(enum cgc1_clk clk) +u32 cgc_clk_get_rate(enum cgc_clk clk) { switch (clk) { + case LVDS: + return 0; /* No external LVDS clock used */ case SOSC: case SOSC_DIV1: case SOSC_DIV2: @@ -429,16 +626,21 @@ u32 cgc1_clk_get_rate(enum cgc1_clk clk) case FRO_DIV3: return cgc1_fro_div(clk); case PLL2: - return decode_pll(PLL2); case PLL3: - return decode_pll(PLL3); + case PLL4: + return decode_pll(clk); case PLL3_VCODIV: - return cgc1_pll3_vcodiv_rate(); + case PLL4_VCODIV: + return cgc_pll_vcodiv_rate(clk); case PLL3_PFD0: case PLL3_PFD1: case PLL3_PFD2: case PLL3_PFD3: - return cgc1_pll3_pfd_rate(clk); + case PLL4_PFD0: + case PLL4_PFD1: + case PLL4_PFD2: + case PLL4_PFD3: + return cgc_pll_pfd_rate(clk); case PLL3_PFD0_DIV1: case PLL3_PFD0_DIV2: case PLL3_PFD1_DIV1: @@ -447,9 +649,27 @@ u32 cgc1_clk_get_rate(enum cgc1_clk clk) case PLL3_PFD2_DIV2: case PLL3_PFD3_DIV1: case PLL3_PFD3_DIV2: - return cgc1_pll3_pfd_div(clk); + case PLL4_PFD0_DIV1: + case PLL4_PFD0_DIV2: + case PLL4_PFD1_DIV1: + case PLL4_PFD1_DIV2: + case PLL4_PFD2_DIV1: + case PLL4_PFD2_DIV2: + case PLL4_PFD3_DIV1: + case PLL4_PFD3_DIV2: + return cgc_pll_pfd_div(clk); + case NIC_APCLK: + case NIC_PERCLK: + case XBAR_APCLK: + case XBAR_BUSCLK: + case AD_SLOWCLK: + return cgc1_nic_get_rate(clk); + case LPAV_AXICLK: + case LPAV_AHBCLK: + case LPAV_BUSCLK: + return cgc2_nic_get_rate(clk); default: - printf("Unsupported cgc1 clock: %d\n", clk); + printf("Unsupported cgc clock: %d\n", clk); return 0; } } diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index ebbaad4106..2beacbceb0 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; #define PLL_USB_LOCK_MASK (0x01 << 31) #define PCC5_LPDDR4_ADDR 0x2da70108

-static void lpuart_set_clk(u32 index, enum cgc1_clk clk) +static void lpuart_set_clk(u32 index, enum cgc_clk clk) { const u32 lpuart_pcc_slots[] = { LPUART4_PCC3_SLOT, @@ -327,7 +327,7 @@ u32 mxc_get_clock(enum mxc_clock clk) case MXC_ESDHC3_CLK: return pcc_clock_get_rate(4, SDHC2_PCC4_SLOT); case MXC_ARM_CLK: - return cgc1_clk_get_rate(PLL2); + return cgc_clk_get_rate(PLL2); default: return 0; } @@ -376,16 +376,40 @@ int do_mx8ulp_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const printf("SDHC1 %8d MHz\n", pcc_clock_get_rate(4, SDHC1_PCC4_SLOT) / 1000000); printf("SDHC2 %8d MHz\n", pcc_clock_get_rate(4, SDHC2_PCC4_SLOT) / 1000000);

- printf("SOSC %8d MHz\n", cgc1_clk_get_rate(SOSC) / 1000000); - printf("FRO %8d MHz\n", cgc1_clk_get_rate(FRO) / 1000000); - printf("PLL2 %8d MHz\n", cgc1_clk_get_rate(PLL2) / 1000000); - printf("PLL3 %8d MHz\n", cgc1_clk_get_rate(PLL3) / 1000000); - printf("PLL3_VCODIV %8d MHz\n", cgc1_clk_get_rate(PLL3_VCODIV) / 1000000); - printf("PLL3_PFD0 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD0) / 1000000); - printf("PLL3_PFD1 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD1) / 1000000); - printf("PLL3_PFD2 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD2) / 1000000); - printf("PLL3_PFD3 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD3) / 1000000); - + printf("SOSC %8d MHz\n", cgc_clk_get_rate(SOSC) / 1000000); + printf("FRO %8d MHz\n", cgc_clk_get_rate(FRO) / 1000000); + printf("PLL2 %8d MHz\n", cgc_clk_get_rate(PLL2) / 1000000); + printf("PLL3 %8d MHz\n", cgc_clk_get_rate(PLL3) / 1000000); + printf("PLL3_VCODIV %8d MHz\n", cgc_clk_get_rate(PLL3_VCODIV) / 1000000); + printf("PLL3_PFD0 %8d MHz\n", cgc_clk_get_rate(PLL3_PFD0) / 1000000); + printf("PLL3_PFD1 %8d MHz\n", cgc_clk_get_rate(PLL3_PFD1) / 1000000); + printf("PLL3_PFD2 %8d MHz\n", cgc_clk_get_rate(PLL3_PFD2) / 1000000); + printf("PLL3_PFD3 %8d MHz\n", cgc_clk_get_rate(PLL3_PFD3) / 1000000); + + printf("PLL4_PFD0 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD0) / 1000000); + printf("PLL4_PFD1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD1) / 1000000); + printf("PLL4_PFD2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD2) / 1000000); + printf("PLL4_PFD3 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD3) / 1000000); + + printf("PLL4_PFD0_DIV1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD0_DIV1) / 1000000); + printf("PLL4_PFD0_DIV2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD0_DIV2) / 1000000); + printf("PLL4_PFD1_DIV1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD1_DIV1) / 1000000); + printf("PLL4_PFD1_DIV2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD1_DIV2) / 1000000); + + printf("PLL4_PFD2_DIV1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD2_DIV1) / 1000000); + printf("PLL4_PFD2_DIV2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD2_DIV2) / 1000000); + printf("PLL4_PFD3_DIV1 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD3_DIV1) / 1000000); + printf("PLL4_PFD3_DIV2 %8d MHz\n", cgc_clk_get_rate(PLL4_PFD3_DIV2) / 1000000); + + printf("LPAV_AXICLK %8d MHz\n", cgc_clk_get_rate(LPAV_AXICLK) / 1000000); + printf("LPAV_AHBCLK %8d MHz\n", cgc_clk_get_rate(LPAV_AHBCLK) / 1000000); + printf("LPAV_BUSCLK %8d MHz\n", cgc_clk_get_rate(LPAV_BUSCLK) / 1000000); + printf("NIC_APCLK %8d MHz\n", cgc_clk_get_rate(NIC_APCLK) / 1000000); + + printf("NIC_PERCLK %8d MHz\n", cgc_clk_get_rate(NIC_PERCLK) / 1000000); + printf("XBAR_APCLK %8d MHz\n", cgc_clk_get_rate(XBAR_APCLK) / 1000000); + printf("XBAR_BUSCLK %8d MHz\n", cgc_clk_get_rate(XBAR_BUSCLK) / 1000000); + printf("AD_SLOWCLK %8d MHz\n", cgc_clk_get_rate(AD_SLOWCLK) / 1000000); return 0; }

diff --git a/arch/arm/mach-imx/imx8ulp/pcc.c b/arch/arm/mach-imx/imx8ulp/pcc.c index 711b685cd7..6145b3ea6a 100644 --- a/arch/arm/mach-imx/imx8ulp/pcc.c +++ b/arch/arm/mach-imx/imx8ulp/pcc.c @@ -12,10 +12,10 @@ #include <asm/arch/cgc.h> #include <asm/arch/sys_proto.h>

-#define cgc1_clk_TYPES 2 -#define cgc1_clk_NUM 8 +#define cgc_clk_TYPES 2 +#define cgc_clk_NUM 8

-static enum cgc1_clk pcc3_clksrc[][8] = { +static enum cgc_clk pcc3_clksrc[][8] = { { }, { DUMMY0_CLK, @@ -29,7 +29,7 @@ static enum cgc1_clk pcc3_clksrc[][8] = { } };

-static enum cgc1_clk pcc4_clksrc[][8] = { +static enum cgc_clk pcc4_clksrc[][8] = { { DUMMY0_CLK, SOSC_DIV1, @@ -52,6 +52,29 @@ static enum cgc1_clk pcc4_clksrc[][8] = { } };

+static enum cgc_clk pcc5_clksrc[][8] = { + { + DUMMY0_CLK, + PLL4_PFD3_DIV2, + PLL4_PFD2_DIV2, + PLL4_PFD2_DIV1, + PLL4_PFD1_DIV2, + PLL4_PFD1_DIV1, + PLL4_PFD0_DIV2, + PLL4_PFD0_DIV1 + }, + { + DUMMY0_CLK, + DUMMY1_CLK, + LPOSC, + SOSC_DIV2, + FRO_DIV2, + LPAV_BUSCLK, + PLL4_VCODIV, + PLL4_PFD3_DIV1 + } +}; + static struct pcc_entry pcc3_arrays[] = { {PCC3_RBASE, DMA1_MP_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, {PCC3_RBASE, DMA1_CH0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, @@ -136,6 +159,69 @@ static struct pcc_entry pcc4_arrays[] = { {} };

+static struct pcc_entry pcc5_arrays[] = { + {PCC5_RBASE, DMA2_MP_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH0_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH1_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH2_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH3_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH4_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH5_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH6_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH7_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH8_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH9_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH10_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH11_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH12_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH13_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH14_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH15_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH16_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH17_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH18_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH19_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH20_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH21_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH22_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH23_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH24_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH25_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH26_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH27_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH28_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH29_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH30_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, DMA2_CH31_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, MU2_B_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, MU3_B_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, SEMA42_2_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, CMC2_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, AVD_SIM_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, LPAV_CGC_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, PCC5_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, TPM8_PCC5_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, SAI6_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, SAI7_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, SPDIF_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, ISI_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, CSI_REGS_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, CSI_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, DSI_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, WDOG5_PCC5_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, EPDC_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, PXP_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, SFA2_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, GPU2D_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, GPU3D_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, DCNANO_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, LPDDR4_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC5_RBASE, CSI_CLK_UI_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, CSI_CLK_ESC_PCC5_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_NO_RST_B }, + {PCC5_RBASE, RGPIOD_PCC5_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {} +}; + static int find_pcc_entry(int pcc_controller, int pcc_clk_slot, struct pcc_entry **out) { struct pcc_entry *pcc_array; @@ -150,6 +236,10 @@ static int find_pcc_entry(int pcc_controller, int pcc_clk_slot, struct pcc_entry pcc_array = pcc4_arrays; *out = &pcc4_arrays[0]; break; + case 5: + pcc_array = pcc5_arrays; + *out = &pcc5_arrays[0]; + break; default: printf("Not supported pcc_controller: %d\n", pcc_controller); return -EINVAL; @@ -199,12 +289,12 @@ int pcc_clock_enable(int pcc_controller, int pcc_clk_slot, bool enable) }

/* The clock source select needs clock is disabled */ -int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src) +int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc_clk src) { u32 val, i, clksrc_type; void __iomem *reg; struct pcc_entry *pcc_array; - enum cgc1_clk *cgc1_clk_array; + enum cgc_clk *cgc_clk_array; int clk;

clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array); @@ -221,18 +311,20 @@ int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src) }

if (pcc_controller == 3) - cgc1_clk_array = pcc3_clksrc[clksrc_type]; + cgc_clk_array = pcc3_clksrc[clksrc_type]; + else if (pcc_controller == 4) + cgc_clk_array = pcc4_clksrc[clksrc_type]; else - cgc1_clk_array = pcc4_clksrc[clksrc_type]; + cgc_clk_array = pcc5_clksrc[clksrc_type];

- for (i = 0; i < cgc1_clk_NUM; i++) { - if (cgc1_clk_array[i] == src) { + for (i = 0; i < cgc_clk_NUM; i++) { + if (cgc_clk_array[i] == src) { /* Find the clock src, then set it to PCS */ break; } }

- if (i == cgc1_clk_NUM) { + if (i == cgc_clk_NUM) { printf("No parent in PCS of PCC %d, invalid scg_clk %d\n", clk, src); return -EINVAL; } @@ -320,13 +412,13 @@ bool pcc_clock_is_enable(int pcc_controller, int pcc_clk_slot) return false; }

-int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *src) +int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc_clk *src) { u32 val, clksrc_type; void __iomem *reg; struct pcc_entry *pcc_array; int clk; - enum cgc1_clk *cgc1_clk_array; + enum cgc_clk *cgc_clk_array;

clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array); if (clk < 0) @@ -360,11 +452,13 @@ int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *sr }

if (pcc_controller == 3) - cgc1_clk_array = pcc3_clksrc[clksrc_type]; + cgc_clk_array = pcc3_clksrc[clksrc_type]; + else if (pcc_controller == 4) + cgc_clk_array = pcc4_clksrc[clksrc_type]; else - cgc1_clk_array = pcc4_clksrc[clksrc_type]; + cgc_clk_array = pcc5_clksrc[clksrc_type];

- *src = cgc1_clk_array[val]; + *src = cgc_clk_array[val];

debug("%s: parent cgc1 clk %d\n", __func__, *src);

@@ -412,7 +506,7 @@ u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot) { u32 val, rate, frac, div; void __iomem *reg; - enum cgc1_clk parent; + enum cgc_clk parent; int ret; int clk; struct pcc_entry *pcc_array; @@ -425,7 +519,7 @@ u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot) if (ret) return 0;

- rate = cgc1_clk_get_rate(parent); + rate = cgc_clk_get_rate(parent);

debug("%s: parent rate %u\n", __func__, rate);

From: Ye Li ye.li@nxp.com

Add the DSI clock enable and disable with PCC reset used. Add the LCD pixel clock calculation and configuration for DCNano

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8ulp/clock.h | 2 + arch/arm/mach-imx/imx8ulp/clock.c | 73 +++++++++++++++++++++++ 2 files changed, 75 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h index 58e3356e32..24322f3ab2 100644 --- a/arch/arm/include/asm/arch-imx8ulp/clock.h +++ b/arch/arm/include/asm/arch-imx8ulp/clock.h @@ -38,4 +38,6 @@ void init_clk_ddr(void); int set_ddr_clk(u32 phy_freq_mhz); void clock_init(void); void cgc1_enet_stamp_sel(u32 clk_src); +void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz); +void enable_mipi_dsi_clk(unsigned char enable); #endif diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 2beacbceb0..02e90f7856 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -317,6 +317,79 @@ int enable_usb_pll(ulong usb_phy_base) return 0; }

+void enable_mipi_dsi_clk(unsigned char enable) +{ + if (enable) { + pcc_clock_enable(5, DSI_PCC5_SLOT, false); + pcc_clock_sel(5, DSI_PCC5_SLOT, PLL4_PFD3_DIV2); + pcc_clock_div_config(5, DSI_PCC5_SLOT, 0, 6); + pcc_clock_enable(5, DSI_PCC5_SLOT, true); + pcc_reset_peripheral(5, DSI_PCC5_SLOT, false); + } else { + pcc_clock_enable(5, DSI_PCC5_SLOT, false); + pcc_reset_peripheral(5, DSI_PCC5_SLOT, true); + } +} + +void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) +{ + u8 pcd, best_pcd = 0; + u32 frac, rate, parent_rate, pfd, div; + u32 best_pfd = 0, best_frac = 0, best = 0, best_div = 0; + u32 pll4_rate; + + pcc_clock_enable(5, DCNANO_PCC5_SLOT, false); + + pll4_rate = cgc_clk_get_rate(PLL4); + pll4_rate = pll4_rate / 1000; /* Change to khz*/ + + debug("PLL4 rate %ukhz\n", pll4_rate); + + for (pfd = 12; pfd <= 35; pfd++) { + parent_rate = pll4_rate; + parent_rate = parent_rate * 18 / pfd; + + for (div = 1; div <= 64; div++) { + parent_rate = parent_rate / div; + + for (pcd = 0; pcd < 8; pcd++) { + for (frac = 0; frac < 2; frac++) { + if (pcd == 0 && frac == 1) + continue; + + rate = parent_rate * (frac + 1) / (pcd + 1); + if (rate > freq_in_khz) + continue; + + if (best == 0 || rate > best) { + best = rate; + best_pfd = pfd; + best_frac = frac; + best_pcd = pcd; + best_div = div; + } + } + } + } + } + + if (best == 0) { + printf("Can't find parent clock for LCDIF, target freq: %u\n", freq_in_khz); + return; + } + + debug("LCD target rate %ukhz, best rate %ukhz, frac %u, pcd %u, best_pfd %u, best_div %u\n", + freq_in_khz, best, best_frac, best_pcd, best_pfd, best_div); + + cgc2_pll4_pfd_config(PLL4_PFD0, best_pfd); + cgc2_pll4_pfddiv_config(PLL4_PFD0_DIV1, best_div - 1); + + pcc_clock_sel(5, DCNANO_PCC5_SLOT, PLL4_PFD0_DIV1); + pcc_clock_div_config(5, DCNANO_PCC5_SLOT, best_frac, best_pcd + 1); + pcc_clock_enable(5, DCNANO_PCC5_SLOT, true); + pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, false); +} + u32 mxc_get_clock(enum mxc_clock clk) { switch (clk) {

From: Ye Li ye.li@nxp.com

For singel boot, set flexspi0 mem to be accessed by A35

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8ulp/soc.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index e0574112cd..f64a8fb9fc 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -463,6 +463,8 @@ static int trdc_set_access(void) /* Iomuxc0: : PBridge1 slot 33 */ trdc_mbc_set_access(2, 7, 1, 33, false);

+ /* flexspi0 */ + trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false); return 0; }

From: Ye Li ye.li@nxp.com

The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and backlight. However the LPI2C0 and TPM0 are M33 resources, in this patch we simply access them, but this is a temporary solution. We will modify it when M33 FW changes to set MIPI DSI panel as default path and enable backlight after reset.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- .../include/asm/arch-imx8ulp/imx8ulp-pins.h | 4 ++ arch/arm/mach-imx/imx8ulp/clock.c | 6 ++ arch/arm/mach-imx/imx8ulp/soc.c | 5 ++ board/freescale/imx8ulp_evk/imx8ulp_evk.c | 56 +++++++++++++++++++ 4 files changed, 71 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h index d7c07f41b3..d0eefcbc92 100644 --- a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h +++ b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h @@ -9,6 +9,10 @@ #include <asm/arch/iomux.h>

enum { + IMX8ULP_PAD_PTA3__TPM0_CH2 = IOMUX_PAD(0x000c, 0x000c, IOMUX_CONFIG_MPORTS | 0x6, 0x0948, 0x1, 0), + IMX8ULP_PAD_PTA8__LPI2C0_SCL = IOMUX_PAD(0x0020, 0x0020, IOMUX_CONFIG_MPORTS | 0x5, 0x097c, 0x2, 0), + IMX8ULP_PAD_PTA9__LPI2C0_SDA = IOMUX_PAD(0x0024, 0x0024, IOMUX_CONFIG_MPORTS | 0x5, 0x0980, 0x2, 0), + IMX8ULP_PAD_PTB7__PMIC0_MODE2 = IOMUX_PAD(0x009C, 0x009C, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0), IMX8ULP_PAD_PTB8__PMIC0_MODE1 = IOMUX_PAD(0x00A0, 0x00A0, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0), IMX8ULP_PAD_PTB9__PMIC0_MODE0 = IOMUX_PAD(0x00A4, 0x00A4, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0), diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 02e90f7856..e599e6c4c6 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -186,6 +186,9 @@ int enable_i2c_clk(unsigned char enable, u32 i2c_num) LPI2C7_PCC4_SLOT << 8 | 4, };

+ if (i2c_num == 0) + return 0; + if (i2c_num < 4 || i2c_num > 7) return -EINVAL;

@@ -214,6 +217,9 @@ u32 imx_get_i2cclk(u32 i2c_num) LPI2C7_PCC4_SLOT << 8 | 4, };

+ if (i2c_num == 0) + return 24000000; + if (i2c_num < 4 || i2c_num > 7) return 0;

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index f64a8fb9fc..427b5e4117 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -465,6 +465,11 @@ static int trdc_set_access(void)

/* flexspi0 */ trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false); + + /* tpm0: PBridge1 slot 21 */ + trdc_mbc_set_access(2, 7, 1, 21, false); + /* lpi2c0: PBridge1 slot 24 */ + trdc_mbc_set_access(2, 7, 1, 24, false); return 0; }

diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c index 3ff4d43c99..1502e4dbb6 100644 --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -12,6 +12,7 @@ #include <asm/arch/sys_proto.h> #include <miiphy.h> #include <netdev.h> +#include <asm/gpio.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -48,11 +49,66 @@ int board_phy_config(struct phy_device *phydev) } #endif

+#define I2C_PAD_CTRL (PAD_CTL_ODE) +static const iomux_cfg_t lpi2c0_pads[] = { + IMX8ULP_PAD_PTA8__LPI2C0_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX8ULP_PAD_PTA9__LPI2C0_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), +}; + +#define TPM_PAD_CTRL (PAD_CTL_DSE) +static const iomux_cfg_t tpm0_pads[] = { + IMX8ULP_PAD_PTA3__TPM0_CH2 | MUX_PAD_CTRL(TPM_PAD_CTRL), +}; + +void mipi_dsi_mux_panel(void) +{ + int ret; + struct gpio_desc desc; + + /* It is temp solution to directly access i2c, need change to rpmsg later */ + + /* enable lpi2c0 clock and iomux */ + imx8ulp_iomux_setup_multiple_pads(lpi2c0_pads, ARRAY_SIZE(lpi2c0_pads)); + writel(0xD2000000, 0x28091060); + + ret = dm_gpio_lookup_name("gpio@20_9", &desc); + if (ret) { + printf("%s lookup gpio@20_9 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "dsi_mux"); + if (ret) { + printf("%s request dsi_mux failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +void mipi_dsi_panel_backlight(void) +{ + /* It is temp solution to directly access pwm, need change to rpmsg later */ + imx8ulp_iomux_setup_multiple_pads(tpm0_pads, ARRAY_SIZE(tpm0_pads)); + writel(0xD4000001, 0x28091054); + + /* Use center-aligned PWM mode, CPWMS=1, MSnB:MSnA = 10, ELSnB:ELSnA = 00 */ + writel(1000, 0x28095018); + writel(1000, 0x28095034); /* MOD = CV, full duty */ + writel(0x28, 0x28095010); + writel(0x20, 0x28095030); +} + int board_init(void) { if (IS_ENABLED(CONFIG_FEC_MXC)) setup_fec();

+ if (IS_ENABLED(CONFIG_DM_VIDEO)) { + mipi_dsi_mux_panel(); + mipi_dsi_panel_backlight(); + } + return 0; }

From: Ye Li ye.li@nxp.com

To avoid DCNANO underrun issue on high loading test, set its read Qos on NIC_LPAV to highest

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8ulp/soc.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 427b5e4117..0cf4765bd6 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -485,6 +485,9 @@ void lpav_configure(void) writel(0x1f, SIM_SEC_BASE_ADDR + 0x50); writel(0xffffffff, SIM_SEC_BASE_ADDR + 0x54); writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58); + + /* Set read QoS of dcnano on LPAV NIC */ + writel(0xf, 0x2e447100); }

int arch_cpu_init(void)

From: Ye Li ye.li@nxp.com

The setting does not have effect because we should set it after power on the PS16 for NIC AV.

So move it after upower_init which has powered on all PS

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 + arch/arm/mach-imx/imx8ulp/soc.c | 3 +++ board/freescale/imx8ulp_evk/spl.c | 3 +++ 3 files changed, 7 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index 1a142dce72..8e2c6ed0ce 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -16,4 +16,5 @@ enum bt_mode get_boot_mode(void); int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm); int xrdc_config_pdac_openacc(u32 bridge, u32 index); enum boot_device get_boot_device(void); +void set_lpav_qos(void); #endif diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 0cf4765bd6..2348132bf7 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -485,7 +485,10 @@ void lpav_configure(void) writel(0x1f, SIM_SEC_BASE_ADDR + 0x50); writel(0xffffffff, SIM_SEC_BASE_ADDR + 0x54); writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58); +}

+void set_lpav_qos(void) +{ /* Set read QoS of dcnano on LPAV NIC */ writel(0xf, 0x2e447100); } diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index faece336ef..42f8e262b6 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -90,6 +90,9 @@ void spl_board_init(void)

/* Init XRDC MRC for VIDEO, DSP domains */ xrdc_init_mrc(); + + /* Call it after PS16 power up */ + set_lpav_qos(); }

void board_init_f(ulong dummy)

From: Ye Li ye.li@nxp.com

Remove the freescale vendor name from CPU revision print to align with other i.MX platforms

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8ulp/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 2348132bf7..d9dca21e8c 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -211,7 +211,7 @@ int print_cpuinfo(void)

cpurev = get_cpu_rev();

- printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", + printf("CPU: i.MX%s rev%d.%d at %d MHz\n", get_imx_type((cpurev & 0xFF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000);

From: Ye Li ye.li@nxp.com

8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0 LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision.

A0.2 will fix the issue in ROM. But A0.1 we have to workaround it in SPL by setting LPOSCCTRL BIASCURRENT again.

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 + arch/arm/mach-imx/imx8ulp/soc.c | 20 +++++++++++++++++++ board/freescale/imx8ulp_evk/spl.c | 6 ++++++ 3 files changed, 27 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index 8e2c6ed0ce..284ccafc98 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -17,4 +17,5 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm); int xrdc_config_pdac_openacc(u32 bridge, u32 index); enum boot_device get_boot_device(void); void set_lpav_qos(void); +void load_lposc_fuse(void); #endif diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index d9dca21e8c..e12e28d9e7 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -487,6 +487,26 @@ void lpav_configure(void) writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58); }

+void load_lposc_fuse(void) +{ + int ret; + u32 val = 0, val2 = 0, reg; + + ret = fuse_read(25, 0, &val); + if (ret) + return; /* failed */ + + ret = fuse_read(25, 1, &val2); + if (ret) + return; /* failed */ + + /* LPOSCCTRL */ + reg = readl(0x2802f304); + reg &= ~0xff; + reg |= (val & 0xff); + writel(reg, 0x2802f304); +} + void set_lpav_qos(void) { /* Set read QoS of dcnano on LPAV NIC */ diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index 42f8e262b6..c17d5eff7d 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -77,6 +77,12 @@ void spl_board_init(void)

/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */

+ /* Load the lposc fuse for single boot to work around ROM issue, + * The fuse depends on S400 to read. + */ + if (is_soc_rev(CHIP_REV_1_0) && get_boot_mode() == SINGLE_BOOT) + load_lposc_fuse(); + upower_init();

power_init_board();

From: Ye Li ye.li@nxp.com

The LPAV is not allocated to APD when dual boot, so LPAV won't reset when APD is reset. We have to explicitly reset the DDR, otherwise its initialization will fail.

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8ulp/clock.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index e599e6c4c6..f54fc25763 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -97,6 +97,9 @@ void ddrphy_pll_lock(void)

void init_clk_ddr(void) { + /* disable the ddr pcc */ + writel(0xc0000000, PCC5_LPDDR4_ADDR); + /* enable pll4 and ddrclk*/ cgc2_pll4_init(); cgc2_ddrclk_config(1, 1);

From: Ye Li ye.li@nxp.com

When LPAV is allocated to RTD, the LPAV won't be reset. So we have to reset DCNano and MIPI DSI in u-boot before enabling the drivers

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8ulp/clock.h | 1 + arch/arm/mach-imx/imx8ulp/clock.c | 8 ++++++++ 2 files changed, 9 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h index 24322f3ab2..cc70284f55 100644 --- a/arch/arm/include/asm/arch-imx8ulp/clock.h +++ b/arch/arm/include/asm/arch-imx8ulp/clock.h @@ -39,5 +39,6 @@ int set_ddr_clk(u32 phy_freq_mhz); void clock_init(void); void cgc1_enet_stamp_sel(u32 clk_src); void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz); +void reset_lcdclk(void); void enable_mipi_dsi_clk(unsigned char enable); #endif diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index f54fc25763..d03269ac04 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -330,6 +330,7 @@ void enable_mipi_dsi_clk(unsigned char enable) { if (enable) { pcc_clock_enable(5, DSI_PCC5_SLOT, false); + pcc_reset_peripheral(5, DSI_PCC5_SLOT, true); pcc_clock_sel(5, DSI_PCC5_SLOT, PLL4_PFD3_DIV2); pcc_clock_div_config(5, DSI_PCC5_SLOT, 0, 6); pcc_clock_enable(5, DSI_PCC5_SLOT, true); @@ -340,6 +341,13 @@ void enable_mipi_dsi_clk(unsigned char enable) } }

+void reset_lcdclk(void) +{ + /* Disable clock and reset dcnano*/ + pcc_clock_enable(5, DCNANO_PCC5_SLOT, false); + pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, true); +} + void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) { u8 pcd, best_pcd = 0;

From: Ye Li ye.li@nxp.com

Get the MAC address from fuse bank5 word 3 and 4. It has MSB first at lowest address, so have a reverse order with other iMX used in mac.c

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8ulp/soc.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index e12e28d9e7..943ea7fb7e 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -588,7 +588,30 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)

void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { + u32 val[2] = {}; + int ret; + + ret = fuse_read(5, 3, &val[0]); + if (ret) + goto err; + + ret = fuse_read(5, 4, &val[1]); + if (ret) + goto err; + + mac[0] = val[0]; + mac[1] = val[0] >> 8; + mac[2] = val[0] >> 16; + mac[3] = val[0] >> 24; + mac[4] = val[1]; + mac[5] = val[1] >> 8; + + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return; +err: memset(mac, 0, 6); + printf("%s: fuse read err: %d\n", __func__, ret); }

int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc;

From: Alice Guo alice.guo@nxp.com

This patch implements enable_adc1_clk() to enable or disable the ADC1 clock on i.MX8ULP.

Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Alice Guo alice.guo@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8ulp/cgc.h | 4 +++ arch/arm/include/asm/arch-imx8ulp/clock.h | 1 + arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 1 + arch/arm/include/asm/arch-imx8ulp/pcc.h | 4 +++ arch/arm/mach-imx/imx8ulp/clock.c | 12 +++++++++ arch/arm/mach-imx/imx8ulp/pcc.c | 28 +++++++++++++++++++- 6 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h index 745fd7f5e8..e15ef1d6c1 100644 --- a/arch/arm/include/asm/arch-imx8ulp/cgc.h +++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h @@ -56,6 +56,10 @@ enum cgc_clk { PLL4_PFD2_DIV2, PLL4_PFD3_DIV1, PLL4_PFD3_DIV2, + CM33_BUSCLK, + PLL1_VCO_DIV, + PLL0_PFD2_DIV, + PLL0_PFD1_DIV, };

struct cgc1_regs { diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h index cc70284f55..c0f32cc087 100644 --- a/arch/arm/include/asm/arch-imx8ulp/clock.h +++ b/arch/arm/include/asm/arch-imx8ulp/clock.h @@ -41,4 +41,5 @@ void cgc1_enet_stamp_sel(u32 clk_src); void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz); void reset_lcdclk(void); void enable_mipi_dsi_clk(unsigned char enable); +void enable_adc1_clk(bool enable); #endif diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h index af6845cbff..91adc85525 100644 --- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h @@ -30,6 +30,7 @@

#define PCC_XRDC_MGR_ADDR 0x292d00bc

+#define PCC1_RBASE 0x28091000 #define PCC3_RBASE 0x292d0000 #define PCC4_RBASE 0x29800000 #define PCC5_RBASE 0x2da70000 diff --git a/arch/arm/include/asm/arch-imx8ulp/pcc.h b/arch/arm/include/asm/arch-imx8ulp/pcc.h index 468015482b..46386f1aba 100644 --- a/arch/arm/include/asm/arch-imx8ulp/pcc.h +++ b/arch/arm/include/asm/arch-imx8ulp/pcc.h @@ -8,6 +8,10 @@

#include <asm/arch/cgc.h>

+enum pcc1_entry { + ADC1_PCC1_SLOT = 34, +}; + enum pcc3_entry { DMA1_MP_PCC3_SLOT = 1, DMA1_CH0_PCC3_SLOT = 2, diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index d03269ac04..961702310c 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -341,6 +341,18 @@ void enable_mipi_dsi_clk(unsigned char enable) } }

+void enable_adc1_clk(bool enable) +{ + if (enable) { + pcc_clock_enable(1, ADC1_PCC1_SLOT, false); + pcc_clock_sel(1, ADC1_PCC1_SLOT, CM33_BUSCLK); + pcc_clock_enable(1, ADC1_PCC1_SLOT, true); + pcc_reset_peripheral(1, ADC1_PCC1_SLOT, false); + } else { + pcc_clock_enable(1, ADC1_PCC1_SLOT, false); + } +} + void reset_lcdclk(void) { /* Disable clock and reset dcnano*/ diff --git a/arch/arm/mach-imx/imx8ulp/pcc.c b/arch/arm/mach-imx/imx8ulp/pcc.c index 6145b3ea6a..7909d770af 100644 --- a/arch/arm/mach-imx/imx8ulp/pcc.c +++ b/arch/arm/mach-imx/imx8ulp/pcc.c @@ -15,6 +15,21 @@ #define cgc_clk_TYPES 2 #define cgc_clk_NUM 8

+static enum cgc_clk pcc1_clksrc[][8] = { + { + }, + { + DUMMY0_CLK, + LPOSC, + SOSC_DIV2, + FRO_DIV2, + CM33_BUSCLK, + PLL1_VCO_DIV, + PLL0_PFD2_DIV, + PLL0_PFD1_DIV, + } +}; + static enum cgc_clk pcc3_clksrc[][8] = { { }, @@ -75,6 +90,11 @@ static enum cgc_clk pcc5_clksrc[][8] = { } };

+static struct pcc_entry pcc1_arrays[] = { + {PCC1_RBASE, ADC1_PCC1_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV, PCC_HAS_RST_B}, + {} +}; + static struct pcc_entry pcc3_arrays[] = { {PCC3_RBASE, DMA1_MP_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, {PCC3_RBASE, DMA1_CH0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, @@ -228,6 +248,10 @@ static int find_pcc_entry(int pcc_controller, int pcc_clk_slot, struct pcc_entry int index = 0;

switch (pcc_controller) { + case 1: + pcc_array = pcc1_arrays; + *out = &pcc1_arrays[0]; + break; case 3: pcc_array = pcc3_arrays; *out = &pcc3_arrays[0]; @@ -310,7 +334,9 @@ int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc_clk src) return -EPERM; }

- if (pcc_controller == 3) + if (pcc_controller == 1) + cgc_clk_array = pcc1_clksrc[clksrc_type]; + else if (pcc_controller == 3) cgc_clk_array = pcc3_clksrc[clksrc_type]; else if (pcc_controller == 4) cgc_clk_array = pcc4_clksrc[clksrc_type];

From: Ye Li ye.li@nxp.com

The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW according to DDR DIV updating or DDR CLK halt status change. So DDR PCC disable/enable will trigger the lock up/down flow. We need wait until unlock to ensure clock is ready.

And before configuring the DDRCLK DIV, we need polling the DDRLOCKED until it is unlocked. Otherwise writing ti DIV bits will not set.

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8ulp/cgc.h | 1 + arch/arm/mach-imx/imx8ulp/cgc.c | 11 +++++++++++ arch/arm/mach-imx/imx8ulp/clock.c | 6 ++++++ 3 files changed, 18 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h index e15ef1d6c1..ad3edc85ad 100644 --- a/arch/arm/include/asm/arch-imx8ulp/cgc.h +++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h @@ -152,6 +152,7 @@ void cgc1_soscdiv_init(void); void cgc1_init_core_clk(void); void cgc2_pll4_init(void); void cgc2_ddrclk_config(u32 src, u32 div); +void cgc2_ddrclk_wait_unlock(void); u32 cgc1_sosc_div(enum cgc_clk clk); void cgc1_enet_stamp_sel(u32 clk_src); void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd); diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index fc84f3f293..38bcbb91e6 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -269,12 +269,23 @@ void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div)

void cgc2_ddrclk_config(u32 src, u32 div) { + /* If reg lock is set, wait until unlock by HW */ + /* This lock is triggered by div updating and ddrclk halt status change, */ + while ((readl(&cgc2_regs->ddrclk) & BIT(31))) + ; + writel((src << 28) | (div << 21), &cgc2_regs->ddrclk); /* wait for DDRCLK switching done */ while (!(readl(&cgc2_regs->ddrclk) & BIT(27))) ; }

+void cgc2_ddrclk_wait_unlock(void) +{ + while ((readl(&cgc2_regs->ddrclk) & BIT(31))) + ; +} + void cgc2_lpav_init(enum cgc_clk clk) { u32 i, scs, reg; diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 961702310c..91580b2c29 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -107,6 +107,9 @@ void init_clk_ddr(void) /* enable ddr pcc */ writel(0xd0000000, PCC5_LPDDR4_ADDR);

+ /* Wait until ddrclk reg lock bit is cleared, so that the div update is finished */ + cgc2_ddrclk_wait_unlock(); + /* for debug */ /* setclkout_ddr(); */ } @@ -144,6 +147,9 @@ int set_ddr_clk(u32 phy_freq_mhz) return -EINVAL; }

+ /* Wait until ddrclk reg lock bit is cleared, so that the div update is finished */ + cgc2_ddrclk_wait_unlock(); + return 0; }

From: Alice Guo alice.guo@nxp.com

Obatin the SoC current temperature in print_cpuinfo().

Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Alice Guo alice.guo@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8ulp/soc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 943ea7fb7e..934b0ef038 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -24,6 +24,7 @@ #include <dm/device.h> #include <dm/uclass-internal.h> #include <fuse.h> +#include <thermal.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -216,6 +217,22 @@ int print_cpuinfo(void) (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000);

+#if defined(CONFIG_IMX_PMC_TEMPERATURE) + struct udevice *udev; + int ret, temp; + + ret = uclass_get_device(UCLASS_THERMAL, 0, &udev); + if (!ret) { + ret = thermal_get_temp(udev, &temp); + if (!ret) + printf("CPU current temperature: %d\n", temp); + else + debug(" - failed to get CPU current temperature\n"); + } else { + debug(" - failed to get CPU current temperature\n"); + } +#endif + printf("Reset cause: %s\n", get_reset_cause(cause));

printf("Boot mode: ");

From: Jacky Bai ping.bai@nxp.com

On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP.

Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Jacky Bai ping.bai@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/ddr/imx/imx8ulp/Kconfig | 7 +++++ drivers/ddr/imx/imx8ulp/ddr_init.c | 45 ++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+)

diff --git a/drivers/ddr/imx/imx8ulp/Kconfig b/drivers/ddr/imx/imx8ulp/Kconfig index e56062a1d0..42848863aa 100644 --- a/drivers/ddr/imx/imx8ulp/Kconfig +++ b/drivers/ddr/imx/imx8ulp/Kconfig @@ -8,4 +8,11 @@ config IMX8ULP_DRAM_PHY_PLL_BYPASS bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK " depends on IMX8ULP_DRAM

+config SAVED_DRAM_TIMING_BASE + hex "Define the base address for saved dram timing" + help + The DRAM config timing data need to be saved into sram + for low power use. + default 0x2006c000 + endmenu diff --git a/drivers/ddr/imx/imx8ulp/ddr_init.c b/drivers/ddr/imx/imx8ulp/ddr_init.c index 16aaf56103..9730dd6450 100644 --- a/drivers/ddr/imx/imx8ulp/ddr_init.c +++ b/drivers/ddr/imx/imx8ulp/ddr_init.c @@ -178,6 +178,48 @@ int ddr_calibration(unsigned int fsp_table[3]) return 0; }

+static void save_dram_config(struct dram_timing_info2 *timing_info, unsigned long saved_timing_base) +{ + int i = 0; + struct dram_timing_info2 *saved_timing = (struct dram_timing_info2 *)saved_timing_base; + struct dram_cfg_param *cfg; + + saved_timing->ctl_cfg_num = timing_info->ctl_cfg_num; + saved_timing->phy_f1_cfg_num = timing_info->phy_f1_cfg_num; + saved_timing->phy_f2_cfg_num = timing_info->phy_f2_cfg_num; + + /* save the fsp table */ + for (i = 0; i < 3; i++) + saved_timing->fsp_table[i] = timing_info->fsp_table[i]; + + cfg = (struct dram_cfg_param *)(saved_timing_base + + sizeof(*timing_info)); + + /* save ctl config */ + saved_timing->ctl_cfg = cfg; + for (i = 0; i < timing_info->ctl_cfg_num; i++) { + cfg->reg = timing_info->ctl_cfg[i].reg; + cfg->val = timing_info->ctl_cfg[i].val; + cfg++; + } + + /* save phy f1 config */ + saved_timing->phy_f1_cfg = cfg; + for (i = 0; i < timing_info->phy_f1_cfg_num; i++) { + cfg->reg = timing_info->phy_f1_cfg[i].reg; + cfg->val = timing_info->phy_f1_cfg[i].val; + cfg++; + } + + /* save phy f2 config */ + saved_timing->phy_f2_cfg = cfg; + for (i = 0; i < timing_info->phy_f2_cfg_num; i++) { + cfg->reg = timing_info->phy_f2_cfg[i].reg; + cfg->val = timing_info->phy_f2_cfg[i].val; + cfg++; + } +} + int ddr_init(struct dram_timing_info2 *dram_timing) { int i; @@ -192,6 +234,9 @@ int ddr_init(struct dram_timing_info2 *dram_timing) clrbits_le32(AVD_SIM_BASE_ADDR, 0x1); /* SIM_DDR_CTRL_DIV2_EN */ }

+ /* save the dram config into sram for low power mode */ + save_dram_config(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); + /* Initialize CTL registers */ for (i = 0; i < dram_timing->ctl_cfg_num; i++) writel(dram_timing->ctl_cfg[i].val, (ulong)dram_timing->ctl_cfg[i].reg);

From: Ye Li ye.li@nxp.com

After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used.

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/ddr/imx/imx8ulp/ddr_init.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/ddr/imx/imx8ulp/ddr_init.c b/drivers/ddr/imx/imx8ulp/ddr_init.c index 9730dd6450..a5a9fd8d7c 100644 --- a/drivers/ddr/imx/imx8ulp/ddr_init.c +++ b/drivers/ddr/imx/imx8ulp/ddr_init.c @@ -129,8 +129,8 @@ int ddr_calibration(unsigned int fsp_table[3]) * Polling SIM LPDDR_CTRL2 Bit phy_freq_chg_req until be 1'b1 */ reg_val = readl(AVD_SIM_LPDDR_CTRL2); - phy_freq_req = (reg_val >> 7) & 0x1; - + /* DFS interrupt is set */ + phy_freq_req = ((reg_val >> 7) & 0x1) && ((reg_val >> 15) & 0x1); if (phy_freq_req) { phy_freq_type = reg_val & 0x1F; if (phy_freq_type == 0x00) { @@ -159,7 +159,11 @@ int ddr_calibration(unsigned int fsp_table[3]) if (freq_chg_pt == 2) freq_chg_cnt--; } - reg_val = readl(AVD_SIM_LPDDR_CTRL2); + + /* Hardware clear the ack on falling edge of LPDDR_CTRL2:phy_freq_chg_reg */ + /* Ensure the ack is clear before starting to poll request again */ + while ((readl(AVD_SIM_LPDDR_CTRL2) & BIT(6))) + ; } } while (1);