From: Stephen Warren swarren@nvidia.com

On Tegra186, it is necessary to perform an SMC to fully flush all caches; flushing/cleaning by set/way is not enough. Implement the required hook to make this happen.

Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/tegra186/Makefile | 1 + arch/arm/mach-tegra/tegra186/cache.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 arch/arm/mach-tegra/tegra186/cache.c

diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile index 26bc462930c1..56f3378ecea3 100644 --- a/arch/arm/mach-tegra/tegra186/Makefile +++ b/arch/arm/mach-tegra/tegra186/Makefile @@ -3,6 +3,7 @@ # SPDX-License-Identifier: GPL-2.0

obj-y += ../board186.o +obj-y += cache.o obj-y += nvtboot_board.o obj-y += nvtboot_ll.o obj-y += nvtboot_mem.o diff --git a/arch/arm/mach-tegra/tegra186/cache.c b/arch/arm/mach-tegra/tegra186/cache.c new file mode 100644 index 000000000000..adaed8968eb9 --- /dev/null +++ b/arch/arm/mach-tegra/tegra186/cache.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/system.h> + +#define SMC_SIP_INVOKE_MCE 0x82FFFF00 +#define MCE_SMC_ROC_FLUSH_CACHE 11 + +int __asm_flush_l3_cache(void) +{ + struct pt_regs regs = {0}; + + isb(); + + regs.regs[0] = SMC_SIP_INVOKE_MCE | MCE_SMC_ROC_FLUSH_CACHE; + smc_call(&regs); + + return 0; +}