On Wednesday 23 April 2008, Andrew E. Mileski wrote:

This affects EBC_BXCR_BW_32BIT defined in include/ppc440.h

According to the AMCC 440EPx User Manual (v1.14), pg 591, figure 22-18, BW (bits 17:18) should be 10 for a 32-bit bus width. This is also repeated for the NAND controller, section 23.4.5 on pg 600.

According to the IBM 440GX User's Manual (November 21, 2003), pg 1037, figure 30-23, BW (bits 17:18) should be 11. A rather old manual.

Can others help confirm the settings for these processors and other 440 family members.

I suspect that both manuals are correct and the register bit setting are incompatible. Best would be if you send a patch to fix this in U-Boot. Something like:

#if defined(CONFIG_440GX) #define EBC_BXCR_BW_32BIT 0x00006000 #else #define EBC_BXCR_BW_32BIT 0x00004000 #endif

Thanks.

Best regards, Stefan

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