[U-Boot] [PATCH 0/4] cl-som-imx7: initial support
This patch series adds support for CompuLab CL-SOM-iMX7, SBC-iMX7, SBC-IOT-iMX7 and IOT-GATE-iMX7.
CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on NXP i.MX7 processor family.
SBC-iMX7 is a single board computer, implemented with the CL-SOM-iMX7 module and the SB-SOM-iMX7 carrier board. The CL-SOM-iMX7 providing most of the functions and the SB-SOM-iMX7 providing additional peripheral functions and connectors.
SBC-IOT-iMX7 is a internet of things single board computer, implemented with the CL-SOM-iMX7 module and the SB-IOT-iMX7 carrier board. The CL-SOM-iMX7 providing most of the functions and the SB-IOT-iMX7 providing additional peripheral functions and connectors.
The CL-SOM-iMX7 has the following features:
CPU: NXP (Freescale) i.MX 7Dual ARM Cortex-A7, 1GHz processor (dual-core) or NXP (Freescale) i.MX 7Solo ARM Cortex-A7, 800MHz processor (single-core)
RAM: 256MB – 2GB, DDR3L-1066
Storage: SLC NAND flash, 128MB - 1GB or eMMC flash, 4GB - 32GB
Ethernet: Up to 2x 10/100/1000Mbps Ethernet ports (MAC+PHY)
WiFi: 802.11b/g/n WiFi interface (TI WiLink 8 WL1801 chipset) or Dual-band 2x2 802.11a/b/g/n WiFi interface (TI WiLink 8 WL1837 chipset)
Bluetooth: Bluetooth 4.1 BLE
Analog Audio: Audio codec with stereo output, stereo input and microphone support
Digital Audio: I2S compliant digital audio interface, MQS audio interface
Display: Parallel 24-bit display interface, up to 1920 x 1080 @60Hz, LVDS, up to 1400 x 1050 @60Hz MIPI-DSI, 2 data lanes, up to 1400 x 1050 @60Hz
More details can be found here:
http://www.compulab.com/products/computer-on-modules/cl-som-imx7-freescale-i...
http://www.compulab.com/products/sbcs/sbc-imx7-freescale-i-mx-7-single-board...
http://www.compulab.com/products/sbcs/sbc-iot-imx7-nxp-i-mx-7-internet-of-th...
http://www.compulab.com/products/iot-gateways/iot-gate-imx7-nxp-i-mx-7-inter...
Ilya Ledvich (1): arm: imx7d: add support for Compulab cl-som-imx7
Uri Mashiach (3): imx: mx7: fix the CCM_ macros imx: mx7: DDR controller configuration for the i.MX7 architecture imx: mx7: SPL support for i.MX7
arch/arm/include/asm/arch-mx7/crm_regs.h | 51 ++--- arch/arm/include/asm/arch-mx7/imx-regs.h | 2 + arch/arm/include/asm/arch-mx7/mx7-ddr.h | 155 ++++++++++++++ arch/arm/include/asm/arch-mx7/sys_proto.h | 1 + arch/arm/mach-imx/mx7/Kconfig | 8 + arch/arm/mach-imx/mx7/Makefile | 2 +- arch/arm/mach-imx/mx7/ddr.c | 201 ++++++++++++++++++ arch/arm/mach-imx/spl.c | 23 ++- board/compulab/cl-som-imx7/Kconfig | 28 +++ board/compulab/cl-som-imx7/MAINTAINERS | 6 + board/compulab/cl-som-imx7/Makefile | 17 ++ board/compulab/cl-som-imx7/cl-som-imx7.c | 331 ++++++++++++++++++++++++++++++ board/compulab/cl-som-imx7/common.c | 46 +++++ board/compulab/cl-som-imx7/common.h | 32 +++ board/compulab/cl-som-imx7/mux.c | 142 +++++++++++++ board/compulab/cl-som-imx7/spl.c | 211 +++++++++++++++++++ configs/cl-som-imx7_defconfig | 54 +++++ include/configs/cl-som-imx7.h | 192 +++++++++++++++++ include/configs/imx7_spl.h | 67 ++++++ 19 files changed, 1544 insertions(+), 25 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx7/mx7-ddr.h create mode 100644 arch/arm/mach-imx/mx7/ddr.c create mode 100644 board/compulab/cl-som-imx7/Kconfig create mode 100644 board/compulab/cl-som-imx7/MAINTAINERS create mode 100644 board/compulab/cl-som-imx7/Makefile create mode 100644 board/compulab/cl-som-imx7/cl-som-imx7.c create mode 100644 board/compulab/cl-som-imx7/common.c create mode 100644 board/compulab/cl-som-imx7/common.h create mode 100644 board/compulab/cl-som-imx7/mux.c create mode 100644 board/compulab/cl-som-imx7/spl.c create mode 100644 configs/cl-som-imx7_defconfig create mode 100644 include/configs/cl-som-imx7.h create mode 100644 include/configs/imx7_spl.h
The CCM_ macros use the CCM_BASE_ADDRESS macro, which doesn't exist. Replace the CCM_BASE_ADDRESS macros with CCM_BASE_ADDR.
Signed-off-by: Uri Mashiach uri.mashiach@compulab.co.il Acked-by: Igor Grinberg grinberg@compulab.co.il --- arch/arm/include/asm/arch-mx7/crm_regs.h | 46 ++++++++++++++++---------------- 1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h index d65d4d9..e54a254 100644 --- a/arch/arm/include/asm/arch-mx7/crm_regs.h +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -2000,29 +2000,29 @@ struct mxc_ccm_anatop_reg { #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK)
-#define CCM_GPR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i)) -#define CCM_OBSERVE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i)) -#define CCM_SCTRL(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i)) -#define CCM_CCGR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i)) -#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i)) - -#define CCM_GPR_SET(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4) -#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4) -#define CCM_SCTRL_SET(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4) -#define CCM_CCGR_SET(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4) -#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4) - -#define CCM_GPR_CLR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 8) -#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8) -#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8) -#define CCM_CCGR_CLR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 8) -#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8) - -#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 12) -#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12) -#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12) -#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 12) -#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12) +#define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i)) +#define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i)) +#define CCM_SCTRL(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i)) +#define CCM_CCGR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i)) +#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i)) + +#define CCM_GPR_SET(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 4) +#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4) +#define CCM_SCTRL_SET(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4) +#define CCM_CCGR_SET(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 4) +#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4) + +#define CCM_GPR_CLR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 8) +#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8) +#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8) +#define CCM_CCGR_CLR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 8) +#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8) + +#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 12) +#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12) +#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12) +#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 12) +#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
#define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i)) #define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i))
The configuration files imximage.cfg are used for the DDR controller configuration. Add DDR configuration function to replace the DDR controller configuration in the imximage.cfg file. The function can be used for DDR size detection.
Signed-off-by: Uri Mashiach uri.mashiach@compulab.co.il --- arch/arm/include/asm/arch-mx7/crm_regs.h | 5 + arch/arm/include/asm/arch-mx7/imx-regs.h | 2 + arch/arm/include/asm/arch-mx7/mx7-ddr.h | 155 ++++++++++++++++++++++++ arch/arm/mach-imx/mx7/Makefile | 2 +- arch/arm/mach-imx/mx7/ddr.c | 201 +++++++++++++++++++++++++++++++ 5 files changed, 364 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-mx7/mx7-ddr.h create mode 100644 arch/arm/mach-imx/mx7/ddr.c
diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h index e54a254..611190e 100644 --- a/arch/arm/include/asm/arch-mx7/crm_regs.h +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -2055,6 +2055,11 @@ struct mxc_ccm_anatop_reg { #define HW_CCM_ROOT_TARGET_TOGGLE(i, v) writel((v), CCM_ROOT_TARGET_TOGGLE(i))
#define CCM_CLK_ON_MSK 0x03 +#define CCM_CLK_ON_N_N 0x00 /* Domain clocks not needed */ +#define CCM_CLK_ON_R_W 0x02 /* Domain clocks needed when in RUN and WAIT */ + +/* CCGR Mapping */ +#define CCGR_IDX_DDR 19 /* CCM_CCGR19 */
#define CCM_ROOT_TGT_POST_DIV_SHIFT 0 #define CCM_ROOT_TGT_PRE_DIV_SHIFT 15 diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index aab3a9a..f0693f9 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -268,6 +268,8 @@ struct src { #define SRC_M4RCR_M4C_NON_SCLR_RST_MASK (1 << 0) #define SRC_M4RCR_ENABLE_M4_OFFSET 3 #define SRC_M4RCR_ENABLE_M4_MASK (1 << 3) +#define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1 +#define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1)
/* GPR0 Bit Fields */ #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u diff --git a/arch/arm/include/asm/arch-mx7/mx7-ddr.h b/arch/arm/include/asm/arch-mx7/mx7-ddr.h new file mode 100644 index 0000000..3a4841c --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/mx7-ddr.h @@ -0,0 +1,155 @@ +/* + * DDR controller registers of the i.MX7 architecture + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach uri.mashiach@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX7_DDR_H__ +#define __ASM_ARCH_MX7_DDR_H__ + +/* DDRC Registers (DDRC_IPS_BASE_ADDR) */ +struct ddrc { + u32 mstr; /* 0x0000 */ + u32 reserved1[0x18]; + u32 rfshtmg; /* 0x0064 */ + u32 reserved2[0x1a]; + u32 init0; /* 0x00d0 */ + u32 init1; /* 0x00d4 */ + u32 reserved3; + u32 init3; /* 0x00dc */ + u32 init4; /* 0x00e0 */ + u32 init5; /* 0x00e4 */ + u32 reserved4[0x03]; + u32 rankctl; /* 0x00f4 */ + u32 reserved5[0x02]; + u32 dramtmg0; /* 0x0100 */ + u32 dramtmg1; /* 0x0104 */ + u32 dramtmg2; /* 0x0108 */ + u32 dramtmg3; /* 0x010c */ + u32 dramtmg4; /* 0x0110 */ + u32 dramtmg5; /* 0x0114 */ + u32 reserved6[0x02]; + u32 dramtmg8; /* 0x0120 */ + u32 reserved7[0x17]; + u32 zqctl0; /* 0x0180 */ + u32 reserved8[0x03]; + u32 dfitmg0; /* 0x0190 */ + u32 dfitmg1; /* 0x0194 */ + u32 reserved9[0x02]; + u32 dfiupd0; /* 0x01a0 */ + u32 dfiupd1; /* 0x01a4 */ + u32 dfiupd2; /* 0x01a8 */ + u32 reserved10[0x15]; + u32 addrmap0; /* 0x0200 */ + u32 addrmap1; /* 0x0204 */ + u32 addrmap2; /* 0x0208 */ + u32 addrmap3; /* 0x020c */ + u32 addrmap4; /* 0x0210 */ + u32 addrmap5; /* 0x0214 */ + u32 addrmap6; /* 0x0218 */ + u32 reserved12[0x09]; + u32 odtcfg; /* 0x0240 */ + u32 odtmap; /* 0x0244 */ +}; + +/* DDRC_MSTR fields */ +#define MSTR_DATA_BUS_WIDTH_MASK 0x3 << 12 +#define MSTR_DATA_BUS_WIDTH_SHIFT 12 +#define MSTR_DATA_ACTIVE_RANKS_MASK 0xf << 24 +#define MSTR_DATA_ACTIVE_RANKS_SHIFT 24 +/* DDRC_ADDRMAP1 fields */ +#define ADDRMAP1_BANK_B0_MASK 0x1f << 0 +#define ADDRMAP1_BANK_B0_SHIFT 0 +#define ADDRMAP1_BANK_B1_MASK 0x1f << 8 +#define ADDRMAP1_BANK_B1_SHIFT 8 +#define ADDRMAP1_BANK_B2_MASK 0x1f << 16 +#define ADDRMAP1_BANK_B2_SHIFT 16 +/* DDRC_ADDRMAP2 fields */ +#define ADDRMAP2_COL_B2_MASK 0xF << 0 +#define ADDRMAP2_COL_B2_SHIFT 0 +#define ADDRMAP2_COL_B3_MASK 0xF << 8 +#define ADDRMAP2_COL_B3_SHIFT 8 +#define ADDRMAP2_COL_B4_MASK 0xF << 16 +#define ADDRMAP2_COL_B4_SHIFT 16 +#define ADDRMAP2_COL_B5_MASK 0xF << 24 +#define ADDRMAP2_COL_B5_SHIFT 24 +/* DDRC_ADDRMAP3 fields */ +#define ADDRMAP3_COL_B6_MASK 0xF << 0 +#define ADDRMAP3_COL_B6_SHIFT 0 +#define ADDRMAP3_COL_B7_MASK 0xF << 8 +#define ADDRMAP3_COL_B7_SHIFT 8 +#define ADDRMAP3_COL_B8_MASK 0xF << 16 +#define ADDRMAP3_COL_B8_SHIFT 16 +#define ADDRMAP3_COL_B9_MASK 0xF << 24 +#define ADDRMAP3_COL_B9_SHIFT 24 +/* DDRC_ADDRMAP4 fields */ +#define ADDRMAP4_COL_B10_MASK 0xF << 0 +#define ADDRMAP4_COL_B10_SHIFT 0 +#define ADDRMAP4_COL_B11_MASK 0xF << 8 +#define ADDRMAP4_COL_B11_SHIFT 8 +/* DDRC_ADDRMAP5 fields */ +#define ADDRMAP5_ROW_B0_MASK 0xF << 0 +#define ADDRMAP5_ROW_B0_SHIFT 0 +#define ADDRMAP5_ROW_B1_MASK 0xF << 8 +#define ADDRMAP5_ROW_B1_SHIFT 8 +#define ADDRMAP5_ROW_B2_10_MASK 0xF << 16 +#define ADDRMAP5_ROW_B2_10_SHIFT 16 +#define ADDRMAP5_ROW_B11_MASK 0xF << 24 +#define ADDRMAP5_ROW_B11_SHIFT 24 +/* DDRC_ADDRMAP6 fields */ +#define ADDRMAP6_ROW_B12_MASK 0xF << 0 +#define ADDRMAP6_ROW_B12_SHIFT 0 +#define ADDRMAP6_ROW_B13_MASK 0xF << 8 +#define ADDRMAP6_ROW_B13_SHIFT 8 +#define ADDRMAP6_ROW_B14_MASK 0xF << 16 +#define ADDRMAP6_ROW_B14_SHIFT 16 +#define ADDRMAP6_ROW_B15_MASK 0xF << 24 +#define ADDRMAP6_ROW_B15_SHIFT 24 + +/* DDRC_MP Registers */ +#define DDRC_MP_BASE_ADDR (DDRC_IPS_BASE_ADDR + 0x03fc) +struct ddrc_mp { + u32 reserved1[0x25]; + u32 pctrl_0; /* 0x0094 */ +}; + +/* DDR_PHY registers */ +struct ddr_phy { + u32 phy_con0; /* 0x0000 */ + u32 phy_con1; /* 0x0004 */ + u32 reserved1[0x02]; + u32 phy_con4; /* 0x0010 */ + u32 reserved2; + u32 offset_lp_con0; /* 0x0018 */ + u32 reserved3; + u32 offset_rd_con0; /* 0x0020 */ + u32 reserved4[0x03]; + u32 offset_wr_con0; /* 0x0030 */ + u32 reserved5[0x07]; + u32 cmd_sdll_con0; /* 0x0050 */ + u32 reserved6[0x12]; + u32 drvds_con0; /* 0x009c */ + u32 reserved7[0x04]; + u32 mdll_con0; /* 0x00b0 */ + u32 reserved8[0x03]; + u32 zq_con0; /* 0x00c0 */ +}; + +#define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK BIT(24) + +#define MX7_CAL_VAL_MAX 5 +/* Calibration parameters */ +struct mx7_calibration { + int num_val; /* Number of calibration values */ + u32 values[MX7_CAL_VAL_MAX]; /* calibration values */ +}; + +void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, + struct ddr_phy *ddr_phy_regs_val, + struct mx7_calibration *calib_param); + +#endif /*__ASM_ARCH_MX7_DDR_H__ */ diff --git a/arch/arm/mach-imx/mx7/Makefile b/arch/arm/mach-imx/mx7/Makefile index d21f87f..ce289c1 100644 --- a/arch/arm/mach-imx/mx7/Makefile +++ b/arch/arm/mach-imx/mx7/Makefile @@ -5,7 +5,7 @@ # #
-obj-y := soc.o clock.o clock_slice.o +obj-y := soc.o clock.o clock_slice.o ddr.o
ifdef CONFIG_ARMV7_PSCI obj-y += psci-mx7.o psci.o diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c new file mode 100644 index 0000000..9268ad9 --- /dev/null +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -0,0 +1,201 @@ +/* + * DDR controller configuration for the i.MX7 architecture + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach uri.mashiach@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/types.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx7-ddr.h> +#include <common.h> + +/* + * Routine: mx7_dram_cfg + * Description: DDR controller configuration + * + * @ddrc_regs_val: DDRC registers value + * @ddrc_mp_val: DDRC_MP registers value + * @ddr_phy_regs_val: DDR_PHY registers value + * @calib_param: calibration parameters + * + */ +void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, + struct ddr_phy *ddr_phy_regs_val, + struct mx7_calibration *calib_param) +{ + struct src *const src_regs = (struct src *)SRC_BASE_ADDR; + struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR; + struct ddrc_mp *const ddrc_mp_reg = (struct ddrc_mp *)DDRC_MP_BASE_ADDR; + struct ddr_phy *const ddr_phy_regs = + (struct ddr_phy *)DDRPHY_IPS_BASE_ADDR; + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int i; + + /* Assert DDR Controller preset and DDR PHY reset */ + writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr); + + /* DDR controller configuration */ + writel(ddrc_regs_val->mstr, &ddrc_regs->mstr); + writel(ddrc_regs_val->rfshtmg, &ddrc_regs->rfshtmg); + writel(ddrc_mp_val->pctrl_0, &ddrc_mp_reg->pctrl_0); + writel(ddrc_regs_val->init1, &ddrc_regs->init1); + writel(ddrc_regs_val->init0, &ddrc_regs->init0); + writel(ddrc_regs_val->init3, &ddrc_regs->init3); + writel(ddrc_regs_val->init4, &ddrc_regs->init4); + writel(ddrc_regs_val->init5, &ddrc_regs->init5); + writel(ddrc_regs_val->rankctl, &ddrc_regs->rankctl); + writel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0); + writel(ddrc_regs_val->dramtmg1, &ddrc_regs->dramtmg1); + writel(ddrc_regs_val->dramtmg2, &ddrc_regs->dramtmg2); + writel(ddrc_regs_val->dramtmg3, &ddrc_regs->dramtmg3); + writel(ddrc_regs_val->dramtmg4, &ddrc_regs->dramtmg4); + writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5); + writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8); + writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0); + writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0); + writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1); + writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0); + writel(ddrc_regs_val->dfiupd1, &ddrc_regs->dfiupd1); + writel(ddrc_regs_val->dfiupd2, &ddrc_regs->dfiupd2); + writel(ddrc_regs_val->addrmap0, &ddrc_regs->addrmap0); + writel(ddrc_regs_val->addrmap1, &ddrc_regs->addrmap1); + writel(ddrc_regs_val->addrmap4, &ddrc_regs->addrmap4); + writel(ddrc_regs_val->addrmap5, &ddrc_regs->addrmap5); + writel(ddrc_regs_val->addrmap6, &ddrc_regs->addrmap6); + writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg); + writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap); + + /* De-assert DDR Controller preset and DDR PHY reset */ + clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK); + + /* PHY configuration */ + writel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0); + writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1); + writel(ddr_phy_regs_val->phy_con4, &ddr_phy_regs->phy_con4); + writel(ddr_phy_regs_val->mdll_con0, &ddr_phy_regs->mdll_con0); + writel(ddr_phy_regs_val->drvds_con0, &ddr_phy_regs->drvds_con0); + writel(ddr_phy_regs_val->offset_wr_con0, &ddr_phy_regs->offset_wr_con0); + writel(ddr_phy_regs_val->offset_rd_con0, &ddr_phy_regs->offset_rd_con0); + writel(ddr_phy_regs_val->cmd_sdll_con0 | + DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK, + &ddr_phy_regs->cmd_sdll_con0); + writel(ddr_phy_regs_val->cmd_sdll_con0 & + ~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK, + &ddr_phy_regs->cmd_sdll_con0); + writel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0); + + /* calibration */ + for (i = 0; i < calib_param->num_val; i++) + writel(calib_param->values[i], &ddr_phy_regs->zq_con0); + + /* Wake_up DDR PHY */ + HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_N_N); + writel(IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(0xf) | + IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK, + &iomuxc_gpr_regs->gpr[8]); + HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_R_W); +} + +/* + * Routine: imx_ddr_size + * Description: extract the current DRAM size from the DDRC registers + * + * @return: DRAM size + */ +unsigned int imx_ddr_size(void) +{ + struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR; + u32 reg_val, field_val; + int bits = 0;/* Number of address bits */ + + /* Count data bus width bits */ + reg_val = readl(&ddrc_regs->mstr); + field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT; + bits += 2 - field_val; + /* Count rank address bits */ + field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT; + if (field_val > 1) + bits += field_val - 1; + /* Count column address bits */ + bits += 2;/* Column address 0 and 1 are fixed mapped */ + reg_val = readl(&ddrc_regs->addrmap2); + field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT; + if (field_val <= 7) + bits++; + field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT; + if (field_val <= 7) + bits++; + field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT; + if (field_val <= 7) + bits++; + field_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT; + if (field_val <= 7) + bits++; + reg_val = readl(&ddrc_regs->addrmap3); + field_val = (reg_val & ADDRMAP3_COL_B6_MASK) >> ADDRMAP3_COL_B6_SHIFT; + if (field_val <= 7) + bits++; + field_val = (reg_val & ADDRMAP3_COL_B7_MASK) >> ADDRMAP3_COL_B7_SHIFT; + if (field_val <= 7) + bits++; + field_val = (reg_val & ADDRMAP3_COL_B8_MASK) >> ADDRMAP3_COL_B8_SHIFT; + if (field_val <= 7) + bits++; + field_val = (reg_val & ADDRMAP3_COL_B9_MASK) >> ADDRMAP3_COL_B9_SHIFT; + if (field_val <= 7) + bits++; + reg_val = readl(&ddrc_regs->addrmap4); + field_val = (reg_val & ADDRMAP4_COL_B10_MASK) >> ADDRMAP4_COL_B10_SHIFT; + if (field_val <= 7) + bits++; + field_val = (reg_val & ADDRMAP4_COL_B11_MASK) >> ADDRMAP4_COL_B11_SHIFT; + if (field_val <= 7) + bits++; + /* Count row address bits */ + reg_val = readl(&ddrc_regs->addrmap5); + field_val = (reg_val & ADDRMAP5_ROW_B0_MASK) >> ADDRMAP5_ROW_B0_SHIFT; + if (field_val <= 11) + bits++; + field_val = (reg_val & ADDRMAP5_ROW_B1_MASK) >> ADDRMAP5_ROW_B1_SHIFT; + if (field_val <= 11) + bits++; + field_val = (reg_val & ADDRMAP5_ROW_B2_10_MASK) >> ADDRMAP5_ROW_B2_10_SHIFT; + if (field_val <= 11) + bits += 9; + field_val = (reg_val & ADDRMAP5_ROW_B11_MASK) >> ADDRMAP5_ROW_B11_SHIFT; + if (field_val <= 11) + bits++; + reg_val = readl(&ddrc_regs->addrmap6); + field_val = (reg_val & ADDRMAP6_ROW_B12_MASK) >> ADDRMAP6_ROW_B12_SHIFT; + if (field_val <= 11) + bits++; + field_val = (reg_val & ADDRMAP6_ROW_B13_MASK) >> ADDRMAP6_ROW_B13_SHIFT; + if (field_val <= 11) + bits++; + field_val = (reg_val & ADDRMAP6_ROW_B14_MASK) >> ADDRMAP6_ROW_B14_SHIFT; + if (field_val <= 11) + bits++; + field_val = (reg_val & ADDRMAP6_ROW_B15_MASK) >> ADDRMAP6_ROW_B15_SHIFT; + if (field_val <= 11) + bits++; + /* Count bank bits */ + reg_val = readl(&ddrc_regs->addrmap1); + field_val = (reg_val & ADDRMAP1_BANK_B0_MASK) >> ADDRMAP1_BANK_B0_SHIFT; + if (field_val <= 30) + bits++; + field_val = (reg_val & ADDRMAP1_BANK_B1_MASK) >> ADDRMAP1_BANK_B1_SHIFT; + if (field_val <= 30) + bits++; + field_val = (reg_val & ADDRMAP1_BANK_B2_MASK) >> ADDRMAP1_BANK_B2_SHIFT; + if (field_val <= 29) + bits++; + + return 1 << bits; +}
Add configuration file and spl_boot_device function for the i.MX7 SPL.
Signed-off-by: Uri Mashiach uri.mashiach@compulab.co.il --- arch/arm/include/asm/arch-mx7/sys_proto.h | 1 + arch/arm/mach-imx/spl.c | 23 ++++++++++- include/configs/imx7_spl.h | 67 +++++++++++++++++++++++++++++++ 3 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 include/configs/imx7_spl.h
diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h b/arch/arm/include/asm/arch-mx7/sys_proto.h index 15e24d4..fa62424 100644 --- a/arch/arm/include/asm/arch-mx7/sys_proto.h +++ b/arch/arm/include/asm/arch-mx7/sys_proto.h @@ -7,3 +7,4 @@ #include <asm/mach-imx/sys_proto.h>
void set_wdog_reset(struct wdog_regs *wdog); +enum boot_device get_boot_device(void); diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 258578a..c41f40c 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -14,6 +14,7 @@ #include <asm/spl.h> #include <spl.h> #include <asm/mach-imx/hab.h> +#include <asm/mach-imx/boot_mode.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -82,7 +83,27 @@ u32 spl_boot_device(void) } return BOOT_DEVICE_NONE; } -#endif + +#elif defined(CONFIG_MX7) +/* Translate iMX7 boot device to the SPL boot device enumeration */ +u32 spl_boot_device(void) +{ + enum boot_device boot_device_spl = get_boot_device(); + + switch (boot_device_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case SPI_NOR_BOOT: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_NONE; + } +} +#endif /* CONFIG_MX6 || CONFIG_MX7 */
#if defined(CONFIG_SPL_MMC_SUPPORT) /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h new file mode 100644 index 0000000..e562cdb --- /dev/null +++ b/include/configs/imx7_spl.h @@ -0,0 +1,67 @@ +/* + * SPL definitions for the i.MX7 SPL + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach uri.mashiach@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX7_SPL_CONFIG_H +#define __IMX7_SPL_CONFIG_H + +#ifdef CONFIG_SPL + +#define CONFIG_SPL_FRAMEWORK + +/* + * see figure 6-22 in i.MX 7Dual/Solo Reference manuals: + * - IMX7D/S OCRAM free area RAM (OCRAM) is from 0x00910000 to + * 0x00946C00. + * - Set the stack at the end of the free area section, at 0x00946BB8. + * - The BOOT ROM loads what they consider the firmware image + * which consists of a 4K header in front of us that contains the IVT, DCD + * and some padding thus 'our' max size is really 0x00946BB8 - 0x00911000. + * 64KB is more then enough for the SPL. + */ +#define CONFIG_SPL_TEXT_BASE 0x00911000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_STACK 0x00946BB8 +/* + * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the + * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + * boot media (given that boot media specific offset is configured properly). + */ +#define CONFIG_SPL_PAD_TO 0x11000 + +/* MMC support */ +#if defined(CONFIG_SPL_MMC_SUPPORT) +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ +#endif + +/* SATA support */ +#if defined(CONFIG_SPL_SATA_SUPPORT) +#define CONFIG_SPL_SATA_BOOT_DEVICE 0 +#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 +#endif + +/* Define the payload for FAT/EXT support */ +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) +# ifdef CONFIG_OF_CONTROL +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +# else +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +# endif +#endif + +#define CONFIG_SPL_BSS_START_ADDR 0x88200000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x88300000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_TEXT_BASE 0x87800000 + +#endif /* CONFIG_SPL */ + +#endif /* __IMX7_SPL_CONFIG_H */
Hi Uri,
On Sun, Sep 24, 2017 at 3:00 AM, Uri Mashiach uri.mashiach@compulab.co.il wrote:
Add configuration file and spl_boot_device function for the i.MX7 SPL.
Signed-off-by: Uri Mashiach uri.mashiach@compulab.co.il
Thanks for working on this!
I will test your series and will try to convert imx7d-sabresd to SPL.
Thanks!
Hi Uri,
On 24/09/2017 15:32, Fabio Estevam wrote:
Hi Uri,
On Sun, Sep 24, 2017 at 3:00 AM, Uri Mashiach uri.mashiach@compulab.co.il wrote:
Add configuration file and spl_boot_device function for the i.MX7 SPL.
Signed-off-by: Uri Mashiach uri.mashiach@compulab.co.il
Thanks for working on this!
I will test your series and will try to convert imx7d-sabresd to SPL.
It looks like that at least a define is missing - by applying the patch and testing, I get the error:
+board/compulab/cl-som-imx7/cl-som-imx7.c: In function 'cl_som_imx7_setup_fec': +board/compulab/cl-som-imx7/cl-som-imx7.c:231:15: error: 'ENET_125MHz' undeclared (first use in this function)
In fact, ENET_125MHz is not definded anywhere in U-Boot. Could you please check and fix this ?
Best regards, Stefano Babic
On Mon, Oct 2, 2017 at 11:22 AM, Stefano Babic sbabic@denx.de wrote:
Hi Uri,
On 24/09/2017 15:32, Fabio Estevam wrote:
Hi Uri,
On Sun, Sep 24, 2017 at 3:00 AM, Uri Mashiach uri.mashiach@compulab.co.il wrote:
Add configuration file and spl_boot_device function for the i.MX7 SPL.
Signed-off-by: Uri Mashiach uri.mashiach@compulab.co.il
Thanks for working on this!
I will test your series and will try to convert imx7d-sabresd to SPL.
It looks like that at least a define is missing - by applying the patch and testing, I get the error:
+board/compulab/cl-som-imx7/cl-som-imx7.c: In function 'cl_som_imx7_setup_fec': +board/compulab/cl-som-imx7/cl-som-imx7.c:231:15: error: 'ENET_125MHz' undeclared (first use in this function)
In fact, ENET_125MHz is not definded anywhere in U-Boot. Could you please check and fix this ?
It is defined but now it is all upper case. Eric did rename it.
Hi Otavio, Fabio,
On 02/10/2017 16:25, Otavio Salvador wrote:
On Mon, Oct 2, 2017 at 11:22 AM, Stefano Babic sbabic@denx.de wrote:
Hi Uri,
On 24/09/2017 15:32, Fabio Estevam wrote:
Hi Uri,
On Sun, Sep 24, 2017 at 3:00 AM, Uri Mashiach uri.mashiach@compulab.co.il wrote:
Add configuration file and spl_boot_device function for the i.MX7 SPL.
Signed-off-by: Uri Mashiach uri.mashiach@compulab.co.il
Thanks for working on this!
I will test your series and will try to convert imx7d-sabresd to SPL.
It looks like that at least a define is missing - by applying the patch and testing, I get the error:
+board/compulab/cl-som-imx7/cl-som-imx7.c: In function 'cl_som_imx7_setup_fec': +board/compulab/cl-som-imx7/cl-som-imx7.c:231:15: error: 'ENET_125MHz' undeclared (first use in this function)
In fact, ENET_125MHz is not definded anywhere in U-Boot. Could you please check and fix this ?
It is defined but now it is all upper case. Eric did rename it.
Yes, thanks both ! It was the "Camelcase" patch, I have forgotten it.
Best regards, Stefano
Hi Stefano,
On Mon, Oct 2, 2017 at 11:22 AM, Stefano Babic sbabic@denx.de wrote:
It looks like that at least a define is missing - by applying the patch and testing, I get the error:
+board/compulab/cl-som-imx7/cl-som-imx7.c: In function 'cl_som_imx7_setup_fec': +board/compulab/cl-som-imx7/cl-som-imx7.c:231:15: error: 'ENET_125MHz' undeclared (first use in this function)
In fact, ENET_125MHz is not definded anywhere in U-Boot. Could you please check and fix this ?
This define has changed since: https://patchwork.ozlabs.org/patch/807947/
It is ENET_125MHZ now.
Thanks
Hi Stefano,
On 10/02/2017 05:22 PM, Stefano Babic wrote:
Hi Uri,
On 24/09/2017 15:32, Fabio Estevam wrote:
Hi Uri,
On Sun, Sep 24, 2017 at 3:00 AM, Uri Mashiach uri.mashiach@compulab.co.il wrote:
Add configuration file and spl_boot_device function for the i.MX7 SPL.
Signed-off-by: Uri Mashiach uri.mashiach@compulab.co.il
Thanks for working on this!
I will test your series and will try to convert imx7d-sabresd to SPL.
It looks like that at least a define is missing - by applying the patch and testing, I get the error:
+board/compulab/cl-som-imx7/cl-som-imx7.c: In function 'cl_som_imx7_setup_fec': +board/compulab/cl-som-imx7/cl-som-imx7.c:231:15: error: 'ENET_125MHz' undeclared (first use in this function)
In fact, ENET_125MHz is not definded anywhere in U-Boot. Could you please check and fix this ?
Best regards, Stefano Babic
The patch is compiling in u-boot-imx/master. Should it be based on mainline u-boot?
Hi Uri,
On 02/10/2017 16:59, Uri Mashiach wrote:
Hi Stefano,
On 10/02/2017 05:22 PM, Stefano Babic wrote:
Hi Uri,
On 24/09/2017 15:32, Fabio Estevam wrote:
Hi Uri,
On Sun, Sep 24, 2017 at 3:00 AM, Uri Mashiach uri.mashiach@compulab.co.il wrote:
Add configuration file and spl_boot_device function for the i.MX7 SPL.
Signed-off-by: Uri Mashiach uri.mashiach@compulab.co.il
Thanks for working on this!
I will test your series and will try to convert imx7d-sabresd to SPL.
It looks like that at least a define is missing - by applying the patch and testing, I get the error:
+board/compulab/cl-som-imx7/cl-som-imx7.c: In function 'cl_som_imx7_setup_fec': +board/compulab/cl-som-imx7/cl-som-imx7.c:231:15: error: 'ENET_125MHz' undeclared (first use in this function)
In fact, ENET_125MHz is not definded anywhere in U-Boot. Could you please check and fix this ?
Best regards, Stefano Babic
The patch is compiling in u-boot-imx/master. Should it be based on mainline u-boot?
No, it is ok - see above, I fix the Camelcase. There is still a small conflict in arch/arm/mach-imx/spl.c (due to other patches I am merging), I fix this as well. If all is fine, I psuh it to the server. This simplifies Fabio's work and someone else can help with tests. Best regards, Stefano Babic
From: Ilya Ledvich ilya@compulab.co.il
Add initial support for Compulab cl-som-imx7 SoM. The initial support includes: - MMC - eMMC - SPI flash - I2C - FEC - USB - Serial console
Signed-off-by: Ilya Ledvich ilya@compulab.co.il --- arch/arm/mach-imx/mx7/Kconfig | 8 + board/compulab/cl-som-imx7/Kconfig | 28 +++ board/compulab/cl-som-imx7/MAINTAINERS | 6 + board/compulab/cl-som-imx7/Makefile | 17 ++ board/compulab/cl-som-imx7/cl-som-imx7.c | 331 +++++++++++++++++++++++++++++++ board/compulab/cl-som-imx7/common.c | 46 +++++ board/compulab/cl-som-imx7/common.h | 32 +++ board/compulab/cl-som-imx7/mux.c | 142 +++++++++++++ board/compulab/cl-som-imx7/spl.c | 211 ++++++++++++++++++++ configs/cl-som-imx7_defconfig | 54 +++++ include/configs/cl-som-imx7.h | 192 ++++++++++++++++++ 11 files changed, 1067 insertions(+) create mode 100644 board/compulab/cl-som-imx7/Kconfig create mode 100644 board/compulab/cl-som-imx7/MAINTAINERS create mode 100644 board/compulab/cl-som-imx7/Makefile create mode 100644 board/compulab/cl-som-imx7/cl-som-imx7.c create mode 100644 board/compulab/cl-som-imx7/common.c create mode 100644 board/compulab/cl-som-imx7/common.h create mode 100644 board/compulab/cl-som-imx7/mux.c create mode 100644 board/compulab/cl-som-imx7/spl.c create mode 100644 configs/cl-som-imx7_defconfig create mode 100644 include/configs/cl-som-imx7.h
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index aea8526..365501d 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -18,6 +18,13 @@ choice prompt "MX7 board select" optional
+config TARGET_CL_SOM_IMX7 + bool "CL-SOM-iMX7" + select MX7D + select DM + select DM_THERMAL + select SUPPORT_SPL + config TARGET_MX7DSABRESD bool "mx7dsabresd" select BOARD_LATE_INIT @@ -51,6 +58,7 @@ endchoice config SYS_SOC default "mx7"
+source "board/compulab/cl-som-imx7/Kconfig" source "board/freescale/mx7dsabresd/Kconfig" source "board/technexion/pico-imx7d/Kconfig" source "board/toradex/colibri_imx7/Kconfig" diff --git a/board/compulab/cl-som-imx7/Kconfig b/board/compulab/cl-som-imx7/Kconfig new file mode 100644 index 0000000..6d69cf3 --- /dev/null +++ b/board/compulab/cl-som-imx7/Kconfig @@ -0,0 +1,28 @@ +if TARGET_CL_SOM_IMX7 + +config SYS_BOARD + default "cl-som-imx7" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "cl-som-imx7" + +config SYS_MMC_DEV + int + default 0 + +config SYS_USB_DEV + int + default 0 + +config SYS_MMC_IMG_LOAD_PART + int + default 1 + +config SYS_USB_IMG_LOAD_PART + int + default 1 + +endif diff --git a/board/compulab/cl-som-imx7/MAINTAINERS b/board/compulab/cl-som-imx7/MAINTAINERS new file mode 100644 index 0000000..2b917a5 --- /dev/null +++ b/board/compulab/cl-som-imx7/MAINTAINERS @@ -0,0 +1,6 @@ +CL-SOM-IMX7 BOARD +M: Uri Mashiach uri.mashiach@compulab.co.il +S: Maintained +F: board/compulab/cl-som-imx7 +F: include/configs/cl-som-imx7.h +F: configs/cl-som-imx7_defconfig diff --git a/board/compulab/cl-som-imx7/Makefile b/board/compulab/cl-som-imx7/Makefile new file mode 100644 index 0000000..8f0e068 --- /dev/null +++ b/board/compulab/cl-som-imx7/Makefile @@ -0,0 +1,17 @@ +# +# Makefile +# +# (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com +# +# Author: Uri Mashiach uri.mashiach@compulab.co.il +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mux.o common.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += cl-som-imx7.o +endif diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c new file mode 100644 index 0000000..2957180 --- /dev/null +++ b/board/compulab/cl-som-imx7/cl-som-imx7.c @@ -0,0 +1,331 @@ +/* + * U-Boot board functions for CompuLab CL-SOM-iMX7 module + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach uri.mashiach@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mmc.h> +#include <phy.h> +#include <netdev.h> +#include <fsl_esdhc.h> +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch-mx7/mx7-pins.h> +#include <asm/arch-mx7/sys_proto.h> +#include <asm/arch-mx7/clock.h> +#include "../common/eeprom.h" +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SYS_I2C_MXC + +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS) + +#define CL_SOM_IMX7_GPIO_I2C2_SCL IMX_GPIO_NR(1, 6) +#define CL_SOM_IMX7_GPIO_I2C2_SDA IMX_GPIO_NR(1, 7) + +static struct i2c_pads_info cl_som_imx7_i2c_pad_info2 = { + .scl = { + .i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL | + MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | + MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = CL_SOM_IMX7_GPIO_I2C2_SCL, + }, + .sda = { + .i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA | + MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 | + MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = CL_SOM_IMX7_GPIO_I2C2_SDA, + }, +}; + +/* + * cl_som_imx7_setup_i2c() - I2C pinmux configuration. + */ +static void cl_som_imx7_setup_i2c(void) +{ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &cl_som_imx7_i2c_pad_info2); +} +#else /* !CONFIG_SYS_I2C_MXC */ +static void cl_som_imx7_setup_i2c(void) {} +#endif /* CONFIG_SYS_I2C_MXC */ + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC + +#define CL_SOM_IMX7_GPIO_USDHC3_PWR IMX_GPIO_NR(6, 11) + +static struct fsl_esdhc_cfg cl_som_imx7_usdhc_cfg[3] = { + {USDHC1_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc2 USDHC3 (eMMC) + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + cl_som_imx7_usdhc1_pads_set(); + gpio_request(CL_SOM_IMX7_GPIO_USDHC1_CD, "usdhc1_cd"); + cl_som_imx7_usdhc_cfg[0].sdhc_clk = + mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + cl_som_imx7_usdhc3_emmc_pads_set(); + gpio_request(CL_SOM_IMX7_GPIO_USDHC3_PWR, "usdhc3_pwr"); + gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 0); + udelay(500); + gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 1); + cl_som_imx7_usdhc_cfg[1].sdhc_clk = + mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers " + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &cl_som_imx7_usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif /* CONFIG_FSL_ESDHC */ + +#ifdef CONFIG_FEC_MXC + +#define CL_SOM_IMX7_ETH1_PHY_NRST IMX_GPIO_NR(1, 4) + +/* + * cl_som_imx7_rgmii_rework() - Ethernet PHY configuration. + */ +static void cl_som_imx7_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val; + + /* Ar8031 phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= ~(0x1 << 8); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); +} + +int board_phy_config(struct phy_device *phydev) +{ + cl_som_imx7_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +/* + * cl_som_imx7_handle_mac_address() - set Ethernet MAC address environment. + * + * @env_var: MAC address environment variable + * @eeprom_bus: I2C bus of the environment EEPROM + * + * @return: 0 on success, < 0 on failure + */ +static int cl_som_imx7_handle_mac_address(char *env_var, uint eeprom_bus) +{ + int ret; + unsigned char enetaddr[6]; + + ret = eth_env_get_enetaddr(env_var, enetaddr); + if (ret) + return 0; + + ret = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus); + if (ret) + return ret; + + ret = is_valid_ethaddr(enetaddr); + if (!ret) + return -1; + + return eth_env_set_enetaddr(env_var, enetaddr); +} + +#define CL_SOM_IMX7_FEC_DEV_ID_PRI 0 + +int board_eth_init(bd_t *bis) +{ + /* set Ethernet MAC address environment */ + cl_som_imx7_handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS); + /* Ethernet interface pinmux configuration */ + cl_som_imx7_phy1_rst_pads_set(); + cl_som_imx7_fec1_pads_set(); + /* PHY reset */ + gpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, "eth1_phy_nrst"); + gpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0); + mdelay(10); + gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1); + /* MAC initialization */ + return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); +} + +/* + * cl_som_imx7_setup_fec() - Ethernet MAC 1 clock configuration. + * - ENET1 reference clock mode select. + * - ENET1_TX_CLK output driver is disabled when configured for ALT1. + */ +static void cl_som_imx7_setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + + set_clk_enet(ENET_125MHz); +} +#else /* !CONFIG_FEC_MXC */ +static void cl_som_imx7_setup_fec(void) {} +#endif /* CONFIG_FEC_MXC */ + +#ifdef CONFIG_SPI + +static void cl_som_imx7_spi_init(void) +{ + cl_som_imx7_espi1_pads_set(); +} +#else /* !CONFIG_SPI */ +static void cl_som_imx7_spi_init(void) {} +#endif /* CONFIG_SPI */ + +int board_early_init_f(void) +{ + cl_som_imx7_uart1_pads_set(); + cl_som_imx7_usb_otg1_pads_set(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + cl_som_imx7_setup_i2c(); + cl_som_imx7_setup_fec(); + cl_som_imx7_spi_init(); + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("PFUZE3000"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE3000_DEVICEID, ®); + pmic_reg_read(p, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1); + + return 0; +} +#endif /* CONFIG_POWER */ + +/* + * cl_som_imx7_setup_wdog() - watchdog configuration. + * - Output WDOG_B signal to reset external pmic. + * - Suspend the watchdog timer during low-power modes. + */ +void cl_som_imx7_setup_wdog(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + cl_som_imx7_wdog_pads_set(); + set_wdog_reset(wdog); + /* + * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), + * since we use PMIC_PWRON to reset the board. + */ + clrsetbits_le16(&wdog->wcr, 0, 0x10); +} + +int board_late_init(void) +{ + env_set("board_name", "CL-SOM-iMX7"); + cl_som_imx7_setup_wdog(); + return 0; +} + +int checkboard(void) +{ + char *mode; + + if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) + mode = "secure"; + else + mode = "non-secure"; + + printf("Board: CL-SOM-iMX7 in %s mode\n", mode); + + return 0; +} diff --git a/board/compulab/cl-som-imx7/common.c b/board/compulab/cl-som-imx7/common.c new file mode 100644 index 0000000..5ee688a --- /dev/null +++ b/board/compulab/cl-som-imx7/common.c @@ -0,0 +1,46 @@ +/* + * SPL/U-Boot common functions for CompuLab CL-SOM-iMX7 module + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach uri.mashiach@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_esdhc.h> +#include <asm-generic/gpio.h> +#include "common.h" + +#ifdef CONFIG_SPI + +#define CL_SOM_IMX7_GPIO_SPI_CS IMX_GPIO_NR(4, 19) + +int board_spi_cs_gpio(unsigned int bus, unsigned int cs) +{ + return CL_SOM_IMX7_GPIO_SPI_CS; +} + +#endif /* CONFIG_SPI */ + +#ifdef CONFIG_FSL_ESDHC + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(CL_SOM_IMX7_GPIO_USDHC1_CD); + break; + case USDHC3_BASE_ADDR: + ret = 1; /* Assume uSDHC3 emmc is always present */ + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC */ diff --git a/board/compulab/cl-som-imx7/common.h b/board/compulab/cl-som-imx7/common.h new file mode 100644 index 0000000..72d96af --- /dev/null +++ b/board/compulab/cl-som-imx7/common.h @@ -0,0 +1,32 @@ +/* + * SPL/U-Boot common header file for CompuLab CL-SOM-iMX7 module + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach uri.mashiach@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define PADS_SET_PROT(pads_array) void cl_som_imx7_##pads_array##_set(void) + +#ifdef CONFIG_FSL_ESDHC +#define CL_SOM_IMX7_GPIO_USDHC1_CD IMX_GPIO_NR(5, 0) +PADS_SET_PROT(usdhc1_pads); +#endif /* CONFIG_FSL_ESDHC */ +PADS_SET_PROT(uart1_pads); +#ifdef CONFIG_SPI +PADS_SET_PROT(espi1_pads); +#endif /* CONFIG_SPI */ + +#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_FSL_ESDHC +PADS_SET_PROT(usdhc3_emmc_pads); +#endif /* CONFIG_FSL_ESDHC */ +#ifdef CONFIG_FEC_MXC +PADS_SET_PROT(phy1_rst_pads); +PADS_SET_PROT(fec1_pads); +#endif /* CONFIG_FEC_MXC */ +PADS_SET_PROT(usb_otg1_pads); +PADS_SET_PROT(wdog_pads); +#endif /* !CONFIG_SPL_BUILD */ diff --git a/board/compulab/cl-som-imx7/mux.c b/board/compulab/cl-som-imx7/mux.c new file mode 100644 index 0000000..82e8b9f --- /dev/null +++ b/board/compulab/cl-som-imx7/mux.c @@ -0,0 +1,142 @@ +/* + * SPL/U-Boot mux functions for CompuLab CL-SOM-iMX7 module + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach uri.mashiach@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch-mx7/mx7-pins.h> + +#define PADS_SET(pads_array) \ +void cl_som_imx7_##pads_array##_set(void) \ +{ \ + imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array)); \ +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_PUS_PU47KOHM) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +PADS_SET(usdhc1_pads) + +#endif /* CONFIG_FSL_ESDHC */ + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +PADS_SET(uart1_pads) + +#ifdef CONFIG_SPI + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SRE_SLOW | \ + PAD_CTL_DSE_3P3V_32OHM) + +#define GPIO_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \ + PAD_CTL_SRE_SLOW) + +static iomux_v3_cfg_t const espi1_pads[] = { + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +PADS_SET(espi1_pads) + +#endif /* CONFIG_SPI */ + +#ifndef CONFIG_SPL_BUILD + +#ifdef CONFIG_FSL_ESDHC + +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +PADS_SET(usdhc3_emmc_pads) + +#endif /* CONFIG_FSL_ESDHC */ + +#ifdef CONFIG_FEC_MXC + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU5KOHM) + +static iomux_v3_cfg_t const phy1_rst_pads[] = { + /* PHY1 RST */ + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +PADS_SET(phy1_rst_pads) + +static iomux_v3_cfg_t const fec1_pads[] = { + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), +}; + +PADS_SET(fec1_pads) + +#endif /* CONFIG_FEC_MXC */ + +static iomux_v3_cfg_t const usb_otg1_pads[] = { + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +PADS_SET(usb_otg1_pads) + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +PADS_SET(wdog_pads) + +#endif /* !CONFIG_SPL_BUILD */ diff --git a/board/compulab/cl-som-imx7/spl.c b/board/compulab/cl-som-imx7/spl.c new file mode 100644 index 0000000..3b013c0 --- /dev/null +++ b/board/compulab/cl-som-imx7/spl.c @@ -0,0 +1,211 @@ +/* + * SPL board functions for CompuLab CL-SOM-iMX7 module + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach uri.mashiach@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <fsl_esdhc.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch-mx7/mx7-pins.h> +#include <asm/arch-mx7/clock.h> +#include <asm/arch-mx7/mx7-ddr.h> +#include "common.h" + +#ifdef CONFIG_FSL_ESDHC + +static struct fsl_esdhc_cfg cl_som_imx7_spl_usdhc_cfg = { + USDHC1_BASE_ADDR, 0, 4}; + +int board_mmc_init(bd_t *bis) +{ + cl_som_imx7_usdhc1_pads_set(); + cl_som_imx7_spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + return fsl_esdhc_initialize(bis, &cl_som_imx7_spl_usdhc_cfg); +} +#endif /* CONFIG_FSL_ESDHC */ + +static iomux_v3_cfg_t const led_pads[] = { + MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM | + PAD_CTL_PUE | PAD_CTL_SRE_SLOW) +}; + +static struct ddrc cl_som_imx7_spl_ddrc_regs_val = { + .init1 = 0x00690000, + .init0 = 0x00020083, + .init3 = 0x09300004, + .init4 = 0x04080000, + .init5 = 0x00100004, + .rankctl = 0x0000033F, + .dramtmg1 = 0x0007020E, + .dramtmg2 = 0x03040407, + .dramtmg3 = 0x00002006, + .dramtmg4 = 0x04020305, + .dramtmg5 = 0x03030202, + .dramtmg8 = 0x00000803, + .zqctl0 = 0x00810021, + .dfitmg0 = 0x02098204, + .dfitmg1 = 0x00030303, + .dfiupd0 = 0x80400003, + .dfiupd1 = 0x00100020, + .dfiupd2 = 0x80100004, + .addrmap4 = 0x00000F0F, + .odtcfg = 0x06000604, + .odtmap = 0x00000001, +}; + +static struct ddrc_mp cl_som_imx7_spl_ddrc_mp_val = { + .pctrl_0 = 0x00000001, +}; + +static struct ddr_phy cl_som_imx7_spl_ddr_phy_regs_val = { + .phy_con0 = 0x17420F40, + .phy_con1 = 0x10210100, + .phy_con4 = 0x00060807, + .mdll_con0 = 0x1010007E, + .drvds_con0 = 0x00000D6E, + .cmd_sdll_con0 = 0x00000010, + .offset_lp_con0 = 0x0000000F, +}; + +struct mx7_calibration cl_som_imx7_spl_calib_param = { + .num_val = 5, + .values = { + 0x0E407304, + 0x0E447304, + 0x0E447306, + 0x0E447304, + 0x0E407304, + }, +}; + +static void cl_som_imx7_spl_dram_cfg_size(u32 ram_size) +{ + switch (ram_size) { + case SZ_256M: + cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01041001; + cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046; + cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; + cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000014; + cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00151515; + cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x03030303; + cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F0F0303; + cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0C0C0C0C; + cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404; + break; + case SZ_512M: + cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; + cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046; + cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; + cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000015; + cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00161616; + cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404; + cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F0F0404; + cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0C0C0C0C; + cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404; + break; + case SZ_1G: + cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; + cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046; + cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; + cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000016; + cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00171717; + cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404; + cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F040404; + cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0A0A0A0A; + cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x02020202; + break; + case SZ_2G: + cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; + cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x0040005E; + cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E110A; + cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000018; + cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00181818; + cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404; + cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x04040404; + cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0A0A0A0A; + cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404; + break; + } + + mx7_dram_cfg(&cl_som_imx7_spl_ddrc_regs_val, + &cl_som_imx7_spl_ddrc_mp_val, + &cl_som_imx7_spl_ddr_phy_regs_val, + &cl_som_imx7_spl_calib_param); +} + +static void cl_som_imx7_spl_dram_cfg(void) +{ + ulong ram_size_test, ram_size = 0; + + for (ram_size = SZ_2G; ram_size >= SZ_256M; ram_size >>= 1) { + cl_som_imx7_spl_dram_cfg_size(ram_size); + ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size); + if (ram_size_test == ram_size) + break; + } + + if (ram_size < SZ_256M) { + puts("!!!ERROR!!! DRAM detection failed!!!\n"); + hang(); + } +} + +#ifdef CONFIG_SPL_SPI_SUPPORT + +static void cl_som_imx7_spl_spi_init(void) +{ + cl_som_imx7_espi1_pads_set(); +} +#else /* !CONFIG_SPL_SPI_SUPPORT */ +static void cl_som_imx7_spl_spi_init(void) {} +#endif /* CONFIG_SPL_SPI_SUPPORT */ + +void board_init_f(ulong dummy) +{ + imx_iomux_v3_setup_multiple_pads(led_pads, 1); + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + /* setup GP timer */ + timer_init(); + cl_som_imx7_spl_spi_init(); + cl_som_imx7_uart1_pads_set(); + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + /* DRAM detection */ + cl_som_imx7_spl_dram_cfg(); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void spl_board_init(void) +{ + u32 boot_device = spl_boot_device(); + + if (boot_device == BOOT_DEVICE_SPI) + puts("Booting from SPI flash\n"); + else if (boot_device == BOOT_DEVICE_MMC1) + puts("Booting from SD card\n"); + else + puts("Unknown boot device\n"); +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + switch (spl_boot_list[0]) { + case BOOT_DEVICE_SPI: + spl_boot_list[1] = BOOT_DEVICE_MMC1; + break; + case BOOT_DEVICE_MMC1: + spl_boot_list[1] = BOOT_DEVICE_SPI; + break; + } +} diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig new file mode 100644 index 0000000..6c1d241 --- /dev/null +++ b/configs/cl-som-imx7_defconfig @@ -0,0 +1,54 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_CL_SOM_IMX7=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_SPI_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="CL-SOM-iMX7 # " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h new file mode 100644 index 0000000..14c4712 --- /dev/null +++ b/include/configs/cl-som-imx7.h @@ -0,0 +1,192 @@ +/* + * Copyright (C) 2015 CompuLab, Ltd. + * + * Configuration settings for the CompuLab CL-SOM-iMX7 System-on-Module. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CL_SOM_IMX7_CONFIG_H +#define __CL_SOM_IMX7_CONFIG_H + +#include "mx7_common.h" + +#define CONFIG_DBG_MONITOR + +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_BOARD_LATE_INIT + +/* Uncomment to enable secure boot support */ +/* #define CONFIG_SECURE_BOOT */ +#define CONFIG_CSF_SIZE 0x4000 + +/* Network */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +/* ENET1 */ +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +/* I2C configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define SYS_I2C_BUS_SOM 0 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM + +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } + +#undef CONFIG_SYS_AUTOLOAD +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND +#undef CONFIG_BOOTDELAY + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SYS_AUTOLOAD "no" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=off\0" \ + "script=boot.scr\0" \ + "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \ + "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \ + "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${fdtfile};\0" \ + "bootscript=echo Running bootscript from ${storagetype} ...; source ${loadaddr};\0" \ + "storagebootcmd=echo Booting from ${storagetype} ...; run ${storagetype}args; run doboot;\0" \ + "kernel=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdtfile=imx7d-sbc-imx7.dtb\0" \ + "fdtaddr=0x83000000\0" \ + "mmcdev_def="__stringify(CONFIG_SYS_MMC_DEV)"\0" \ + "usbdev_def="__stringify(CONFIG_SYS_USB_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "usbpart=" __stringify(CONFIG_SYS_USB_IMG_LOAD_PART) "\0" \ + "doboot=bootz ${loadaddr} - ${fdtaddr}\0" \ + "mmc_config=mmc dev ${mmcdev}; mmc rescan\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/mmcblk${mmcblk}p2 rootwait rw\0" \ + "mmcbootscript=" \ + "if run mmc_config; then " \ + "setenv storagetype mmc;" \ + "setenv storagedev ${mmcdev}:${mmcpart};" \ + "if run loadscript; then " \ + "run bootscript; " \ + "fi; " \ + "fi;\0" \ + "mmcboot=" \ + "if run mmc_config; then " \ + "setenv storagetype mmc;" \ + "setenv storagedev ${mmcdev}:${mmcpart};" \ + "if run loadkernel; then " \ + "if run loadfdt; then " \ + "run storagebootcmd;" \ + "fi; " \ + "fi; " \ + "fi;\0" \ + "sdbootscript=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; " \ + "run mmcbootscript\0" \ + "usbbootscript=setenv usbdev ${usbdev_def}; " \ + "setenv storagetype usb;" \ + "setenv storagedev ${usbdev}:${usbpart};" \ + "if run loadscript; then " \ + "run bootscript; " \ + "fi; " \ + "sdboot=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; run mmcboot\0" \ + "emmcbootscript=setenv mmcdev 1; setenv mmcblk 2; run mmcbootscript\0" \ + "emmcboot=setenv mmcdev 1; setenv mmcblk 2; run mmcboot\0" \ + +#define CONFIG_BOOTCOMMAND \ + "echo SD boot attempt ...; run sdbootscript; run sdboot; " \ + "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \ + "echo USB boot attempt ...; run usbbootscript; " + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* SPI Flash support */ +#define CONFIG_SPI +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) + +/* FLASH and environment organization */ +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED + +/* MMC Config*/ +#define CONFIG_FSL_USDHC +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#endif + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* Uncomment to enable iMX thermal driver support */ +/*#define CONFIG_IMX_THERMAL*/ + +/* SPL */ +#include "imx7_spl.h" +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) +#endif /* CONFIG_SPL_BUILD */ + +#endif /* __CONFIG_H */
Hi Uri,
On Sun, Sep 24, 2017 at 3:00 AM, Uri Mashiach uri.mashiach@compulab.co.il wrote:
This patch series adds support for CompuLab CL-SOM-iMX7, SBC-iMX7, SBC-IOT-iMX7 and IOT-GATE-iMX7.
CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on NXP i.MX7 processor family.
SBC-iMX7 is a single board computer, implemented with the CL-SOM-iMX7 module and the SB-SOM-iMX7 carrier board. The CL-SOM-iMX7 providing most of the functions and the SB-SOM-iMX7 providing additional peripheral functions and connectors.
SBC-IOT-iMX7 is a internet of things single board computer, implemented with the CL-SOM-iMX7 module and the SB-IOT-iMX7 carrier board. The CL-SOM-iMX7 providing most of the functions and the SB-IOT-iMX7 providing additional peripheral functions and connectors.
The CL-SOM-iMX7 has the following features:
CPU: NXP (Freescale) i.MX 7Dual ARM Cortex-A7, 1GHz processor (dual-core) or NXP (Freescale) i.MX 7Solo ARM Cortex-A7, 800MHz processor (single-core)
RAM: 256MB – 2GB, DDR3L-1066
Storage: SLC NAND flash, 128MB - 1GB or eMMC flash, 4GB - 32GB
Ethernet: Up to 2x 10/100/1000Mbps Ethernet ports (MAC+PHY)
WiFi: 802.11b/g/n WiFi interface (TI WiLink 8 WL1801 chipset) or Dual-band 2x2 802.11a/b/g/n WiFi interface (TI WiLink 8 WL1837 chipset)
Bluetooth: Bluetooth 4.1 BLE
Analog Audio: Audio codec with stereo output, stereo input and microphone support
Digital Audio: I2S compliant digital audio interface, MQS audio interface
Display: Parallel 24-bit display interface, up to 1920 x 1080 @60Hz, LVDS, up to 1400 x 1050 @60Hz MIPI-DSI, 2 data lanes, up to 1400 x 1050 @60Hz
More details can be found here:
http://www.compulab.com/products/computer-on-modules/cl-som-imx7-freescale-i...
http://www.compulab.com/products/sbcs/sbc-imx7-freescale-i-mx-7-single-board...
http://www.compulab.com/products/sbcs/sbc-iot-imx7-nxp-i-mx-7-internet-of-th...
http://www.compulab.com/products/iot-gateways/iot-gate-imx7-nxp-i-mx-7-inter...
Ilya Ledvich (1): arm: imx7d: add support for Compulab cl-som-imx7
Uri Mashiach (3): imx: mx7: fix the CCM_ macros imx: mx7: DDR controller configuration for the i.MX7 architecture imx: mx7: SPL support for i.MX7
I didn't have a chance to test it yet, but I don't want to block this work.
Your series looks good, thanks:
Reviewed-by: Fabio Estevam fabio.estevam@nxp.com
On 24/09/2017 08:00, Uri Mashiach wrote:
This patch series adds support for CompuLab CL-SOM-iMX7, SBC-iMX7, SBC-IOT-iMX7 and IOT-GATE-iMX7.
CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on NXP i.MX7 processor family.
SBC-iMX7 is a single board computer, implemented with the CL-SOM-iMX7 module and the SB-SOM-iMX7 carrier board. The CL-SOM-iMX7 providing most of the functions and the SB-SOM-iMX7 providing additional peripheral functions and connectors.
SBC-IOT-iMX7 is a internet of things single board computer, implemented with the CL-SOM-iMX7 module and the SB-IOT-iMX7 carrier board. The CL-SOM-iMX7 providing most of the functions and the SB-IOT-iMX7 providing additional peripheral functions and connectors.
The CL-SOM-iMX7 has the following features:
CPU: NXP (Freescale) i.MX 7Dual ARM Cortex-A7, 1GHz processor (dual-core) or NXP (Freescale) i.MX 7Solo ARM Cortex-A7, 800MHz processor (single-core)
RAM: 256MB – 2GB, DDR3L-1066
Storage: SLC NAND flash, 128MB - 1GB or eMMC flash, 4GB - 32GB
Ethernet: Up to 2x 10/100/1000Mbps Ethernet ports (MAC+PHY)
WiFi: 802.11b/g/n WiFi interface (TI WiLink 8 WL1801 chipset) or Dual-band 2x2 802.11a/b/g/n WiFi interface (TI WiLink 8 WL1837 chipset)
Bluetooth: Bluetooth 4.1 BLE
Analog Audio: Audio codec with stereo output, stereo input and microphone support
Digital Audio: I2S compliant digital audio interface, MQS audio interface
Display: Parallel 24-bit display interface, up to 1920 x 1080 @60Hz, LVDS, up to 1400 x 1050 @60Hz MIPI-DSI, 2 data lanes, up to 1400 x 1050 @60Hz
More details can be found here:
http://www.compulab.com/products/computer-on-modules/cl-som-imx7-freescale-i...
http://www.compulab.com/products/sbcs/sbc-imx7-freescale-i-mx-7-single-board...
http://www.compulab.com/products/sbcs/sbc-iot-imx7-nxp-i-mx-7-internet-of-th...
http://www.compulab.com/products/iot-gateways/iot-gate-imx7-nxp-i-mx-7-inter...
Ilya Ledvich (1): arm: imx7d: add support for Compulab cl-som-imx7
Uri Mashiach (3): imx: mx7: fix the CCM_ macros imx: mx7: DDR controller configuration for the i.MX7 architecture imx: mx7: SPL support for i.MX7
arch/arm/include/asm/arch-mx7/crm_regs.h | 51 ++--- arch/arm/include/asm/arch-mx7/imx-regs.h | 2 + arch/arm/include/asm/arch-mx7/mx7-ddr.h | 155 ++++++++++++++ arch/arm/include/asm/arch-mx7/sys_proto.h | 1 + arch/arm/mach-imx/mx7/Kconfig | 8 + arch/arm/mach-imx/mx7/Makefile | 2 +- arch/arm/mach-imx/mx7/ddr.c | 201 ++++++++++++++++++ arch/arm/mach-imx/spl.c | 23 ++- board/compulab/cl-som-imx7/Kconfig | 28 +++ board/compulab/cl-som-imx7/MAINTAINERS | 6 + board/compulab/cl-som-imx7/Makefile | 17 ++ board/compulab/cl-som-imx7/cl-som-imx7.c | 331 ++++++++++++++++++++++++++++++ board/compulab/cl-som-imx7/common.c | 46 +++++ board/compulab/cl-som-imx7/common.h | 32 +++ board/compulab/cl-som-imx7/mux.c | 142 +++++++++++++ board/compulab/cl-som-imx7/spl.c | 211 +++++++++++++++++++ configs/cl-som-imx7_defconfig | 54 +++++ include/configs/cl-som-imx7.h | 192 +++++++++++++++++ include/configs/imx7_spl.h | 67 ++++++ 19 files changed, 1544 insertions(+), 25 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx7/mx7-ddr.h create mode 100644 arch/arm/mach-imx/mx7/ddr.c create mode 100644 board/compulab/cl-som-imx7/Kconfig create mode 100644 board/compulab/cl-som-imx7/MAINTAINERS create mode 100644 board/compulab/cl-som-imx7/Makefile create mode 100644 board/compulab/cl-som-imx7/cl-som-imx7.c create mode 100644 board/compulab/cl-som-imx7/common.c create mode 100644 board/compulab/cl-som-imx7/common.h create mode 100644 board/compulab/cl-som-imx7/mux.c create mode 100644 board/compulab/cl-som-imx7/spl.c create mode 100644 configs/cl-som-imx7_defconfig create mode 100644 include/configs/cl-som-imx7.h create mode 100644 include/configs/imx7_spl.h
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
participants (4)
-
Fabio Estevam -
Otavio Salvador -
Stefano Babic -
Uri Mashiach