[PATCH] arm:dts:k3-am64-sk: EMIF tool update to 0.8.0 with 1333MTs for lpddr4
From: Sinthu Raja sinthu.raja@ti.com
EMIF tool for AM64 SK is now updated to 0.8.0 that includes * disabled Write DQ training * improve CA ODT to 60 ohms
The lpddr4 enabled with periodic WDQ training is causing periodic 26us stall. This makes the SoC stall without doing anything which leads to R5 interrupt latency in TCM memory. Due to this periodic training there are some outstanding CPU transactions waiting for the lpddr4 to complete.
Hence, disable the periodic write DQ training during the non-initialization stage of lpddr4 which results in an approximate 1us stall. Also, update the lpddr4 config to improve CA ODT by 60 ohms
The rationales are as follows: - PI_WDQLVL_EN: 2 Bits register field to support write DQ leveling, disable bit 1 that supports Write DQ during non-initialization to avoid ~26us stall during code execution.
- MR11_DATA_F1/F2_x register fields value changed to 0x66 that changes the CA ODT from 48ohm to 60ohm to improve the eye margin on CA bus by increasing the signal swing.
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Sinthu Raja sinthu.raja@ti.com --- arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi | 28 ++++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi b/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi index 64a159f6d0..dde5ab150d 100644 --- a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi +++ b/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi @@ -2,8 +2,8 @@ /* * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ * This file was generated with the - * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.06.00 - * Mon Apr 26 2021 20:47:47 GMT-0500 (Central Daylight Time) + * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.00 + * Wed Oct 13 2021 10:08:29 GMT-0500 (Central Daylight Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = 666.7MHz F2 = 666.7MHz * Density (per channel): 16Gb @@ -268,8 +268,8 @@ #define DDRSS_CTL_251_DATA 0x00000000 #define DDRSS_CTL_252_DATA 0x00000000 #define DDRSS_CTL_253_DATA 0x00000000 -#define DDRSS_CTL_254_DATA 0x66006666 -#define DDRSS_CTL_255_DATA 0x00002766 +#define DDRSS_CTL_254_DATA 0x46004646 +#define DDRSS_CTL_255_DATA 0x00002746 #define DDRSS_CTL_256_DATA 0x00000027 #define DDRSS_CTL_257_DATA 0x00000027 #define DDRSS_CTL_258_DATA 0x00000027 @@ -660,13 +660,13 @@ #define DDRSS_PI_220_DATA 0x000000A7 #define DDRSS_PI_221_DATA 0x00001900 #define DDRSS_PI_222_DATA 0x32000056 -#define DDRSS_PI_223_DATA 0x06000301 +#define DDRSS_PI_223_DATA 0x06000101 #define DDRSS_PI_224_DATA 0x001D0204 #define DDRSS_PI_225_DATA 0x32120059 -#define DDRSS_PI_226_DATA 0x05000301 +#define DDRSS_PI_226_DATA 0x05000101 #define DDRSS_PI_227_DATA 0x001D0409 #define DDRSS_PI_228_DATA 0x32120059 -#define DDRSS_PI_229_DATA 0x05000301 +#define DDRSS_PI_229_DATA 0x05000101 #define DDRSS_PI_230_DATA 0x00000409 #define DDRSS_PI_231_DATA 0x05030900 #define DDRSS_PI_232_DATA 0x00040900 @@ -748,7 +748,7 @@ #define DDRSS_PI_308_DATA 0x00000031 #define DDRSS_PI_309_DATA 0x00000000 #define DDRSS_PI_310_DATA 0x00000000 -#define DDRSS_PI_311_DATA 0x66000000 +#define DDRSS_PI_311_DATA 0x46000000 #define DDRSS_PI_312_DATA 0x00150F27 #define DDRSS_PI_313_DATA 0x00000000 #define DDRSS_PI_314_DATA 0x00000024 @@ -756,7 +756,7 @@ #define DDRSS_PI_316_DATA 0x00000031 #define DDRSS_PI_317_DATA 0x00000000 #define DDRSS_PI_318_DATA 0x00000000 -#define DDRSS_PI_319_DATA 0x66000000 +#define DDRSS_PI_319_DATA 0x46000000 #define DDRSS_PI_320_DATA 0x00150F27 #define DDRSS_PI_321_DATA 0x00000000 #define DDRSS_PI_322_DATA 0x00000004 @@ -772,7 +772,7 @@ #define DDRSS_PI_332_DATA 0x00000031 #define DDRSS_PI_333_DATA 0x00000000 #define DDRSS_PI_334_DATA 0x00000000 -#define DDRSS_PI_335_DATA 0x66000000 +#define DDRSS_PI_335_DATA 0x46000000 #define DDRSS_PI_336_DATA 0x00150F27 #define DDRSS_PI_337_DATA 0x00000000 #define DDRSS_PI_338_DATA 0x00000024 @@ -780,7 +780,7 @@ #define DDRSS_PI_340_DATA 0x00000031 #define DDRSS_PI_341_DATA 0x00000000 #define DDRSS_PI_342_DATA 0x00000000 -#define DDRSS_PI_343_DATA 0x66000000 +#define DDRSS_PI_343_DATA 0x46000000 #define DDRSS_PI_344_DATA 0x00150F27 #define DDRSS_PHY_0_DATA 0x04F00000 #define DDRSS_PHY_1_DATA 0x00000000 @@ -873,7 +873,7 @@ #define DDRSS_PHY_88_DATA 0x51516041 #define DDRSS_PHY_89_DATA 0x31C06000 #define DDRSS_PHY_90_DATA 0x07AB0340 -#define DDRSS_PHY_91_DATA 0x0100C0C0 +#define DDRSS_PHY_91_DATA 0x0000C0C0 #define DDRSS_PHY_92_DATA 0x03040000 #define DDRSS_PHY_93_DATA 0x00000403 #define DDRSS_PHY_94_DATA 0x42100010 @@ -1129,7 +1129,7 @@ #define DDRSS_PHY_344_DATA 0x51516041 #define DDRSS_PHY_345_DATA 0x31C06000 #define DDRSS_PHY_346_DATA 0x07AB0340 -#define DDRSS_PHY_347_DATA 0x0100C0C0 +#define DDRSS_PHY_347_DATA 0x0000C0C0 #define DDRSS_PHY_348_DATA 0x03040000 #define DDRSS_PHY_349_DATA 0x00000403 #define DDRSS_PHY_350_DATA 0x42100010 @@ -2157,7 +2157,7 @@ #define DDRSS_PHY_1372_DATA 0x00000002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 -#define DDRSS_PHY_1375_DATA 0x030207AB +#define DDRSS_PHY_1375_DATA 0x03020000 #define DDRSS_PHY_1376_DATA 0x00000080 #define DDRSS_PHY_1377_DATA 0x03900390 #define DDRSS_PHY_1378_DATA 0x03900390
On Mon, Nov 29, 2021 at 05:34:49PM +0530, Sinthu Raja wrote:
From: Sinthu Raja sinthu.raja@ti.com
EMIF tool for AM64 SK is now updated to 0.8.0 that includes
- disabled Write DQ training
- improve CA ODT to 60 ohms
The lpddr4 enabled with periodic WDQ training is causing periodic 26us stall. This makes the SoC stall without doing anything which leads to R5 interrupt latency in TCM memory. Due to this periodic training there are some outstanding CPU transactions waiting for the lpddr4 to complete.
Hence, disable the periodic write DQ training during the non-initialization stage of lpddr4 which results in an approximate 1us stall. Also, update the lpddr4 config to improve CA ODT by 60 ohms
The rationales are as follows:
PI_WDQLVL_EN: 2 Bits register field to support write DQ leveling, disable bit 1 that supports Write DQ during non-initialization to avoid ~26us stall during code execution.
MR11_DATA_F1/F2_x register fields value changed to 0x66 that changes the CA ODT from 48ohm to 60ohm to improve the eye margin on CA bus by increasing the signal swing.
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Sinthu Raja sinthu.raja@ti.com
arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi | 28 ++++++++++++------------
Have all of these updates been pushed to Linux? Thanks!
On Sat, Jan 15, 2022 at 9:04 PM Tom Rini trini@konsulko.com wrote:
On Mon, Nov 29, 2021 at 05:34:49PM +0530, Sinthu Raja wrote:
From: Sinthu Raja sinthu.raja@ti.com
EMIF tool for AM64 SK is now updated to 0.8.0 that includes
- disabled Write DQ training
- improve CA ODT to 60 ohms
The lpddr4 enabled with periodic WDQ training is causing periodic 26us stall. This makes the SoC stall without doing anything which leads to R5 interrupt latency in TCM memory. Due to this periodic training there are some outstanding CPU transactions waiting for the lpddr4 to complete.
Hence, disable the periodic write DQ training during the non-initialization stage of lpddr4 which results in an approximate 1us stall. Also, update the lpddr4 config to improve CA ODT by 60 ohms
The rationales are as follows:
PI_WDQLVL_EN: 2 Bits register field to support write DQ leveling, disable bit 1 that supports Write DQ during non-initialization to avoid ~26us stall during code execution.
MR11_DATA_F1/F2_x register fields value changed to 0x66 that changes the CA ODT from 48ohm to 60ohm to improve the eye margin on CA bus by increasing the signal swing.
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Sinthu Raja sinthu.raja@ti.com
arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi | 28 ++++++++++++------------
Have all of these updates been pushed to Linux? Thanks!
Tom, These changes are specific to u-boot. And it not requires any change in Linux.
-- Tom
On Wed, Feb 09, 2022 at 01:35:58PM +0530, Sinthu Raja M wrote:
On Sat, Jan 15, 2022 at 9:04 PM Tom Rini trini@konsulko.com wrote:
On Mon, Nov 29, 2021 at 05:34:49PM +0530, Sinthu Raja wrote:
From: Sinthu Raja sinthu.raja@ti.com
EMIF tool for AM64 SK is now updated to 0.8.0 that includes
- disabled Write DQ training
- improve CA ODT to 60 ohms
The lpddr4 enabled with periodic WDQ training is causing periodic 26us stall. This makes the SoC stall without doing anything which leads to R5 interrupt latency in TCM memory. Due to this periodic training there are some outstanding CPU transactions waiting for the lpddr4 to complete.
Hence, disable the periodic write DQ training during the non-initialization stage of lpddr4 which results in an approximate 1us stall. Also, update the lpddr4 config to improve CA ODT by 60 ohms
The rationales are as follows:
PI_WDQLVL_EN: 2 Bits register field to support write DQ leveling, disable bit 1 that supports Write DQ during non-initialization to avoid ~26us stall during code execution.
MR11_DATA_F1/F2_x register fields value changed to 0x66 that changes the CA ODT from 48ohm to 60ohm to improve the eye margin on CA bus by increasing the signal swing.
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Sinthu Raja sinthu.raja@ti.com
arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi | 28 ++++++++++++------------
Have all of these updates been pushed to Linux? Thanks!
Tom, These changes are specific to u-boot. And it not requires any change in Linux.
OK, thanks.
On Mon, Nov 29, 2021 at 05:34:49PM +0530, Sinthu Raja wrote:
From: Sinthu Raja sinthu.raja@ti.com
EMIF tool for AM64 SK is now updated to 0.8.0 that includes
- disabled Write DQ training
- improve CA ODT to 60 ohms
The lpddr4 enabled with periodic WDQ training is causing periodic 26us stall. This makes the SoC stall without doing anything which leads to R5 interrupt latency in TCM memory. Due to this periodic training there are some outstanding CPU transactions waiting for the lpddr4 to complete.
Hence, disable the periodic write DQ training during the non-initialization stage of lpddr4 which results in an approximate 1us stall. Also, update the lpddr4 config to improve CA ODT by 60 ohms
The rationales are as follows:
PI_WDQLVL_EN: 2 Bits register field to support write DQ leveling, disable bit 1 that supports Write DQ during non-initialization to avoid ~26us stall during code execution.
MR11_DATA_F1/F2_x register fields value changed to 0x66 that changes the CA ODT from 48ohm to 60ohm to improve the eye margin on CA bus by increasing the signal swing.
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Sinthu Raja sinthu.raja@ti.com
Applied to u-boot/master, thanks!
participants (3)
-
Sinthu Raja -
Sinthu Raja M
-
Tom Rini