Move the SR3 bit definition in the right place. Fix what is likely a rebase artifact. No functional change.

Fixes: 215f1d5794c6 ("mtd: spi-nor: Clear Winbond SR3 WPS bit on boot") Signed-off-by: Marek Vasut marex@denx.de --- Cc: Hai Pham hai.pham.ud@renesas.com Cc: Heinrich Schuchardt xypron.glpk@gmx.de Cc: Jagan Teki jagan@amarulasolutions.com Cc: Johann Neuhauser jneuhauser@dh-electronics.com Cc: Simon Glass sjg@chromium.org Cc: Takahiro Kuwano Takahiro.Kuwano@infineon.com Cc: Tom Rini trini@konsulko.com Cc: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com Cc: Vignesh R vigneshr@ti.com --- include/linux/mtd/spi-nor.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 1ae586b2e5f..655a6d197ea 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -182,15 +182,15 @@ /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT7 BIT(7)

+/* Status Register 3 bits. */ +#define SR3_WPS BIT(2) + /* * Maximum number of flashes that can be connected * in stacked/parallel configuration */ #define SNOR_FLASH_CNT_MAX 2

-/* Status Register 3 bits. */ -#define SR3_WPS BIT(2) - /* For Cypress flash. */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */