From: Peng Fan peng.fan@nxp.com

The return value is int type, not sc_err_t(u8), correct the usage.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/cmd_dek.c | 2 +- arch/arm/mach-imx/imx8/ahab.c | 10 +- arch/arm/mach-imx/imx8/cpu.c | 6 +- arch/arm/mach-imx/imx8/fdt.c | 2 +- arch/arm/mach-imx/imx8/snvs_security_sc.c | 175 +++++++++--------- .../power/domain/imx8-power-domain-legacy.c | 9 +- 6 files changed, 98 insertions(+), 106 deletions(-)

diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 69ed57537b3..d77a49df860 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -154,7 +154,7 @@ error:

static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) { - sc_err_t err; + int err; sc_rm_mr_t mr_input, mr_output; struct generate_key_blob_hdr hdr; u8 in_size, out_size; diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 9addb824b6d..86b0e0b755f 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -147,7 +147,7 @@ int authenticate_os_container(ulong addr) }

exit: - if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0) != SC_ERR_NONE) + if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0)) printf("Error: release container failed!\n");

return ret; @@ -263,7 +263,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, u16 lc;

err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); - if (err != SC_ERR_NONE) { + if (err) { printf("Error in get lifecycle\n"); return -EIO; } @@ -271,7 +271,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, display_life_cycle(lc);

err = sc_seco_get_event(-1, idx, &event); - while (err == SC_ERR_NONE) { + while (!err) { printf("SECO Event[%u] = 0x%08X\n", idx, event); display_ahab_auth_event(event);

@@ -312,7 +312,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, return -EACCES;

err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); - if (err != SC_ERR_NONE) { + if (err) { printf("Error in get lifecycle\n"); return -EIO; } @@ -324,7 +324,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, }

err = sc_seco_forward_lifecycle(-1, 16); - if (err != SC_ERR_NONE) { + if (err) { printf("Error in forward lifecycle to OEM closed\n"); return -EIO; } diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 7b292c07ef9..2b34077438f 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -195,7 +195,7 @@ enum boot_device get_boot_device(void) #define FUSE_UNIQUE_ID_WORD1 17 void get_board_serial(struct tag_serialnr *serialnr) { - sc_err_t err; + int err; u32 val1 = 0, val2 = 0; u32 word1, word2;

@@ -206,13 +206,13 @@ void get_board_serial(struct tag_serialnr *serialnr) word2 = FUSE_UNIQUE_ID_WORD1;

err = sc_misc_otp_fuse_read(-1, word1, &val1); - if (err != SC_ERR_NONE) { + if (err) { printf("%s fuse %d read error: %d\n", __func__, word1, err); return; }

err = sc_misc_otp_fuse_read(-1, word2, &val2); - if (err != SC_ERR_NONE) { + if (err) { printf("%s fuse %d read error: %d\n", __func__, word2, err); return; } diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c index 02b3ee5c111..491c8bb8c75 100644 --- a/arch/arm/mach-imx/imx8/fdt.c +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -110,7 +110,7 @@ static int config_smmu_resource_sid(int rsrc, int sid)

err = sc_rm_set_master_sid(-1, rsrc, sid); debug("set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err); - if (err != SC_ERR_NONE) { + if (err) { if (!check_owned_resource(rsrc)) { printf("%s rsrc[%d] not owned\n", __func__, rsrc); return -1; diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c index d7b20a1fcbf..1eaa68f8d5f 100644 --- a/arch/arm/mach-imx/imx8/snvs_security_sc.c +++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c @@ -286,16 +286,15 @@ static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2, u32 *_p3, u32 *_p4, u32 *_p5, u32 _cnt) { - int scierr = 0; + int err; u32 d1 = ptr_value(_p1); u32 d2 = ptr_value(_p2); u32 d3 = ptr_value(_p3); u32 d4 = ptr_value(_p4); u32 d5 = ptr_value(_p5);

- scierr = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3, - &d4, &d4, _cnt); - if (scierr != SC_ERR_NONE) { + err = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3, &d4, &d4, _cnt); + if (err) { printf("Failed to set secvio configuration\n"); debug("Failed to set conf id 0x%x with values ", id); debug("0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x (cnt: %d)\n", @@ -315,7 +314,7 @@ static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2, *(u32 *)_p5 = d5;

exit: - return scierr; + return err; }

#define SC_CHECK_WRITE1(id, _p1) \ @@ -323,7 +322,7 @@ exit:

static int apply_snvs_config(struct snvs_security_sc_conf *cnf) { - int scierr = 0; + int err = 0;

debug("%s\n", __func__);

@@ -365,92 +364,88 @@ static int apply_snvs_config(struct snvs_security_sc_conf *cnf) cnf->lp.act_tamper_routing_ctl1, cnf->lp.act_tamper_routing_ctl2);

- scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg), - &cnf->lp.tamper_filt_cfg, - &cnf->lp.tamper_filt1_cfg, - &cnf->lp.tamper_filt2_cfg, NULL, - NULL, 3); - if (scierr != SC_ERR_NONE) + err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg), + &cnf->lp.tamper_filt_cfg, + &cnf->lp.tamper_filt1_cfg, + &cnf->lp.tamper_filt2_cfg, + NULL, NULL, 3); + if (err) goto exit;

/* Configure AT */ - scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg), - &cnf->lp.act_tamper1_cfg, - &cnf->lp.act_tamper2_cfg, - &cnf->lp.act_tamper2_cfg, - &cnf->lp.act_tamper2_cfg, - &cnf->lp.act_tamper2_cfg, 5); - if (scierr != SC_ERR_NONE) + err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg), + &cnf->lp.act_tamper1_cfg, + &cnf->lp.act_tamper2_cfg, + &cnf->lp.act_tamper2_cfg, + &cnf->lp.act_tamper2_cfg, + &cnf->lp.act_tamper2_cfg, 5); + if (err) goto exit;

/* Configure AT routing */ - scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1), - &cnf->lp.act_tamper_routing_ctl1, - &cnf->lp.act_tamper_routing_ctl2, - NULL, NULL, NULL, 2); - if (scierr != SC_ERR_NONE) + err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1), + &cnf->lp.act_tamper_routing_ctl1, + &cnf->lp.act_tamper_routing_ctl2, + NULL, NULL, NULL, 2); + if (err) goto exit;

/* Configure AT frequency */ - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl), - &cnf->lp.act_tamper_clk_ctl); - if (scierr != SC_ERR_NONE) + err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl), + &cnf->lp.act_tamper_clk_ctl); + if (err) goto exit;

/* Activate the ATs */ - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl), - &cnf->lp.act_tamper_ctl); - if (scierr != SC_ERR_NONE) + err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl), &cnf->lp.act_tamper_ctl); + if (err) goto exit;

/* Activate the detectors */ - scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg), - &cnf->lp.tamper_det_cfg, - &cnf->lp.tamper_det_cfg2, NULL, NULL, - NULL, 2); - if (scierr != SC_ERR_NONE) + err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg), + &cnf->lp.tamper_det_cfg, + &cnf->lp.tamper_det_cfg2, NULL, NULL, NULL, 2); + if (err) goto exit;

/* Configure LP secvio */ - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl), - &cnf->lp.secvio_ctl); - if (scierr != SC_ERR_NONE) + err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl), &cnf->lp.secvio_ctl); + if (err) goto exit;

/* Configure HP secvio */ - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl), - &cnf->hp.secvio_ctl); - if (scierr != SC_ERR_NONE) + err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl), &cnf->hp.secvio_ctl); + if (err) goto exit;

/* Lock access */ - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock); - if (scierr != SC_ERR_NONE) + err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock); + if (err) goto exit;

- scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock); - if (scierr != SC_ERR_NONE) + err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock); + if (err) goto exit;

exit: - return (scierr == SC_ERR_NONE) ? 0 : -EIO; + return err; }

static int dgo_write(u32 _id, u8 _access, u32 *_pdata) { - int scierr = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata); + int err = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata);

- if (scierr != SC_ERR_NONE) { + if (err) { printf("Failed to set dgo configuration\n"); debug("Failed to set conf id 0x%x : 0x%.8x", _id, *_pdata); }

- return scierr; + return err; }

static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf) { - int scierr = 0; + int err;

debug("%s\n", __func__);

@@ -468,50 +463,50 @@ static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf) cnf->tamper_misc_ctl, cnf->tamper_core_volt_mon_ctl);

- dgo_write(0x04, 1, &cnf->tamper_offset_ctl); - if (scierr != SC_ERR_NONE) + err = dgo_write(0x04, 1, &cnf->tamper_offset_ctl); + if (err) goto exit;

- dgo_write(0x14, 1, &cnf->tamper_pull_ctl); - if (scierr != SC_ERR_NONE) + err = dgo_write(0x14, 1, &cnf->tamper_pull_ctl); + if (err) goto exit;

- dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl); - if (scierr != SC_ERR_NONE) + err = dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl); + if (err) goto exit;

- dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl); - if (scierr != SC_ERR_NONE) + err = dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl); + if (err) goto exit;

- dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl); - if (scierr != SC_ERR_NONE) + err = dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl); + if (err) goto exit;

/* Last as it could lock the writes */ - dgo_write(0x44, 1, &cnf->tamper_misc_ctl); - if (scierr != SC_ERR_NONE) + err = dgo_write(0x44, 1, &cnf->tamper_misc_ctl); + if (err) goto exit;

exit: - return (scierr == SC_ERR_NONE) ? 0 : -EIO; + return err; }

static int pad_write(u32 _pad, u32 _value) { - int scierr = sc_pad_set(-1, _pad, _value); + int err = sc_pad_set(-1, _pad, _value);

- if (scierr != SC_ERR_NONE) { + if (err) { printf("Failed to set pad configuration\n"); debug("Failed to set conf pad 0x%x : 0x%.8x", _pad, _value); }

- return scierr; + return err; }

static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size) { - int scierr = 0; + int err = 0; u32 idx;

debug("%s\n", __func__); @@ -519,13 +514,13 @@ static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size) for (idx = 0; idx < size; idx++) { debug("\t idx %d: pad %d: 0x%.8x\n", idx, confs[idx].pad, confs[idx].mux_conf); - pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf); - if (scierr != SC_ERR_NONE) + err = pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf); + if (err) goto exit; }

exit: - return (scierr == SC_ERR_NONE) ? 0 : -EIO; + return err; }

int examples(void) @@ -753,7 +748,7 @@ static char snvs_clear_status_help_text[] = static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - int scierr = 0; + int err; u32 idx = 0;

struct snvs_security_sc_conf conf = {0}; @@ -764,20 +759,18 @@ static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc, conf.lp.status = hextoul(argv[++idx], NULL); conf.lp.tamper_det_status = hextoul(argv[++idx], NULL);

- scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status), - &conf.lp.status, NULL, NULL, NULL, - NULL, 1); - if (scierr != SC_ERR_NONE) + err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status), + &conf.lp.status, NULL, NULL, NULL, NULL, 1); + if (err) goto exit;

- scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status), - &conf.lp.tamper_det_status, NULL, - NULL, NULL, NULL, 1); - if (scierr != SC_ERR_NONE) + err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status), + &conf.lp.tamper_det_status, NULL, NULL, NULL, NULL, 1); + if (err) goto exit;

exit: - return (scierr == SC_ERR_NONE) ? 0 : 1; + return err; }

U_BOOT_CMD(snvs_clear_status, @@ -793,7 +786,7 @@ static char snvs_sec_status_help_text[] = static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - int scierr; + int err; u32 idx;

u32 data[5]; @@ -864,8 +857,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, for (idx = 0; idx < ARRAY_SIZE(pads); idx++) { u8 pad_id = pads[idx];

- scierr = sc_pad_get(-1, pad_id, &data[0]); - if (scierr == 0) + err = sc_pad_get(-1, pad_id, &data[0]); + if (!err) printf("\t- Pin %d: %.8x\n", pad_id, data[0]); else printf("Failed to read Pin %d\n", pad_id); @@ -876,8 +869,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, for (idx = 0; idx < ARRAY_SIZE(fuses); idx++) { u32 fuse_id = fuses[idx];

- scierr = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]); - if (scierr == 0) + err = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]); + if (!err) printf("\t- Fuse %d: %.8x\n", fuse_id, data[0]); else printf("Failed to read Fuse %d\n", fuse_id); @@ -888,10 +881,10 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, for (idx = 0; idx < ARRAY_SIZE(snvs); idx++) { struct snvs_reg *reg = &snvs[idx];

- scierr = sc_seco_secvio_config(-1, reg->id, 0, &data[0], - &data[1], &data[2], &data[3], - &data[4], reg->nb); - if (scierr == 0) { + err = sc_seco_secvio_config(-1, reg->id, 0, &data[0], + &data[1], &data[2], &data[3], + &data[4], reg->nb); + if (!err) { int subidx;

printf("\t- SNVS %.2x(%d):", reg->id, reg->nb); @@ -908,8 +901,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, for (idx = 0; idx < ARRAY_SIZE(dgo); idx++) { u8 dgo_id = dgo[idx];

- scierr = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]); - if (scierr == 0) + err = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]); + if (!err) printf("\t- DGO %.2x: %.8x\n", dgo_id, data[0]); else printf("Failed to read DGO %d\n", dgo_id); diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c index 37b0f95abac..c8ca2665752 100644 --- a/drivers/power/domain/imx8-power-domain-legacy.c +++ b/drivers/power/domain/imx8-power-domain-legacy.c @@ -89,7 +89,6 @@ static int imx8_power_domain_on(struct power_domain *power_domain) struct udevice *dev = power_domain->dev; struct imx8_power_domain_plat *pdata; struct imx8_power_domain_priv *ppriv; - sc_err_t ret; int err;

struct power_domain parent_domain; @@ -117,11 +116,11 @@ static int imx8_power_domain_on(struct power_domain *power_domain) if (!sc_rm_is_resource_owned(-1, pdata->resource_id)) printf("%s [%d] not owned by curr partition\n", dev->name, pdata->resource_id);

- ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id, + err = sc_pm_set_resource_power_mode(-1, pdata->resource_id, SC_PM_PW_MODE_ON); - if (ret) { + if (err) { printf("Error: %s Power up failed! (error = %d)\n", - dev->name, ret); + dev->name, err); return -EIO; } } @@ -139,7 +138,7 @@ static int imx8_power_domain_off_node(struct power_domain *power_domain) struct imx8_power_domain_priv *ppriv; struct imx8_power_domain_priv *child_ppriv; struct imx8_power_domain_plat *pdata; - sc_err_t ret; + int ret;

ppriv = dev_get_priv(dev); pdata = dev_get_plat(dev);

From: Peng Fan peng.fan@nxp.com

The return value is int type, not sc_err_t(u8), correct the usage.

Signed-off-by: Peng Fan peng.fan@nxp.com --- board/toradex/colibri-imx8x/colibri-imx8x.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 52fc7a391bb..29efd8c6a53 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -43,9 +43,9 @@ static void setup_iomux_uart(void) static int is_imx8dx(void) { u32 val = 0; - sc_err_t sc_err = sc_misc_otp_fuse_read(-1, 6, &val); + int sc_err = sc_misc_otp_fuse_read(-1, 6, &val);

- if (sc_err == SC_ERR_NONE) { + if (sc_err) { /* DX has two A35 cores disabled */ return (val & 0xf) != 0x0; } @@ -70,7 +70,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start, int board_early_init_f(void) { sc_pm_clock_rate_t rate; - sc_err_t err = 0; + int err;

/* * This works around that having only UART3 up the baudrate is 1.2M @@ -78,13 +78,13 @@ int board_early_init_f(void) */ rate = 80000000; err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate); - if (err != SC_ERR_NONE) + if (err) return 0;

/* Set UART3 clock root to 80 MHz and enable it */ rate = SC_80MHZ; err = sc_pm_setup_uart(SC_R_UART_3, rate); - if (err != SC_ERR_NONE) + if (err) return 0;

setup_iomux_uart();

From: Peng Fan peng.fan@nxp.com

The return value is int type, not sc_err_t(u8), correct the usage.

Signed-off-by: Peng Fan peng.fan@nxp.com --- board/advantech/imx8qm_dmsse20_a1/spl.c | 6 +++--- board/advantech/imx8qm_rom7720_a1/spl.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c index 7f2e972425b..f36caece7d7 100644 --- a/board/advantech/imx8qm_dmsse20_a1/spl.c +++ b/board/advantech/imx8qm_dmsse20_a1/spl.c @@ -111,7 +111,7 @@ int board_mmc_init(struct bd_info *bis) switch (i) { case 0: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret;

imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); @@ -120,10 +120,10 @@ int board_mmc_init(struct bd_info *bis) break; case 1: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret;

imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c index b602437c35b..922bb0b7d43 100644 --- a/board/advantech/imx8qm_rom7720_a1/spl.c +++ b/board/advantech/imx8qm_rom7720_a1/spl.c @@ -112,7 +112,7 @@ int board_mmc_init(struct bd_info *bis) switch (i) { case 0: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret;

imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); @@ -121,10 +121,10 @@ int board_mmc_init(struct bd_info *bis) break; case 1: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret;

imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));

From: Peng Fan peng.fan@nxp.com

The return value is int type, not sc_err_t(u8), correct the usage.

Signed-off-by: Peng Fan peng.fan@nxp.com --- board/congatec/cgtqmx8/cgtqmx8.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c index bedd1e03308..26189ff66f5 100644 --- a/board/congatec/cgtqmx8/cgtqmx8.c +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -79,7 +79,7 @@ static void setup_iomux_uart(void) int board_early_init_f(void) { /* sc_ipc_t ipcHndl = 0; */ - sc_err_t scierr = 0; + int scierr;

/* When start u-boot in XEN VM, directly return */ /* if (IS_ENABLED(CONFIG_XEN)) */ @@ -89,19 +89,19 @@ int board_early_init_f(void)

/* Power up UART0, this is very early while power domain is not working */ scierr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); - if (scierr != SC_ERR_NONE) + if (scierr) return 0;

/* Set UART0 clock root to 80 MHz */ sc_pm_clock_rate_t rate = 80000000;

scierr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); - if (scierr != SC_ERR_NONE) + if (scierr) return 0;

/* Enable UART0 clock root */ scierr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); - if (scierr != SC_ERR_NONE) + if (scierr) return 0;

setup_iomux_uart();

From: Peng Fan peng.fan@nxp.com

Upgrade SCFW API to 1.16 Add more APIs: sc_misc_get_button_status sc_pm_reboot sc_seco_v2x_build_info

Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/misc/imx8/scu_api.c | 78 ++++++++++++++++++++ include/firmware/imx/sci/rpc.h | 27 ++++--- include/firmware/imx/sci/sci.h | 24 ++++++ include/firmware/imx/sci/svc/misc/api.h | 42 ++++++++--- include/firmware/imx/sci/svc/pm/api.h | 94 ++++++++++++++++++++++++ include/firmware/imx/sci/svc/rm/api.h | 14 ++-- include/firmware/imx/sci/svc/seco/api.h | 5 +- include/firmware/imx/sci/svc/timer/api.h | 33 +++++++++ 8 files changed, 287 insertions(+), 30 deletions(-) create mode 100644 include/firmware/imx/sci/svc/timer/api.h

diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index dfede7f1d5f..3e3002ba6df 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -481,6 +481,22 @@ int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, return 0; }

+void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status) +{ + struct sc_rpc_msg_s msg; + struct udevice *dev = gd->arch.scu_dev; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = (u8)(MISC_FUNC_GET_BUTTON_STATUS); + + misc_call(dev, SC_FALSE, &msg, 1U, &msg, 1U); + + if (status) + *status = (sc_bool_t)(!!(RPC_U8(&msg, 0U))); +} + /* RM */ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) { @@ -851,6 +867,21 @@ int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, return ret; }

+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = (u8)(PM_FUNC_REBOOT); + RPC_U8(&msg, 0U) = (u8)(type); + RPC_SIZE(&msg) = 2U; + + misc_call(dev, SC_TRUE, &msg, size, &msg, size); +} + int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_power_mode_t *mode) { @@ -877,6 +908,28 @@ int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, return ret; }

+int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = (u8)(TIMER_FUNC_SET_WDOG_WINDOW); + + RPC_U32(&msg, 0U) = (u32)(window); + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: window:%u: res:%d\n", + __func__, window, RPC_R8(&msg)); + + return ret; +} + int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) { @@ -974,6 +1027,31 @@ void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) *commit = RPC_U32(&msg, 4U); }

+int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = (u8)(SECO_FUNC_V2X_BUILD_INFO); + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", __func__, RPC_R8(&msg)); + + if (version) + *version = RPC_U32(&msg, 0U); + + if (commit) + *commit = RPC_U32(&msg, 4U); + + return ret; +} + int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event) { struct udevice *dev = gd->arch.scu_dev; diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h index 39de7f0e3e0..85af6f3996e 100644 --- a/include/firmware/imx/sci/rpc.h +++ b/include/firmware/imx/sci/rpc.h @@ -23,12 +23,12 @@ #define RPC_FUNC(MSG) ((MSG)->func) #define RPC_R8(MSG) ((MSG)->func) #define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ - (s64)(RPC_U32((MSG), (IDX) + 4U)) + (s64)(RPC_U32((MSG), (IDX) + 4U)) #define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) #define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) #define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) #define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ - (u64)(RPC_U32((MSG), (IDX) + 4U)) + (u64)(RPC_U32((MSG), (IDX) + 4U)) #define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) #define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) #define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) @@ -67,7 +67,9 @@ struct sc_rpc_msg_s { #define PM_FUNC_SET_SYS_POWER_MODE 19U #define PM_FUNC_SET_PARTITION_POWER_MODE 1U #define PM_FUNC_GET_SYS_POWER_MODE 2U +#define PM_FUNC_PARTITION_WAKE 28U #define PM_FUNC_SET_RESOURCE_POWER_MODE 3U +#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL 22U #define PM_FUNC_GET_RESOURCE_POWER_MODE 4U #define PM_FUNC_REQ_LOW_POWER_MODE 16U #define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U @@ -81,13 +83,16 @@ struct sc_rpc_msg_s { #define PM_FUNC_GET_CLOCK_PARENT 15U #define PM_FUNC_RESET 13U #define PM_FUNC_RESET_REASON 10U +#define PM_FUNC_GET_RESET_PART 26U #define PM_FUNC_BOOT 8U +#define PM_FUNC_SET_BOOT_PARM 27U #define PM_FUNC_REBOOT 9U #define PM_FUNC_REBOOT_PARTITION 12U +#define PM_FUNC_REBOOT_CONTINUE 25U #define PM_FUNC_CPU_START 11U #define PM_FUNC_CPU_RESET 23U #define PM_FUNC_RESOURCE_RESET 29U -#define PM_FUNC_IS_PARTITION_STARTED 24U +#define PM_FUNC_IS_PARTITION_STARTED 24U

/* MISC RPC */ #define MISC_FUNC_UNKNOWN 0 @@ -95,16 +100,10 @@ struct sc_rpc_msg_s { #define MISC_FUNC_GET_CONTROL 2U #define MISC_FUNC_SET_MAX_DMA_GROUP 4U #define MISC_FUNC_SET_DMA_GROUP 5U -#define MISC_FUNC_SECO_IMAGE_LOAD 8U -#define MISC_FUNC_SECO_AUTHENTICATE 9U -#define MISC_FUNC_SECO_FUSE_WRITE 20U -#define MISC_FUNC_SECO_ENABLE_DEBUG 21U -#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U -#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U -#define MISC_FUNC_SECO_BUILD_INFO 24U #define MISC_FUNC_DEBUG_OUT 10U #define MISC_FUNC_WAVEFORM_CAPTURE 6U #define MISC_FUNC_BUILD_INFO 15U +#define MISC_FUNC_API_VER 35U #define MISC_FUNC_UNIQUE_ID 19U #define MISC_FUNC_SET_ARI 3U #define MISC_FUNC_BOOT_STATUS 7U @@ -114,8 +113,11 @@ struct sc_rpc_msg_s { #define MISC_FUNC_SET_TEMP 12U #define MISC_FUNC_GET_TEMP 13U #define MISC_FUNC_GET_BOOT_DEV 16U +#define MISC_FUNC_GET_BOOT_TYPE 33U +#define MISC_FUNC_GET_BOOT_CONTAINER 36U #define MISC_FUNC_GET_BUTTON_STATUS 18U -#define MISC_FUNC_GET_BOOT_CONTAINER 36U +#define MISC_FUNC_ROMPATCH_CHECKSUM 26U +#define MISC_FUNC_BOARD_IOCTL 34U

/* PAD RPC */ #define PAD_FUNC_UNKNOWN 0 @@ -160,6 +162,7 @@ struct sc_rpc_msg_s { #define RM_FUNC_GET_RESOURCE_INFO 16U #define RM_FUNC_MEMREG_ALLOC 17U #define RM_FUNC_MEMREG_SPLIT 29U +#define RM_FUNC_MEMREG_FRAG 32U #define RM_FUNC_MEMREG_FREE 18U #define RM_FUNC_FIND_MEMREG 30U #define RM_FUNC_ASSIGN_MEMREG 19U @@ -190,6 +193,7 @@ struct sc_rpc_msg_s { #define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */ #define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */ #define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */ +#define SECO_FUNC_V2X_BUILD_INFO 30U /* Index for sc_seco_v2x_build_info() RPC call */ #define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */ #define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */ #define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */ @@ -210,6 +214,7 @@ struct sc_rpc_msg_s { #define TIMER_FUNC_UNKNOWN 0 /* Unknown function */ #define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */ #define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */ +#define TIMER_FUNC_SET_WDOG_WINDOW 19U /* Index for sc_timer_set_wdog_window() RPC call */ #define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */ #define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */ #define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */ diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 61c8211b443..f832982b3de 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -13,6 +13,7 @@ #include <firmware/imx/sci/svc/pm/api.h> #include <firmware/imx/sci/svc/rm/api.h> #include <firmware/imx/sci/svc/seco/api.h> +#include <firmware/imx/sci/svc/timer/api.h> #include <firmware/imx/sci/rpc.h> #include <dt-bindings/soc/imx_rsrc.h> #include <linux/errno.h> @@ -73,6 +74,7 @@ int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clk_parent_t parent); int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, sc_faddr_t address); +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource);

@@ -88,6 +90,7 @@ void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, s16 *celsius, s8 *tenths); +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status);

/* RM API */ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); @@ -117,6 +120,9 @@ int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); /* SMMU API */ int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);

+/* Timer API */ +int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window); + /* SECO API */ int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr); @@ -124,6 +130,7 @@ int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change); int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, u32 *uid_h); void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); +int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event); int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, sc_faddr_t export_addr, u16 max_size); @@ -374,6 +381,23 @@ static inline int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, u32 *dat return -EOPNOTSUPP; }

+static inline void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) +{ +} + +static inline int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) +{ + return -EOPNOTSUPP; +} + +static inline void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status) +{ +} + +static inline int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) +{ + return -EOPNOTSUPP; +} #endif

#endif diff --git a/include/firmware/imx/sci/svc/misc/api.h b/include/firmware/imx/sci/svc/misc/api.h index 3629eb68d7a..a4b92b86cc6 100644 --- a/include/firmware/imx/sci/svc/misc/api.h +++ b/include/firmware/imx/sci/svc/misc/api.h @@ -5,27 +5,45 @@

#ifndef SC_MISC_API_H #define SC_MISC_API_H +/* Defines for type widths */ +#define SC_MISC_DMA_GRP_W 5U /* Width of sc_misc_dma_group_t */

+/* Max DMA channel priority group */ +#define SC_MISC_DMA_GRP_MAX 31U /* Defines for sc_misc_boot_status_t */ #define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */ #define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */

-/* Defines for sc_misc_seco_auth_cmd_t */ -#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */ -#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */ -#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */ - /* Defines for sc_misc_temp_t */ -#define SC_MISC_TEMP 0U /* Temp sensor */ -#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ -#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ +#define SC_MISC_TEMP 0U /* Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ + +/* Defines for sc_misc_bt_t */ +#define SC_MISC_BT_PRIMARY 0U /* Primary boot */ +#define SC_MISC_BT_SECONDARY 1U /* Secondary boot */ +#define SC_MISC_BT_RECOVERY 2U /* Recovery boot */ +#define SC_MISC_BT_MANUFACTURE 3U /* Manufacture boot */ +#define SC_MISC_BT_SERIAL 4U /* Serial boot */ +/* Types */

-/* Defines for sc_misc_seco_auth_cmd_t */ -#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */ -#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */ -#define SC_MISC_REL_CONTAINER 2U /* Release container */ +/* + * This type is used to store a DMA channel priority group. + */ +typedef u8 sc_misc_dma_group_t;

+/* + * This type is used report boot status. + */ typedef u8 sc_misc_boot_status_t; + +/* + * This type is used report boot status. + */ typedef u8 sc_misc_temp_t;

+/* + * This type is used report the boot type. + */ +typedef u8 sc_misc_bt_t; #endif /* SC_MISC_API_H */ diff --git a/include/firmware/imx/sci/svc/pm/api.h b/include/firmware/imx/sci/svc/pm/api.h index 9008b85c6f6..d1b085d7f87 100644 --- a/include/firmware/imx/sci/svc/pm/api.h +++ b/include/firmware/imx/sci/svc/pm/api.h @@ -6,6 +6,14 @@ #ifndef SC_PM_API_H #define SC_PM_API_H

+#include <firmware/imx/sci/types.h> +/* Defines for type widths */ +#define SC_PM_POWER_MODE_W 2U /* Width of sc_pm_power_mode_t */ +#define SC_PM_CLOCK_MODE_W 3U /* Width of sc_pm_clock_mode_t */ +#define SC_PM_RESET_TYPE_W 2U /* Width of sc_pm_reset_type_t */ +#define SC_PM_RESET_REASON_W 4U /* Width of sc_pm_reset_reason_t */ +/* Defines for ALL parameters */ +#define SC_PM_CLK_ALL ((sc_pm_clk_t)UINT8_MAX) /* All clocks */ /* Defines for sc_pm_power_mode_t */ #define SC_PM_PW_MODE_OFF 0U /* Power off */ #define SC_PM_PW_MODE_STBY 1U /* Power in standby */ @@ -35,10 +43,96 @@ #define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ #define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */

+/* Defines for sc_pm_clk_parent_t */ +#define SC_PM_PARENT_XTAL 0U /*!< Parent is XTAL. */ +#define SC_PM_PARENT_PLL0 1U /*!< Parent is PLL0 */ +#define SC_PM_PARENT_PLL1 2U /*!< Parent is PLL1 or PLL0/2 */ +#define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or PLL0/4 */ +#define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass clock. */ + +/* Defines for sc_pm_reset_type_t */ +#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */ +#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */ +#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */ + +/* Defines for sc_pm_reset_reason_t */ +#define SC_PM_RESET_REASON_POR 0U /* Power on reset */ +#define SC_PM_RESET_REASON_JTAG 1U /* JTAG reset */ +#define SC_PM_RESET_REASON_SW 2U /* Software reset */ +#define SC_PM_RESET_REASON_WDOG 3U /* Partition watchdog reset */ +#define SC_PM_RESET_REASON_LOCKUP 4U /* SCU lockup reset */ +#define SC_PM_RESET_REASON_SNVS 5U /* SNVS reset */ +#define SC_PM_RESET_REASON_TEMP 6U /* Temp panic reset */ +#define SC_PM_RESET_REASON_MSI 7U /* MSI reset */ +#define SC_PM_RESET_REASON_UECC 8U /* ECC reset */ +#define SC_PM_RESET_REASON_SCFW_WDOG 9U /* SCFW watchdog reset */ +#define SC_PM_RESET_REASON_ROM_WDOG 10U /* SCU ROM watchdog reset */ +#define SC_PM_RESET_REASON_SECO 11U /* SECO reset */ +#define SC_PM_RESET_REASON_SCFW_FAULT 12U /* SCFW fault reset */ + +/* Defines for sc_pm_sys_if_t */ +#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */ +#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */ +#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */ +#define SC_PM_SYS_IF_DDR 3U /* DDR memory */ + +/* Defines for sc_pm_wake_src_t */ +/* No wake source, used for self-kill */ +#define SC_PM_WAKE_SRC_NONE 0U +/* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */ +#define SC_PM_WAKE_SRC_SCU 1U +/* Wakeup from IRQSTEER to resume CPU (GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER 2U +/* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */ +#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U +/* Wakeup from GIC to wake CPU */ +#define SC_PM_WAKE_SRC_GIC 4U +/* Types */ + +/* + * This type is used to declare a power mode. Note resources only use + * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only + * as system power modes. + */ typedef u8 sc_pm_power_mode_t; + +/* + * This type is used to declare a clock. + */ typedef u8 sc_pm_clk_t; + +/* + * This type is used to declare a clock mode. + */ typedef u8 sc_pm_clk_mode_t; + +/* + * This type is used to declare the clock parent. + */ typedef u8 sc_pm_clk_parent_t; + +/* + * This type is used to declare clock rates. + */ typedef u32 sc_pm_clock_rate_t;

+/* + * This type is used to declare a desired reset type. + */ +typedef u8 sc_pm_reset_type_t; + +/* + * This type is used to declare a reason for a reset. + */ +typedef u8 sc_pm_reset_reason_t; + +/* + * This type is used to specify a system-level interface to be power managed. + */ +typedef u8 sc_pm_sys_if_t; + +/* + * This type is used to specify a wake source for CPU resources. + */ +typedef u8 sc_pm_wake_src_t; #endif /* SC_PM_API_H */ diff --git a/include/firmware/imx/sci/svc/rm/api.h b/include/firmware/imx/sci/svc/rm/api.h index 163d81403c5..f4e9abcd9b3 100644 --- a/include/firmware/imx/sci/svc/rm/api.h +++ b/include/firmware/imx/sci/svc/rm/api.h @@ -38,32 +38,36 @@

/* Types */

-/*! +/* * This type is used to declare a resource partition. */ typedef u8 sc_rm_pt_t;

-/*! +/* * This type is used to declare a memory region. */ typedef u8 sc_rm_mr_t;

-/*! +/* * This type is used to declare a resource domain ID used by the * isolation HW. */ typedef u8 sc_rm_did_t;

-/*! +/* * This type is used to declare an SMMU StreamID. */ typedef u16 sc_rm_sid_t;

-/*! +/* * This type is a used to declare master transaction attributes. */ typedef u8 sc_rm_spa_t;

+/* + * This type is used to declare a resource/memory region access permission. + * Refer to the XRDC2 Block Guide for more information. + */ typedef u8 sc_rm_perm_t;

#endif /* SC_RM_API_H */ diff --git a/include/firmware/imx/sci/svc/seco/api.h b/include/firmware/imx/sci/svc/seco/api.h index 6e9c302315b..7d4b6b92e17 100644 --- a/include/firmware/imx/sci/svc/seco/api.h +++ b/include/firmware/imx/sci/svc/seco/api.h @@ -17,6 +17,7 @@ #define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */ #define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */ #define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */ +#define SC_SECO_EVERIFY_IMAGE 6U /* Enhanced verify image */

#define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */ #define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */ @@ -24,12 +25,12 @@

/* Types */

-/*! +/* * This type is used to issue SECO authenticate commands. */ typedef u8 sc_seco_auth_cmd_t;

-/*! +/* * This type is used to return the RNG initialization status. */ typedef u32 sc_seco_rng_stat_t; diff --git a/include/firmware/imx/sci/svc/timer/api.h b/include/firmware/imx/sci/svc/timer/api.h new file mode 100644 index 00000000000..c2fe34aa751 --- /dev/null +++ b/include/firmware/imx/sci/svc/timer/api.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + */ + +#ifndef SC_TIMER_API_H +#define SC_TIMER_API_H + +/* Defines */ + +/* Defines for type widths */ +#define SC_TIMER_ACTION_W 3U /* Width of sc_timer_wdog_action_t */ + +/* Defines for sc_timer_wdog_action_t */ +#define SC_TIMER_WDOG_ACTION_PARTITION 0U /* Reset partition */ +#define SC_TIMER_WDOG_ACTION_WARM 1U /* Warm reset system */ +#define SC_TIMER_WDOG_ACTION_COLD 2U /* Cold reset system */ +#define SC_TIMER_WDOG_ACTION_BOARD 3U /* Reset board */ +#define SC_TIMER_WDOG_ACTION_IRQ 4U /* Only generate IRQs */ + +/* Types */ + +/* + * This type is used to configure the watchdog action. + */ +typedef u8 sc_timer_wdog_action_t; + +/* + * This type is used to declare a watchdog time value in milliseconds. + */ +typedef u32 sc_timer_wdog_time_t; + +#endif /* SC_TIMER_API_H */

From: Peng Fan peng.fan@nxp.com

Fix build warning: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 3 has type ‘u64’ {aka ‘long long unsigned int’} [-Wformat=] printf("can't find memreg for image %d load address 0x%x, error %d\n", warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘sc_faddr_t’ {aka ‘long long unsigned int’} [-Wformat=] debug("memreg %u 0x%lx -- 0x%lx\n", mr, start, end);

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/parse-container.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/parse-container.c b/arch/arm/mach-imx/parse-container.c index f7582825d6d..a0d1eb3831c 100644 --- a/arch/arm/mach-imx/parse-container.c +++ b/arch/arm/mach-imx/parse-container.c @@ -35,14 +35,14 @@ static int authenticate_image(struct boot_img_t *img, int image_index) ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1);

if (err) { - printf("can't find memreg for image %d load address 0x%x, error %d\n", + printf("can't find memreg for image %d load address 0x%llx, error %d\n", image_index, img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), err); return -ENOMEM; }

err = sc_rm_get_memreg_info(-1, mr, &start, &end); if (!err) - debug("memreg %u 0x%x -- 0x%x\n", mr, start, end); + debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);

err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT, SC_RM_PERM_FULL);

From: Peng Fan peng.fan@nxp.com

Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/mach-imx/ele_api.h | 2 + arch/arm/mach-imx/ele_ahab.c | 74 +++++++++++++++++++++++++ drivers/misc/imx_ele/ele_api.c | 64 ++++++++++++++++++++- 3 files changed, 139 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 120da0854e4..477cfe73ab0 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -146,5 +146,7 @@ int ele_dump_buffer(u32 *buffer, u32 buffer_length); int ele_get_info(struct ele_get_info_data *info, u32 *response); int ele_get_fw_status(u32 *status, u32 *response); int ele_release_m33_trout(void); +int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response); +int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response);

#endif diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 5f23486304c..785b0d6ec3c 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -563,6 +563,68 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const return 0; }

+static int do_sec_fuse_prog(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + ulong addr; + u32 header, response; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = hextoul(argv[1], NULL); + header = *(u32 *)addr; + + if ((header & 0xff0000ff) != 0x89000000) { + printf("Wrong Signed message block format, header 0x%x\n", header); + return CMD_RET_FAILURE; + } + + header = (header & 0xffff00) >> 8; + + printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header); + flush_dcache_range(addr, addr + header - 1); + + if (ele_write_secure_fuse(addr, &response)) { + printf("Program secure fuse failed, response 0x%x\n", response); + return CMD_RET_FAILURE; + } + + printf("Program secure fuse completed, response 0x%x\n", response); + + return CMD_RET_SUCCESS; +} + +static int do_ahab_return_lifecycle(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + ulong addr; + u32 header, response; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = hextoul(argv[1], NULL); + header = *(u32 *)addr; + + if ((header & 0xff0000ff) != 0x89000000) { + printf("Wrong Signed message block format, header 0x%x\n", header); + return CMD_RET_FAILURE; + } + + header = (header & 0xffff00) >> 8; + + printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header); + flush_dcache_range(addr, addr + header - 1); + + if (ele_return_lifecycle_update(addr, &response)) { + printf("Return lifecycle failed, response 0x%x\n", response); + return CMD_RET_FAILURE; + } + + printf("Return lifecycle completed, response 0x%x\n", response); + + return CMD_RET_SUCCESS; +} + U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, "autenticate OS container via AHAB", "addr\n" @@ -583,3 +645,15 @@ U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status, "display AHAB lifecycle only", "" ); + +U_BOOT_CMD(ahab_sec_fuse_prog, CONFIG_SYS_MAXARGS, 1, do_sec_fuse_prog, + "Program secure fuse via signed message block", + "addr\n" + "addr - Signed message block for secure fuse\n" +); + +U_BOOT_CMD(ahab_return_lifecycle, CONFIG_SYS_MAXARGS, 1, do_ahab_return_lifecycle, + "Return lifecycle to OEM field return via signed message block", + "addr\n" + "addr - Return lifecycle message block signed by OEM SRK\n" +); diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 56605714f44..0ca0a94f08c 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2020 NXP + * Copyright 2020, 2023 NXP * */

@@ -490,3 +490,65 @@ int ele_get_events(u32 *events, u32 *events_cnt, u32 *response)

return ret; } + +int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 3; + msg.command = ELE_WRITE_SECURE_FUSE_REQ; + + msg.data[0] = upper_32_bits(signed_msg_blk); + msg.data[1] = lower_32_bits(signed_msg_blk); + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x, failed fuse row index %u\n", + __func__, ret, msg.data[0], msg.data[1]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 3; + msg.command = ELE_RET_LIFECYCLE_UP_REQ; + + msg.data[0] = upper_32_bits(signed_msg_blk); + msg.data[1] = lower_32_bits(signed_msg_blk); + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x, failed fuse row index %u\n", + __func__, ret, msg.data[0], msg.data[1]); + + if (response) + *response = msg.data[0]; + + return ret; +}

From: Ye Li ye.li@nxp.com

Fix Coverity (CID 21143558). When tee_shm_register returns failure, the shm_input pointer is invalid, should not free it. Same issue also exists on registering shm_output.

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/cmd_dek.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index d77a49df860..0be9df521a5 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -101,6 +101,7 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) 0x0, &shm_output); if (ret < 0) { printf("Cannot register output shared memory 0x%X\n", ret); + tee_shm_free(shm_input); goto error; }

@@ -122,11 +123,11 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) if (ret < 0) printf("Cannot generate Blob with PTA DEK Blob 0x%X\n", ret);

-error: /* Free shared memory */ tee_shm_free(shm_input); tee_shm_free(shm_output);

+error: /* Close session */ ret = tee_close_session(dev, arg.session); if (ret < 0)

From: Ye Li ye.li@nxp.com

According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All of them are used for ELE message. So update TR count to 8 and fix a typo in receive msg

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/misc/imx_ele/ele_mu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index 0d34b8c9010..956f8a1eb2f 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -22,7 +22,7 @@ struct imx8ulp_mu {

#define MU_SR_TE0_MASK BIT(0) #define MU_SR_RF0_MASK BIT(0) -#define MU_TR_COUNT 4 +#define MU_TR_COUNT 8 #define MU_RR_COUNT 4

void mu_hal_init(ulong base) @@ -65,7 +65,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) u32 val; int ret;

- assert(reg_index < MU_TR_COUNT); + assert(reg_index < MU_RR_COUNT);

debug("receivemsg sr 0x%x\n", readl(&mu_base->sr));

From: Peng Fan peng.fan@nxp.com

On the imx8ulp A1 SoC, the ELE RNG needs to be manually started.

Signed-off-by: Clement Faure clement.faure@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/mach-imx/ele_api.h | 1 + board/freescale/imx8ulp_evk/spl.c | 10 ++++++++++ drivers/misc/imx_ele/ele_api.c | 25 +++++++++++++++++++++++++ 3 files changed, 36 insertions(+)

diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 053a23f030b..cfd4ecebb62 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -149,4 +149,5 @@ int ele_get_fw_status(u32 *status, u32 *response); int ele_release_m33_trout(void); int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response); int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response); +int ele_start_rng(void); #endif diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index b7c6ff092b1..66d0f68cc62 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -123,6 +123,16 @@ void spl_board_init(void) ret = ele_release_caam(0x7, &res); if (ret) printf("ele release caam failed %d, 0x%x\n", ret, res); + + /* + * RNG start only available on the A1 soc revision. + * Check some JTAG register for the SoC revision. + */ + if (!is_soc_rev(CHIP_REV_1_0)) { + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + } }

void board_init_f(ulong dummy) diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 8a14cf6aa92..0c017734a49 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -503,6 +503,31 @@ int ele_get_events(u32 *events, u32 *events_cnt, u32 *response) return ret; }

+int ele_start_rng(void) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 1; + msg.command = ELE_START_RNG; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + return ret; +} + int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response) { struct udevice *dev = gd->arch.ele_dev;

From: Ye Li ye.li@nxp.com

Checking container header tag and version is wrong, it causes to fail to bypass invalid container

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/image-container.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 5b059a64292..745de130630 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -31,7 +31,7 @@ int get_container_size(ulong addr, u16 *header_length) u32 max_offset = 0, img_end;

phdr = (struct container_hdr *)addr; - if (phdr->tag != 0x87 && phdr->version != 0x0) { + if (phdr->tag != 0x87 || phdr->version != 0x0) { debug("Wrong container header\n"); return -EFAULT; }

From: Peng Fan peng.fan@nxp.com

i.MX8MN/P has Cortex-M7, i.MX93 has Cortex-M33, so use "M4" is a bit misleading, so update the name of the macro

Signed-off-by: faqiang.zhu faqiang.zhu@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 +- arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +- arch/arm/include/asm/arch-mx7/imx-regs.h | 2 +- arch/arm/mach-imx/imx9/imx_bootaux.c | 6 +++--- arch/arm/mach-imx/imx_bootaux.c | 24 +++++++++++----------- board/kontron/sl-mx8mm/sl-mx8mm.c | 2 +- board/kontron/sl-mx8mm/spl.c | 2 +- board/technexion/pico-imx8mq/pico-imx8mq.c | 2 +- board/technexion/pico-imx8mq/spl.c | 2 +- include/imx_sip.h | 6 +++--- 10 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 6e2fc82a0e4..8632eddb530 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -13,7 +13,7 @@ #define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800 #define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800

-#define M4_BOOTROM_BASE_ADDR 0x007E0000 +#define MCU_BOOTROM_BASE_ADDR 0x007E0000

#define GPIO1_BASE_ADDR 0X30200000 #define GPIO2_BASE_ADDR 0x30210000 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 72944af18a4..8fd3dd2df3a 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -23,7 +23,7 @@ #define GPU_ARB_END_ADDR 0x01803FFF #define APBH_DMA_ARB_BASE_ADDR 0x01804000 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF -#define M4_BOOTROM_BASE_ADDR 0x007F8000 +#define MCU_BOOTROM_BASE_ADDR 0x007F8000

#elif !defined(CONFIG_MX6SLL) #define CAAM_ARB_BASE_ADDR 0x00100000 diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index c863cd9da36..6f5ae5173c0 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -18,7 +18,7 @@ #define GIC400_ARB_END_ADDR 0x31007FFF #define APBH_DMA_ARB_BASE_ADDR 0x33000000 #define APBH_DMA_ARB_END_ADDR 0x33007FFF -#define M4_BOOTROM_BASE_ADDR 0x00180000 +#define MCU_BOOTROM_BASE_ADDR 0x00180000

#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c index 256e6fa1c54..6afb59e0515 100644 --- a/arch/arm/mach-imx/imx9/imx_bootaux.c +++ b/arch/arm/mach-imx/imx9/imx_bootaux.c @@ -13,7 +13,7 @@ int arch_auxiliary_core_check_up(u32 core_id) { struct arm_smccc_res res;

- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, 0, 0, 0, 0, &res);

return res.a0; @@ -25,7 +25,7 @@ int arch_auxiliary_core_down(u32 core_id)

printf("## Stopping auxiliary core\n");

- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STOP, 0, 0, + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, 0, 0, 0, 0, 0, &res);

return 0; @@ -40,7 +40,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)

printf("## Starting auxiliary core addr = 0x%08lX...\n", addr);

- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, addr, 0, + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, addr, 0, 0, 0, 0, 0, &res);

return 0; diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 888c53d6901..2b97aae3a23 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -124,15 +124,15 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n", stack, pc);

- /* Set the stack and pc to M4 bootROM */ - writel(stack, M4_BOOTROM_BASE_ADDR); - writel(pc, M4_BOOTROM_BASE_ADDR + 4); + /* Set the stack and pc to MCU bootROM */ + writel(stack, MCU_BOOTROM_BASE_ADDR); + writel(pc, MCU_BOOTROM_BASE_ADDR + 4);

flush_dcache_all();

- /* Enable M4 */ + /* Enable MCU */ if (IS_ENABLED(CONFIG_IMX8M)) { - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL); + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0, 0, 0, 0, 0, NULL); } else { clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK); @@ -147,7 +147,7 @@ int arch_auxiliary_core_check_up(u32 core_id) unsigned int val;

if (IS_ENABLED(CONFIG_IMX8M)) { - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res); + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, 0, 0, 0, 0, &res); return res.a0; }

@@ -164,13 +164,13 @@ int arch_auxiliary_core_check_up(u32 core_id) * the reset vector at the head for the image, with SP and PC * as the first two words. * - * Per the cortex-M reference manual, the reset vector of M4 needs - * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses - * of that vector. So to boot M4, the A core must build the M4's reset + * Per the cortex-M reference manual, the reset vector of M4/M7 needs + * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses + * of that vector. So to boot M4/M7, the A core must build the M4/M7's reset * vector with getting the PC and SP from image and filling them to - * TCMUL. When M4 is kicked, it will load the PC and SP by itself. - * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for - * accessing the M4 TCMUL. + * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself. + * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for + * accessing the M4/M7 TCMUL/IDTCM. */ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c index 250195694ba..f0c95d17b1a 100644 --- a/board/kontron/sl-mx8mm/sl-mx8mm.c +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -37,7 +37,7 @@ u8 num_image_type_guids = ARRAY_SIZE(fw_images);

int board_phys_sdram_size(phys_size_t *size) { - u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR); + u32 ddr_size = readl(MCU_BOOTROM_BASE_ADDR);

if (ddr_size == 4) { *size = 0x100000000; diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 3a919d0a9c3..b49373442a2 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -106,7 +106,7 @@ static void spl_dram_init(void) }

gd->ram_size = size; - writel(size, M4_BOOTROM_BASE_ADDR); + writel(size, MCU_BOOTROM_BASE_ADDR); }

int do_board_detect(void) diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c b/board/technexion/pico-imx8mq/pico-imx8mq.c index 951e3e1985b..2be3206f78a 100644 --- a/board/technexion/pico-imx8mq/pico-imx8mq.c +++ b/board/technexion/pico-imx8mq/pico-imx8mq.c @@ -54,7 +54,7 @@ int board_early_init_f(void)

int board_phys_sdram_size(phys_size_t *size) { - int ddr_size = readl(M4_BOOTROM_BASE_ADDR); + int ddr_size = readl(MCU_BOOTROM_BASE_ADDR);

if (ddr_size == 0x4) { *size = 0x100000000; diff --git a/board/technexion/pico-imx8mq/spl.c b/board/technexion/pico-imx8mq/spl.c index 8b853a914e8..2afb4d37608 100644 --- a/board/technexion/pico-imx8mq/spl.c +++ b/board/technexion/pico-imx8mq/spl.c @@ -89,7 +89,7 @@ static void spl_dram_init(void)

printf("%s: LPDDR4 %d GiB\n", __func__, size); ddr_init(dram_timing); - writel(size, M4_BOOTROM_BASE_ADDR); + writel(size, MCU_BOOTROM_BASE_ADDR); }

#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) diff --git a/include/imx_sip.h b/include/imx_sip.h index 1b873f231be..54317f20427 100644 --- a/include/imx_sip.h +++ b/include/imx_sip.h @@ -13,8 +13,8 @@ #define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00

#define IMX_SIP_SRC 0xC2000005 -#define IMX_SIP_SRC_M4_START 0x00 -#define IMX_SIP_SRC_M4_STARTED 0x01 -#define IMX_SIP_SRC_M4_STOP 0x02 +#define IMX_SIP_SRC_MCU_START 0x00 +#define IMX_SIP_SRC_MCU_STARTED 0x01 +#define IMX_SIP_SRC_MCU_STOP 0x02

#endif

From: Ye Li ye.li@nxp.com

The bootaux uses ulong to read private data and write to M4 TCM, this cause problem on ARM64 platform where the ulong is 8bytes. Fix it by using u32 to replace ulong.

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx_bootaux.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 2b97aae3a23..ab7a41fd11d 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -45,7 +45,7 @@ static const struct rproc_att *get_host_mapping(unsigned long auxcore) * is valid, returns the entry point address. * Translates load addresses in the elf file to the U-Boot address space. */ -static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack) +static u32 load_elf_image_m_core_phdr(unsigned long addr, u32 *stack) { Elf32_Ehdr *ehdr; /* ELF header structure pointer */ Elf32_Phdr *phdr; /* Program header structure pointer */ @@ -95,7 +95,7 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack

int arch_auxiliary_core_up(u32 core_id, ulong addr) { - ulong stack, pc; + u32 stack, pc;

if (!addr) return -EINVAL; @@ -121,7 +121,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) pc = *(u32 *)(addr + 4); }

- printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n", + printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n", stack, pc);

/* Set the stack and pc to MCU bootROM */

From: Peng Fan peng.fan@nxp.com

i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it.

Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 - 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 31c34b6031f..986870799d3 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -90,7 +90,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq) case ANATOP_DRAM_PLL: setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); - writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);

pll_base = &ana_pll->dram_pll_gnrl_ctl; break;

From: Ye Li ye.li@nxp.com

Abstract common interfaces for AHAB authentication operations. Then share some common codes for AHAB and SPL container authentication

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/mach-imx/ahab.h | 15 ++++ arch/arm/mach-imx/imx8/ahab.c | 129 +++++++++++++++++---------- arch/arm/mach-imx/imx8ulp/Makefile | 1 - arch/arm/mach-imx/parse-container.c | 81 ++--------------- 4 files changed, 103 insertions(+), 123 deletions(-) create mode 100644 arch/arm/include/asm/mach-imx/ahab.h

diff --git a/arch/arm/include/asm/mach-imx/ahab.h b/arch/arm/include/asm/mach-imx/ahab.h new file mode 100644 index 00000000000..4222e3db278 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/ahab.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __IMX_AHAB_H__ +#define __IMX_AHAB_H__ + +#include <asm/mach-imx/image.h> + +int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length); +int ahab_auth_release(void); +int ahab_verify_cntr_image(struct boot_img_t *img, int image_index); + +#endif diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 86b0e0b755f..c878743feeb 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -16,6 +16,7 @@ #include <asm/mach-imx/image.h> #include <console.h> #include <cpu_func.h> +#include <asm/mach-imx/ahab.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -25,6 +26,84 @@ DECLARE_GLOBAL_DATA_PTR;

#define SECO_PT 2U

+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) +{ + int err; + + memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container, + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); + + err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER, + SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); + if (err) + printf("Authenticate container hdr failed, return %d\n", err); + + return err; +} + +int ahab_auth_release(void) +{ + int err; + + err = sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0); + if (err) + printf("Error: release container failed!\n"); + + return err; +} + +int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) +{ + sc_faddr_t start, end; + sc_rm_mr_t mr; + int err; + int ret = 0; + + debug("img %d, dst 0x%llx, src 0x%x, size 0x%x\n", + image_index, img->dst, img->offset, img->size); + + /* Find the memreg and set permission for seco pt */ + err = sc_rm_find_memreg(-1, &mr, + img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1); + + if (err) { + printf("Error: can't find memreg for image load address 0x%llx, error %d\n", + img->dst, err); + return -ENOMEM; + } + + err = sc_rm_get_memreg_info(-1, mr, &start, &end); + if (!err) + debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end); + + err = sc_rm_set_memreg_permissions(-1, mr, + SECO_PT, SC_RM_PERM_FULL); + if (err) { + printf("Set permission failed for img %d, error %d\n", + image_index, err); + return -EPERM; + } + + err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE, + 1 << image_index); + if (err) { + printf("Authenticate img %d failed, return %d\n", + image_index, err); + ret = -EIO; + } + + err = sc_rm_set_memreg_permissions(-1, mr, + SECO_PT, SC_RM_PERM_NONE); + if (err) { + printf("Remove permission failed for img %d, error %d\n", + image_index, err); + ret = -EPERM; + } + + return ret; +} + static inline bool check_in_dram(ulong addr) { int i; @@ -46,8 +125,6 @@ int authenticate_os_container(ulong addr) struct container_hdr *phdr; int i, ret = 0; int err; - sc_rm_mr_t mr; - sc_faddr_t start, end; u16 length; struct boot_img_t *img; unsigned long s, e; @@ -76,14 +153,9 @@ int authenticate_os_container(ulong addr) length = phdr->length_lsb + (phdr->length_msb << 8);

debug("container length %u\n", length); - memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)addr, - ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));

- err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER, - SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); + err = ahab_auth_cntr_hdr(phdr, length); if (err) { - printf("Authenticate container hdr failed, return %d\n", - err); ret = -EIO; goto exit; } @@ -105,50 +177,13 @@ int authenticate_os_container(ulong addr)

flush_dcache_range(s, e);

- /* Find the memreg and set permission for seco pt */ - err = sc_rm_find_memreg(-1, &mr, s, e); - if (err) { - printf("Error: can't find memreg for image load address 0x%llx, error %d\n", img->dst, err); - ret = -ENOMEM; - goto exit; - } - - err = sc_rm_get_memreg_info(-1, mr, &start, &end); - if (!err) - debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end); - - err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT, - SC_RM_PERM_FULL); - if (err) { - printf("Set permission failed for img %d, error %d\n", - i, err); - ret = -EPERM; - goto exit; - } - - err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE, - (1 << i)); - if (err) { - printf("Authenticate img %d failed, return %d\n", - i, err); - ret = -EIO; - } - - err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT, - SC_RM_PERM_NONE); - if (err) { - printf("Remove permission failed for img %d, err %d\n", - i, err); - ret = -EPERM; - } - + ret = ahab_verify_cntr_image(img, i); if (ret) goto exit; }

exit: - if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0)) - printf("Error: release container failed!\n"); + ahab_auth_release();

return ret; } diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index f7692cf3a78..2c9938fcdf0 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -5,7 +5,6 @@

obj-y += lowlevel_init.o obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o -obj-$(CONFIG_AHAB_BOOT) += ahab.o

ifeq ($(CONFIG_SPL_BUILD),y) obj-y += upower/ diff --git a/arch/arm/mach-imx/parse-container.c b/arch/arm/mach-imx/parse-container.c index c5b3abc4f29..e2a9e2b2732 100644 --- a/arch/arm/mach-imx/parse-container.c +++ b/arch/arm/mach-imx/parse-container.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2021 NXP */

#include <common.h> @@ -10,67 +10,7 @@ #include <spl.h> #include <asm/mach-imx/image.h> #ifdef CONFIG_AHAB_BOOT -#include <firmware/imx/sci/sci.h> -#endif - -#define SEC_SECURE_RAM_BASE 0x31800000UL -#define SEC_SECURE_RAM_END_BASE (SEC_SECURE_RAM_BASE + 0xFFFFUL) -#define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE 0x60000000UL - -#define SECO_PT 2U - -#ifdef CONFIG_AHAB_BOOT -static int authenticate_image(struct boot_img_t *img, int image_index) -{ - sc_faddr_t start, end; - sc_rm_mr_t mr; - int err; - int ret = 0; - - debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n", - image_index, (uint32_t)img->dst, img->offset, img->size); - - /* Find the memreg and set permission for seco pt */ - err = sc_rm_find_memreg(-1, &mr, - img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), - ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1); - - if (err) { - printf("can't find memreg for image %d load address 0x%llx, error %d\n", - image_index, img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), err); - return -ENOMEM; - } - - err = sc_rm_get_memreg_info(-1, mr, &start, &end); - if (!err) - debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end); - - err = sc_rm_set_memreg_permissions(-1, mr, - SECO_PT, SC_RM_PERM_FULL); - if (err) { - printf("set permission failed for img %d, error %d\n", - image_index, err); - return -EPERM; - } - - err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE, - 1 << image_index); - if (err) { - printf("authenticate img %d failed, return %d\n", - image_index, err); - ret = -EIO; - } - - err = sc_rm_set_memreg_permissions(-1, mr, - SECO_PT, SC_RM_PERM_NONE); - if (err) { - printf("remove permission failed for img %d, error %d\n", - image_index, err); - ret = -EPERM; - } - - return ret; -} +#include <asm/mach-imx/ahab.h> #endif

static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, @@ -111,10 +51,8 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, }

#ifdef CONFIG_AHAB_BOOT - if (authenticate_image(&images[image_index], image_index)) { - printf("Failed to authenticate image %d\n", image_index); + if (ahab_verify_cntr_image(&images[image_index], image_index)) return NULL; - } #endif

return &images[image_index]; @@ -180,15 +118,9 @@ static int read_auth_container(struct spl_image_info *spl_image, }

#ifdef CONFIG_AHAB_BOOT - memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container, - ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); - - ret = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER, - SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); - if (ret) { - printf("authenticate container hdr failed, return %d\n", ret); + ret = ahab_auth_cntr_hdr(container, length); + if (ret) goto end_auth; - } #endif

for (i = 0; i < container->num_images; i++) { @@ -209,8 +141,7 @@ static int read_auth_container(struct spl_image_info *spl_image,

end_auth: #ifdef CONFIG_AHAB_BOOT - if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0)) - printf("Error: release container failed!\n"); + ahab_auth_release(); #endif

end:

From: Peng Fan peng.fan@nxp.com

Add CAAM_BASE_ADDR which will be used by priblob.c

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 8632eddb530..f1b7526ac77 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -40,6 +40,7 @@ #define UART1_BASE_ADDR 0x30860000 #define UART3_BASE_ADDR 0x30880000 #define UART2_BASE_ADDR 0x30890000 +#define CAAM_BASE_ADDR 0x30900000 #define I2C1_BASE_ADDR 0x30A20000 #define I2C2_BASE_ADDR 0x30A30000 #define I2C3_BASE_ADDR 0x30A40000

From: Utkarsh Gupta utkarsh.gupta@nxp.com

The sec_in32 preprocessor is defined as follows in include/fsl_sec.h file: When address "a" is calculated using math for ex: addition of base address and an offset, then casting is applied only to the first address which in this example is base address.

caam_ccbvid_reg = sec_in32(CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET) resolves to: caam_ccbvid_reg = in_le32((ulong *)(ulong)CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET) instead it should resolve to: caam_ccbvid_reg = in_le32((ulong *)(ulong)(CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET))

Thus add parenthesis around the address "a" so that however the address is calculated, the casting is applied to the final calculated address.

Reviewed-by: Horia Geanta horia.geanta@nxp.com Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Utkarsh Gupta utkarsh.gupta@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- include/fsl_sec.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/fsl_sec.h b/include/fsl_sec.h index d8861d1d0b7..9dad1d1ec47 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -13,8 +13,8 @@ #include <asm/io.h>

#ifdef CONFIG_SYS_FSL_SEC_LE -#define sec_in32(a) in_le32((ulong *)(ulong)a) -#define sec_out32(a, v) out_le32((ulong *)(ulong)a, v) +#define sec_in32(a) in_le32((ulong *)(ulong)(a)) +#define sec_out32(a, v) out_le32((ulong *)(ulong)(a), v) #define sec_in16(a) in_le16(a) #define sec_clrbits32 clrbits_le32 #define sec_setbits32 setbits_le32