[U-Boot] [PATCH] ARM: pantheon: enable dcache by default
Marvell 88SV331xV5 has its specific arm cp15 opcode, which could flush out whole dcache by only one line of asm code.
Signed-off-by: Lei Wen leiwen@marvell.com --- arch/arm/cpu/arm926ejs/pantheon/cpu.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c index 2d9c13a..8f94ea9 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c +++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c @@ -105,3 +105,17 @@ void i2c_clk_enable(void) { } #endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + +void flush_cache(unsigned long start, unsigned long size) +{ + /* clean & invalidate all D cache */ + asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0)); +} +#endif
-----Original Message----- From: Lei Wen [mailto:leiwen@marvell.com] Sent: Wednesday, October 05, 2011 8:43 PM To: Prafulla Wadaskar; u-boot@lists.denx.de Subject: [PATCH] ARM: pantheon: enable dcache by default
Marvell 88SV331xV5 has its specific arm cp15 opcode, which could
I think this will be applicable to all SoC those fall under this core. So we should modify arch/arm/include/asm/cache.h for this.
flush out whole dcache by only one line of asm code.
Signed-off-by: Lei Wen leiwen@marvell.com
arch/arm/cpu/arm926ejs/pantheon/cpu.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c index 2d9c13a..8f94ea9 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c +++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c @@ -105,3 +105,17 @@ void i2c_clk_enable(void) { } #endif
+#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
+}
+void flush_cache(unsigned long start, unsigned long size) +{
- /* clean & invalidate all D cache */
- asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));
+} +#endif
Otherwise ack for this change
Regards.. Prafulla ..
-- 1.7.0.4
Hi Prafulla,
On Fri, Oct 7, 2011 at 11:53 AM, Prafulla Wadaskar prafulla@marvell.com wrote:
-----Original Message----- From: Lei Wen [mailto:leiwen@marvell.com] Sent: Wednesday, October 05, 2011 8:43 PM To: Prafulla Wadaskar; u-boot@lists.denx.de Subject: [PATCH] ARM: pantheon: enable dcache by default
Marvell 88SV331xV5 has its specific arm cp15 opcode, which could
I think this will be applicable to all SoC those fall under this core. So we should modify arch/arm/include/asm/cache.h for this.
I modify my original one patch into three small patch series. And put the op code place as you suggested, please help re-check it.
flush out whole dcache by only one line of asm code.
Signed-off-by: Lei Wen leiwen@marvell.com
arch/arm/cpu/arm926ejs/pantheon/cpu.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c index 2d9c13a..8f94ea9 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c +++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c @@ -105,3 +105,17 @@ void i2c_clk_enable(void) { } #endif
+#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
+}
+void flush_cache(unsigned long start, unsigned long size) +{
- /* clean & invalidate all D cache */
- asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));
+} +#endif
Otherwise ack for this change
Thanks, Lei
This patch seris use Marvell its own special op code to flush the dcache
Lei Wen (3): ARM: add special dcache flush op code for 88SV331xV5 ARM: pantheon: enable dcache by default ARM: armada100: enable dcache by default
arch/arm/cpu/arm926ejs/armada100/cpu.c | 8 ++++++++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 8 ++++++++ arch/arm/lib/cache.c | 5 +++++ 3 files changed, 21 insertions(+), 0 deletions(-)
Hi Prafulla,
On Sat, Oct 8, 2011 at 9:59 PM, Lei Wen leiwen@marvell.com wrote:
This patch seris use Marvell its own special op code to flush the dcache
Lei Wen (3): ARM: add special dcache flush op code for 88SV331xV5 ARM: pantheon: enable dcache by default ARM: armada100: enable dcache by default
arch/arm/cpu/arm926ejs/armada100/cpu.c | 8 ++++++++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 8 ++++++++ arch/arm/lib/cache.c | 5 +++++ 3 files changed, 21 insertions(+), 0 deletions(-)
Do you have any comment over this patch series?
Thanks, Lei
Le 18/10/2011 17:02, Lei Wen a écrit :
Hi Prafulla,
On Sat, Oct 8, 2011 at 9:59 PM, Lei Wenleiwen@marvell.com wrote:
This patch seris use Marvell its own special op code to flush the dcache
Lei Wen (3): ARM: add special dcache flush op code for 88SV331xV5 ARM: pantheon: enable dcache by default ARM: armada100: enable dcache by default
arch/arm/cpu/arm926ejs/armada100/cpu.c | 8 ++++++++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 8 ++++++++ arch/arm/lib/cache.c | 5 +++++ 3 files changed, 21 insertions(+), 0 deletions(-)
Do you have any comment over this patch series?
Prafulla, will you take this series in?
Amicalement,
-----Original Message----- From: Albert ARIBAUD [mailto:albert.u.boot@aribaud.net] Sent: Wednesday, November 09, 2011 1:37 AM To: Prafulla Wadaskar Cc: u-boot@lists.denx.de; Lei Wen Subject: Re: [U-Boot] [PATCH 0/3] enable dcache for pantheon and armada100
Le 18/10/2011 17:02, Lei Wen a écrit :
Hi Prafulla,
On Sat, Oct 8, 2011 at 9:59 PM, Lei Wenleiwen@marvell.com
wrote:
This patch seris use Marvell its own special op code to
flush the dcache
Lei Wen (3): ARM: add special dcache flush op code for 88SV331xV5 ARM: pantheon: enable dcache by default ARM: armada100: enable dcache by default
arch/arm/cpu/arm926ejs/armada100/cpu.c | 8 ++++++++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 8 ++++++++ arch/arm/lib/cache.c | 5 +++++ 3 files changed, 21 insertions(+), 0 deletions(-)
Do you have any comment over this patch series?
Prafulla, will you take this series in?
Yes, I will do it Regards.. Prafulla . . .
Amicalement,
Albert.
Marvell 88SV331xV5 has its specific arm cp15 opcode, which could flush out whole dcache by only one line of asm code.
Signed-off-by: Lei Wen leiwen@marvell.com --- arch/arm/lib/cache.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index b545fb7..bfcbda4 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -33,11 +33,16 @@ void __flush_cache(unsigned long start, unsigned long size) arm1136_cache_flush(); #endif #ifdef CONFIG_ARM926EJS +#ifdef CONFIG_SHEEVA_88SV331xV5 + /* clean & invalidate all D cache */ + asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0)); +#else /* test and clean, page 2-23 of arm926ejs manual */ asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); #endif +#endif return; } void flush_cache(unsigned long start, unsigned long size)
Signed-off-by: Lei Wen leiwen@marvell.com --- arch/arm/cpu/arm926ejs/pantheon/cpu.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c index 8b2eafa..18da1c1 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c +++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c @@ -88,3 +88,11 @@ void i2c_clk_enable(void) { } #endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in arch_cpu_init */ + dcache_enable(); +} +#endif
Signed-off-by: Lei Wen leiwen@marvell.com --- arch/arm/cpu/arm926ejs/armada100/cpu.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c index c21938e..47b764d 100644 --- a/arch/arm/cpu/arm926ejs/armada100/cpu.c +++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c @@ -106,3 +106,11 @@ void i2c_clk_enable(void) { } #endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in arch_cpu_init */ + dcache_enable(); +} +#endif
participants (4)
-
Albert ARIBAUD -
Lei Wen -
Lei Wen -
Prafulla Wadaskar