[U-Boot] [PATCH] 85xx: Update MPC85xx_PORDEVSR_IO_SEL mask

The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx processors have a 3-bit wide IO_SEL field but have the most significant bit is wired to 0 so this change should not affect them.
Signed-off-by: Peter Tyser ptyser@xes-inc.com --- include/asm-ppc/immap_85xx.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index ad30099..4892d8b 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1568,7 +1568,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 -#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 +#define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000

On Mon, Oct 27, 2008 at 4:42 PM, Peter Tyser ptyser@xes-inc.com wrote:
The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx processors have a 3-bit wide IO_SEL field but have the most significant bit is wired to 0 so this change should not affect them.
Signed-off-by: Peter Tyser ptyser@xes-inc.com
Applied, thanks
Andy
participants (2)
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Andy Fleming
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Peter Tyser