[U-Boot] Question about PCIe configuration
Hi,
I am trying to map a PCIe peripherical on my MPC8536 custom board. I already have u-boot and linux kernel running fine on this board.
The peripherical is on PCIe1 port. Compiling u-boot using debug flag I have the following log:
pci_init_board: devdisr=40900, sdrs2_io_sel=7, io_sel=7 Serdes2 disalbed
PCIE3: disabled
PCIE1: disabled
PCIE2: disabled
PCI: 32 bit, 66 MHz, sync, host, arbiter (base address ffe08000) with errors. Clearing. Now 0x0b200091Outbound memory range: f0000000:100000000 PCICSRBAR @ 0xeff00000 R0 bus_start: 0 phys_start: 0 size: 8000000 R64 bus_start: 1000000000 phys_start: 0 size: 8000000 PCI reg:0 0000000c00000000:00000000f0000000 0000000010000000 00000000 PCI reg:1 0000000fffc00000:0000000000000000 0000000000010000 00000001 PCI reg:2 0000000fffe00000:00000000eff00000 0000000000100000 00000100 PCI reg:3 0000000000000000:0000000000000000 0000000008000000 00000108 PCI reg:4 0000000000000000:0000001000000000 0000000008000000 00000108 Scanning PCI bus 00 PCIE1 on bus 00 - 00
Running pci command I can see:
=> pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1957 0x0050 Processor 0x20
I don't know if I am correct, but I understand that the PCIe controller identify itself. However, the PCIe peripherical was not found.
Bellow, the default PCIe1 configuration to MPC8536DS target. Could something in this configuration prevent the PCIe peripherical to be found?
I have CONFIG_PHYS_64BIT enabled.
/* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull #else #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 #endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Thank you.
Carlos R. Moratelli
From: Carlos Roberto Moratelli
I am trying to map a PCIe peripherical on my MPC8536 custom board. The peripherical is on PCIe1 port.
Is this still an issue?
pci_init_board: devdisr=40900, sdrs2_io_sel=7, io_sel=7 Serdes2 disalbed
That is fine.
PCIE3: disabled PCIE1: disabled
This is the problem. Check:
pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE))
in your board file.
PCIE2: disabled PCI: 32 bit, 66 MHz, sync, host, arbiter (base address ffe08000)
...
Scanning PCI bus 00 PCIE1 on bus 00 - 00
This is a code bug, it really should say is PCI1 and not PCIE1.
Running pci command I can see:
=> pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1957 0x0050 Processor 0x20
I don't know if I am correct, but I understand that the PCIe controller identify itself. However, the PCIe peripherical was not
found.
You need to figure out why "PCIE1: disabled" is occurring
-Ed Swarthout
Em Qui, 2010-10-07 às 00:39 -0500, Swarthout Edward L-SWARTHOU escreveu:
From: Carlos Roberto Moratelli
I am trying to map a PCIe peripherical on my MPC8536 custom board. The peripherical is on PCIe1 port.
Is this still an issue?
pci_init_board: devdisr=40900, sdrs2_io_sel=7, io_sel=7 Serdes2 disalbed
That is fine.
PCIE3: disabled PCIE1: disabledThis is the problem. Check:
pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE))
in your board file.
Rigth! I just enabled CONFIG_PCIE1 flag and the PCIE1 bus is detected. Now I have this new log:
PCIE1 connected to Slot1 as Root Complex (base address ffe0a000) Outbound memory range: f8000000:100000000 PCICSRBAR @ 0xf7f00000 R0 bus_start: 0 phys_start: 0 size: 8000000 PCI reg:0 0000000c10000000:f800000008000000 0000000000000001 0210def0 PCI reg:1 0000000fffc10000:0000000000010000 0000000100000001 0210def0 PCI reg:2 0000000fffe00000:f7f0000000100000 0000010000000001 0210def0 PCI reg:3 0000000000000000:0000000008000000 0000010800000001 0210def0 ....PCIE link error. Skipping scan.LTSSM=0x08 PCIE1 on bus 01 - 01
I was expecting to find a peripherical on PCIE1 bus. I have a switch chip connected to Serdes 1 lane A.
pci_init_board: devdisr=40900, sdrs2_io_sel=7, io_sel=7 Serdes2 disalbed
How you can see, serdes 1 is enabled and working with pcie1 (io_sel=7). It appears that something is not correctly configured, but I have no idea about what.
PCIE2: disabled PCI: 32 bit, 66 MHz, sync, host, arbiter (base address ffe08000)...
Scanning PCI bus 00 PCIE1 on bus 00 - 00This is a code bug, it really should say is PCI1 and not PCIE1.
Yes! That was a bit confused.
Running pci command I can see:
=> pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1957 0x0050 Processor 0x20
I don't know if I am correct, but I understand that the PCIe controller identify itself. However, the PCIe peripherical was not
found.
You need to figure out why "PCIE1: disabled" is occurring
-Ed Swarthout
I will apreciate some tip to deal with that issue.
Thanks,
Carlos Roberto Moratelli.
From: Carlos Roberto Moratelli
Rigth! I just enabled CONFIG_PCIE1 flag and the PCIE1 bus is detected. Now I have this new log:
PCIE1 connected to Slot1 as Root Complex (base address ffe0a000)Outbound memory range: f8000000:100000000 PCICSRBAR @ 0xf7f00000 R0 bus_start: 0 phys_start: 0 size: 8000000 PCI reg:0 0000000c10000000:f800000008000000 0000000000000001 0210def0 PCI reg:1 0000000fffc10000:0000000000010000 0000000100000001 0210def0 PCI reg:2 0000000fffe00000:f7f0000000100000 0000010000000001 0210def0 PCI reg:3 0000000000000000:0000000008000000 0000010800000001 0210def0
....PCIE link error. Skipping scan.LTSSM=0x08
The LTSSM value of 8 indicates the problem. See:
"Table 18-111. PEX_LTSSM_STAT Status Codes" 8 - "Polling compliance"
This shows the 8536 is fine and detects the device's receivers on the bus, but the device has not responded with a correct training sequence.
There are many potential causes for the device not responding: 1. device powered on? 2. have correct clocks? 3. if an fpga, is it loaded? 4. is it out of reset?
What is the device? Can you query it with a jtag probe?
PCIE1 on bus 01 - 01I was expecting to find a peripherical on PCIE1 bus. I have a switch chip connected to Serdes 1 lane A.
I see. What switch? Is it on a card or directly on the board? Can you probe reset, power, and clocks?
pci_init_board: devdisr=40900, sdrs2_io_sel=7, io_sel=7 Serdes2 disalbed
How you can see, serdes 1 is enabled and working with pcie1 (io_sel=7). It appears that something is not correctly configured, but
I have no idea about what.
This is all correct.
PCIE2: disabled PCI: 32 bit, 66 MHz, sync, host, arbiter (base...
Scanning PCI bus 00 PCIE1 on bus 00 - 00This is a code bug, it really should say is PCI1 and not PCIE1.
Yes! That was a bit confused.
I will appreciate some tip to deal with that issue.
You can read the ltssm register from the prompt and on a working link you will see 16:
=> pci d 1.0 404 1 00000404: 00000016
-Ed
Em Qui, 2010-10-07 às 09:33 -0500, Swarthout Edward L-SWARTHOU escreveu:
The LTSSM value of 8 indicates the problem. See:
"Table 18-111. PEX_LTSSM_STAT Status Codes" 8 - "Polling compliance"
This shows the 8536 is fine and detects the device's receivers on the bus, but the device has not responded with a correct training sequence.
There are many potential causes for the device not responding:
- device powered on?
- have correct clocks?
- if an fpga, is it loaded?
- is it out of reset?
I am considering a hardware design issue too, the hardware team is working on that.
What is the device? Can you query it with a jtag probe?
PCIE1 on bus 01 - 01I was expecting to find a peripherical on PCIE1 bus. I have a
switch
chip connected to Serdes 1 lane A.
I see. What switch? Is it on a card or directly on the board? Can you probe reset, power, and clocks?
A broadcom switch. It is directly on the board.
I tried to probe SD1_PLL_TPD (PLL test point Digital, pin V28 on MPC8536 E), there is no signal there. What Should I observe in this pin? I was expecting to observe the internal serdes clock signal.
Thanks
Carlos R. Moratelli
participants (2)
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Carlos Roberto Moratelli -
Swarthout Edward L-SWARTHOU