[U-Boot] [RFC PATCH 0/6] Mips: Refactoring of CPU and SoC code
All current Mips CPUs and SoCs are based on Mips32 arch. The complete code resides in the global arch/mips/cpu directory. All SoC specific code resides in this directory too. This is not suitable if other Mips architectures like Mips64 or Octeon or new SoCs should be supported in the future.
This patch series refactors the Mips CPU directory and put all current code into an own mips32 subdirectory. Furthermore the SoC specific code of IncaIP, Purple and Au1x00 is moved to separate SoC subdirectories.
Daniel Schwierzeck (6): Mips: Move content of arch/mips/cpu to arch/mips/cpu/mips32 Mips: Purple: Adapt u-boot.lds to changed CPU directory layout Mips: IncaIP: Move all IncaIP specific code to separate subdirectory Mips: Purple: Move all Purple specific code to separate subdirectory Mips: Au1x00: Move all Au1x00 specific code to separate subdirectory Mips: Update setting of endianess and CPU optimization flags
arch/mips/cpu/config.mk | 39 --------------- arch/mips/cpu/{ => mips32}/Makefile | 5 -- arch/mips/cpu/mips32/au1x00/Makefile | 45 +++++++++++++++++ arch/mips/cpu/{ => mips32/au1x00}/au1x00_eth.c | 0 arch/mips/cpu/{ => mips32/au1x00}/au1x00_serial.c | 0 .../mips/cpu/{ => mips32/au1x00}/au1x00_usb_ohci.c | 0 .../mips/cpu/{ => mips32/au1x00}/au1x00_usb_ohci.h | 0 arch/mips/cpu/mips32/au1x00/config.mk | 24 +++++++++ arch/mips/cpu/{ => mips32}/cache.S | 0 arch/mips/cpu/mips32/config.mk | 32 ++++++++++++ arch/mips/cpu/{ => mips32}/cpu.c | 0 arch/mips/cpu/mips32/incaip/Makefile | 46 +++++++++++++++++ arch/mips/cpu/{ => mips32/incaip}/asc_serial.c | 0 arch/mips/cpu/{ => mips32/incaip}/asc_serial.h | 0 arch/mips/cpu/mips32/incaip/config.mk | 24 +++++++++ arch/mips/cpu/{ => mips32/incaip}/incaip_clock.c | 0 arch/mips/cpu/{ => mips32/incaip}/incaip_wdt.S | 0 arch/mips/cpu/{ => mips32}/interrupts.c | 0 arch/mips/cpu/mips32/purple/Makefile | 45 +++++++++++++++++ arch/mips/cpu/{ => mips32/purple}/asc_serial.c | 0 arch/mips/cpu/{ => mips32/purple}/asc_serial.h | 0 arch/mips/cpu/mips32/purple/config.mk | 24 +++++++++ arch/mips/cpu/{ => mips32}/start.S | 0 board/purple/u-boot.lds | 2 +- boards.cfg | 52 ++++++++++---------- 25 files changed, 267 insertions(+), 71 deletions(-) delete mode 100644 arch/mips/cpu/config.mk rename arch/mips/cpu/{ => mips32}/Makefile (87%) create mode 100644 arch/mips/cpu/mips32/au1x00/Makefile rename arch/mips/cpu/{ => mips32/au1x00}/au1x00_eth.c (100%) rename arch/mips/cpu/{ => mips32/au1x00}/au1x00_serial.c (100%) rename arch/mips/cpu/{ => mips32/au1x00}/au1x00_usb_ohci.c (100%) rename arch/mips/cpu/{ => mips32/au1x00}/au1x00_usb_ohci.h (100%) create mode 100644 arch/mips/cpu/mips32/au1x00/config.mk rename arch/mips/cpu/{ => mips32}/cache.S (100%) create mode 100644 arch/mips/cpu/mips32/config.mk rename arch/mips/cpu/{ => mips32}/cpu.c (100%) create mode 100644 arch/mips/cpu/mips32/incaip/Makefile copy arch/mips/cpu/{ => mips32/incaip}/asc_serial.c (100%) copy arch/mips/cpu/{ => mips32/incaip}/asc_serial.h (100%) create mode 100644 arch/mips/cpu/mips32/incaip/config.mk rename arch/mips/cpu/{ => mips32/incaip}/incaip_clock.c (100%) rename arch/mips/cpu/{ => mips32/incaip}/incaip_wdt.S (100%) rename arch/mips/cpu/{ => mips32}/interrupts.c (100%) create mode 100644 arch/mips/cpu/mips32/purple/Makefile rename arch/mips/cpu/{ => mips32/purple}/asc_serial.c (100%) rename arch/mips/cpu/{ => mips32/purple}/asc_serial.h (100%) create mode 100644 arch/mips/cpu/mips32/purple/config.mk rename arch/mips/cpu/{ => mips32}/start.S (100%)
-- 1.7.4.1
All current CPUs and SoCs are based on Mips32 arch. The complete code resides in the global arch/mips/cpu directory. This is not suitable if other Mips architectures like Mips64 or Octeon should be supported in the future.
To achieve this the current CPU code is moved to its own mips32 subdirectory. All Mips32 boards have to use mips32 as config switch in board.cfg.
Signed-off-by: Daniel Schwierzeck daniel.schwierzeck@googlemail.com Cc: Shinya Kuribayashi skuribay@pobox.com --- arch/mips/cpu/{ => mips32}/Makefile | 0 arch/mips/cpu/{ => mips32}/asc_serial.c | 0 arch/mips/cpu/{ => mips32}/asc_serial.h | 0 arch/mips/cpu/{ => mips32}/au1x00_eth.c | 0 arch/mips/cpu/{ => mips32}/au1x00_serial.c | 0 arch/mips/cpu/{ => mips32}/au1x00_usb_ohci.c | 0 arch/mips/cpu/{ => mips32}/au1x00_usb_ohci.h | 0 arch/mips/cpu/{ => mips32}/cache.S | 0 arch/mips/cpu/{ => mips32}/config.mk | 0 arch/mips/cpu/{ => mips32}/cpu.c | 0 arch/mips/cpu/{ => mips32}/incaip_clock.c | 0 arch/mips/cpu/{ => mips32}/incaip_wdt.S | 0 arch/mips/cpu/{ => mips32}/interrupts.c | 0 arch/mips/cpu/{ => mips32}/start.S | 0 boards.cfg | 52 +++++++++++++------------- 15 files changed, 26 insertions(+), 26 deletions(-) rename arch/mips/cpu/{ => mips32}/Makefile (100%) rename arch/mips/cpu/{ => mips32}/asc_serial.c (100%) rename arch/mips/cpu/{ => mips32}/asc_serial.h (100%) rename arch/mips/cpu/{ => mips32}/au1x00_eth.c (100%) rename arch/mips/cpu/{ => mips32}/au1x00_serial.c (100%) rename arch/mips/cpu/{ => mips32}/au1x00_usb_ohci.c (100%) rename arch/mips/cpu/{ => mips32}/au1x00_usb_ohci.h (100%) rename arch/mips/cpu/{ => mips32}/cache.S (100%) rename arch/mips/cpu/{ => mips32}/config.mk (100%) rename arch/mips/cpu/{ => mips32}/cpu.c (100%) rename arch/mips/cpu/{ => mips32}/incaip_clock.c (100%) rename arch/mips/cpu/{ => mips32}/incaip_wdt.S (100%) rename arch/mips/cpu/{ => mips32}/interrupts.c (100%) rename arch/mips/cpu/{ => mips32}/start.S (100%)
diff --git a/arch/mips/cpu/Makefile b/arch/mips/cpu/mips32/Makefile similarity index 100% rename from arch/mips/cpu/Makefile rename to arch/mips/cpu/mips32/Makefile diff --git a/arch/mips/cpu/asc_serial.c b/arch/mips/cpu/mips32/asc_serial.c similarity index 100% rename from arch/mips/cpu/asc_serial.c rename to arch/mips/cpu/mips32/asc_serial.c diff --git a/arch/mips/cpu/asc_serial.h b/arch/mips/cpu/mips32/asc_serial.h similarity index 100% rename from arch/mips/cpu/asc_serial.h rename to arch/mips/cpu/mips32/asc_serial.h diff --git a/arch/mips/cpu/au1x00_eth.c b/arch/mips/cpu/mips32/au1x00_eth.c similarity index 100% rename from arch/mips/cpu/au1x00_eth.c rename to arch/mips/cpu/mips32/au1x00_eth.c diff --git a/arch/mips/cpu/au1x00_serial.c b/arch/mips/cpu/mips32/au1x00_serial.c similarity index 100% rename from arch/mips/cpu/au1x00_serial.c rename to arch/mips/cpu/mips32/au1x00_serial.c diff --git a/arch/mips/cpu/au1x00_usb_ohci.c b/arch/mips/cpu/mips32/au1x00_usb_ohci.c similarity index 100% rename from arch/mips/cpu/au1x00_usb_ohci.c rename to arch/mips/cpu/mips32/au1x00_usb_ohci.c diff --git a/arch/mips/cpu/au1x00_usb_ohci.h b/arch/mips/cpu/mips32/au1x00_usb_ohci.h similarity index 100% rename from arch/mips/cpu/au1x00_usb_ohci.h rename to arch/mips/cpu/mips32/au1x00_usb_ohci.h diff --git a/arch/mips/cpu/cache.S b/arch/mips/cpu/mips32/cache.S similarity index 100% rename from arch/mips/cpu/cache.S rename to arch/mips/cpu/mips32/cache.S diff --git a/arch/mips/cpu/config.mk b/arch/mips/cpu/mips32/config.mk similarity index 100% rename from arch/mips/cpu/config.mk rename to arch/mips/cpu/mips32/config.mk diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/mips32/cpu.c similarity index 100% rename from arch/mips/cpu/cpu.c rename to arch/mips/cpu/mips32/cpu.c diff --git a/arch/mips/cpu/incaip_clock.c b/arch/mips/cpu/mips32/incaip_clock.c similarity index 100% rename from arch/mips/cpu/incaip_clock.c rename to arch/mips/cpu/mips32/incaip_clock.c diff --git a/arch/mips/cpu/incaip_wdt.S b/arch/mips/cpu/mips32/incaip_wdt.S similarity index 100% rename from arch/mips/cpu/incaip_wdt.S rename to arch/mips/cpu/mips32/incaip_wdt.S diff --git a/arch/mips/cpu/interrupts.c b/arch/mips/cpu/mips32/interrupts.c similarity index 100% rename from arch/mips/cpu/interrupts.c rename to arch/mips/cpu/mips32/interrupts.c diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/mips32/start.S similarity index 100% rename from arch/mips/cpu/start.S rename to arch/mips/cpu/mips32/start.S diff --git a/boards.cfg b/boards.cfg index 45c3102..8f63b6c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -217,32 +217,32 @@ M5282EVB m68k mcf52x2 m5282evb freesca M53017EVB m68k mcf52x2 m53017evb freescale EP2500 m68k mcf52x2 ep2500 Mercury microblaze-generic microblaze microblaze microblaze-generic xilinx -dbau1000 mips mips dbau1x00 - - dbau1x00:DBAU1000 -dbau1100 mips mips dbau1x00 - - dbau1x00:DBAU1100 -dbau1500 mips mips dbau1x00 - - dbau1x00:DBAU1500 -dbau1550 mips mips dbau1x00 - - dbau1x00:DBAU1550 -dbau1550_el mips mips dbau1x00 - - dbau1x00:DBAU1550 -gth2 mips mips -incaip mips mips -incaip_100MHz mips mips incaip - - incaip:CPU_CLOCK_RATE=100000000 -incaip_133MHz mips mips incaip - - incaip:CPU_CLOCK_RATE=133000000 -incaip_150MHz mips mips incaip - - incaip:CPU_CLOCK_RATE=150000000 -pb1000 mips mips pb1x00 - - pb1x00:PB1000 -purple mips mips -qemu_mips mips mips qemu-mips - - qemu-mips -tb0229 mips mips -vct_premium mips mips vct micronas - vct:VCT_PREMIUM -vct_premium_small mips mips vct micronas - vct:VCT_PREMIUM,VCT_SMALL_IMAGE -vct_premium_onenand mips mips vct micronas - vct:VCT_PREMIUM,VCT_ONENAND -vct_premium_onenand_small mips mips vct micronas - vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE -vct_platinum mips mips vct micronas - vct:VCT_PLATINUM -vct_platinum_small mips mips vct micronas - vct:VCT_PLATINUM,VCT_SMALL_IMAGE -vct_platinum_onenand mips mips vct micronas - vct:VCT_PLATINUM,VCT_ONENAND -vct_platinum_onenand_small mips mips vct micronas - vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE -vct_platinumavc mips mips vct micronas - vct:VCT_PLATINUMAVC -vct_platinumavc_small mips mips vct micronas - vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE -vct_platinumavc_onenand mips mips vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND -vct_platinumavc_onenand_small mips mips vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE +dbau1000 mips mips32 dbau1x00 - - dbau1x00:DBAU1000 +dbau1100 mips mips32 dbau1x00 - - dbau1x00:DBAU1100 +dbau1500 mips mips32 dbau1x00 - - dbau1x00:DBAU1500 +dbau1550 mips mips32 dbau1x00 - - dbau1x00:DBAU1550 +dbau1550_el mips mips32 dbau1x00 - - dbau1x00:DBAU1550 +gth2 mips mips32 +incaip mips mips32 +incaip_100MHz mips mips32 incaip - - incaip:CPU_CLOCK_RATE=100000000 +incaip_133MHz mips mips32 incaip - - incaip:CPU_CLOCK_RATE=133000000 +incaip_150MHz mips mips32 incaip - - incaip:CPU_CLOCK_RATE=150000000 +pb1000 mips mips32 pb1x00 - - pb1x00:PB1000 +purple mips mips32 +qemu_mips mips mips32 qemu-mips - - qemu-mips +tb0229 mips mips32 +vct_premium mips mips32 vct micronas - vct:VCT_PREMIUM +vct_premium_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_SMALL_IMAGE +vct_premium_onenand mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND +vct_premium_onenand_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE +vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM +vct_platinum_small mips mips32 vct micronas - vct:VCT_PLATINUM,VCT_SMALL_IMAGE +vct_platinum_onenand mips mips32 vct micronas - vct:VCT_PLATINUM,VCT_ONENAND +vct_platinum_onenand_small mips mips32 vct micronas - vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE +vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC +vct_platinumavc_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE +vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND +vct_platinumavc_onenand_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE PCI5441 nios2 nios2 pci5441 psyent PK1C20 nios2 nios2 pk1c20 psyent EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260 -- 1.7.4.1
On 3/9/11 10:16 PM, daniel.schwierzeck@googlemail.com wrote:
All current CPUs and SoCs are based on Mips32 arch. The complete
Is that true? What about purple SoC? IIUC It's based on MIPS 5Kc and capable of 64-bit, which MIPS32 is 32-bit only architecture.
code resides in the global arch/mips/cpu directory. This is not suitable if other Mips architectures like Mips64 or Octeon should be supported in the future.
Just for the record.
Personally, Octeon is sort of a special case. It's based on MIPS64 architecture, and definitely a MIPS SoC, but not usual MIPS machine. As Aaron already mentioned before, we have very few files sharable with other MIPS machines even in the Linux kernel case. I think it will take long time the Octeon port gets merged to upstream, regard- less of my opinions, because they have a lot of things need to be resolved prior to Octeon itself.
To achieve this the current CPU code is moved to its own mips32 subdirectory. All Mips32 boards have to use mips32 as config switch in board.cfg.
Signed-off-by: Daniel Schwierzeckdaniel.schwierzeck@googlemail.com Cc: Shinya Kuribayashiskuribay@pobox.com
Hi Shinya,
On 03/12/2011 03:43 PM, Shinya Kuribayashi wrote:
On 3/9/11 10:16 PM, daniel.schwierzeck@googlemail.com wrote:
All current CPUs and SoCs are based on Mips32 arch. The complete
Is that true? What about purple SoC? IIUC It's based on MIPS 5Kc and capable of 64-bit, which MIPS32 is 32-bit only architecture.
that was an assumption. I could not find any information about Purple. This patch series is a suggestion. Maybe there are better approaches like arch/mips/cpu/{mips4k|mips5k|mips24k|...|octeon}.
code resides in the global arch/mips/cpu directory. This is not suitable if other Mips architectures like Mips64 or Octeon should be supported in the future.
Just for the record.
Personally, Octeon is sort of a special case. It's based on MIPS64 architecture, and definitely a MIPS SoC, but not usual MIPS machine. As Aaron already mentioned before, we have very few files sharable with other MIPS machines even in the Linux kernel case. I think it will take long time the Octeon port gets merged to upstream, regard- less of my opinions, because they have a lot of things need to be resolved prior to Octeon itself.
My original intention was cleaning up the MIPS CPU directory as preparation to support new SoCs. I included this patch because Aaron asked for this separation some weeks ago but no one answered or commented ;) However I posted this series to get some feedback if such a change is wanted or acceptable. If so I prepare a new patch series. At least I hope the SoC separation is acceptable.
Cheers, Daniel
Dear Daniel Schwierzeck,
In message 4D7C147A.5060501@gmail.com you wrote:
All current CPUs and SoCs are based on Mips32 arch. The complete
Is that true? What about purple SoC? IIUC It's based on MIPS 5Kc and capable of 64-bit, which MIPS32 is 32-bit only architecture.
that was an assumption. I could not find any information about Purple. This patch series is a suggestion. Maybe there are better approaches like arch/mips/cpu/{mips4k|mips5k|mips24k|...|octeon}.
Purple is (better: was) indeed a 64 bit system.
OTOH, the purple board has not been actively maintained for several years, and I'm not aware of anybody who still has access to the hardware. If it should cause trouble, it would probably most appropriate to drop the purple support.
Best regards,
Wolfgang Denk
Hello Wolfgang,
2011/3/13 Wolfgang Denk wd@denx.de:
Dear Daniel Schwierzeck,
In message 4D7C147A.5060501@gmail.com you wrote:
All current CPUs and SoCs are based on Mips32 arch. The complete
Is that true? What about purple SoC? IIUC It's based on MIPS 5Kc and capable of 64-bit, which MIPS32 is 32-bit only architecture.
that was an assumption. I could not find any information about Purple. This patch series is a suggestion. Maybe there are better approaches like arch/mips/cpu/{mips4k|mips5k|mips24k|...|octeon}.
Purple is (better: was) indeed a 64 bit system.
OTOH, the purple board has not been actively maintained for several years, and I'm not aware of anybody who still has access to the hardware. If it should cause trouble, it would probably most appropriate to drop the purple support.
shall I include an additional patch that drops Purple support and do you agree to the refactoring of the CPU directory itself?
Best regards, Daniel
Dear Daniel Schwierzeck,
In message AANLkTinP-3rVXVKcxi8_XTra8mKoBzTV88Vu2t1YkP+q@mail.gmail.com you wrote:
OTOH, the purple board has not been actively maintained for several years, and I'm not aware of anybody who still has access to the hardware. =C2=A0If it should cause trouble, it would probably most appropriate to drop the purple support.
shall I include an additional patch that drops Purple support and do you agree
Yes, please, if it reduces the effort for you now.
to the refactoring of the CPU directory itself?
Sorry, I didn't have much time to read it / think about it yet.
Best regards,
Wolfgang Denk
Seperating the SOCs solves most of my problems with the exception of board.c, but then again, we're rather a special case there due to some of the stuff we do.
Not counting our SDK we have around 27Kloc for our platform, a large chunk of that being DDR2/3 memory initialization code. Our SDK currently weighs in at 764Kloc, most of which isn't needed by U-Boot (lots of autogenerated hardware definition files for all our chips).
-Aaron
On Saturday, March 12, 2011 04:48:58 PM Daniel Schwierzeck wrote:
Hi Shinya,
On 03/12/2011 03:43 PM, Shinya Kuribayashi wrote:
On 3/9/11 10:16 PM, daniel.schwierzeck@googlemail.com wrote:
All current CPUs and SoCs are based on Mips32 arch. The complete
Is that true? What about purple SoC? IIUC It's based on MIPS 5Kc and capable of 64-bit, which MIPS32 is 32-bit only architecture.
that was an assumption. I could not find any information about Purple. This patch series is a suggestion. Maybe there are better approaches like arch/mips/cpu/{mips4k|mips5k|mips24k|...|octeon}.
code resides in the global arch/mips/cpu directory. This is not suitable if other Mips architectures like Mips64 or Octeon should be supported in the future.
Just for the record.
Personally, Octeon is sort of a special case. It's based on MIPS64 architecture, and definitely a MIPS SoC, but not usual MIPS machine. As Aaron already mentioned before, we have very few files sharable with other MIPS machines even in the Linux kernel case. I think it will take long time the Octeon port gets merged to upstream, regard- less of my opinions, because they have a lot of things need to be resolved prior to Octeon itself.
My original intention was cleaning up the MIPS CPU directory as preparation to support new SoCs. I included this patch because Aaron asked for this separation some weeks ago but no one answered or commented ;) However I posted this series to get some feedback if such a change is wanted or acceptable. If so I prepare a new patch series. At least I hope the SoC separation is acceptable.
Cheers, Daniel
This fixes a linker error introduced by the previous commit.
Signed-off-by: Daniel Schwierzeck daniel.schwierzeck@googlemail.com Cc: Shinya Kuribayashi skuribay@pobox.com --- board/purple/u-boot.lds | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds index 719f268..982937d 100644 --- a/board/purple/u-boot.lds +++ b/board/purple/u-boot.lds @@ -34,7 +34,7 @@ SECTIONS . = ALIGN(4); .text : { - arch/mips/cpu/start.o (.text) + arch/mips/cpu/mips32/start.o (.text) board/purple/lowlevel_init.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv) -- 1.7.4.1
On 3/9/11 10:16 PM, daniel.schwierzeck@googlemail.com wrote:
This fixes a linker error introduced by the previous commit.
If so, such fix should be made along with that previous commit.
IncaIP is a SoC and its specific code should reside in an own SoC subdirectory.
Signed-off-by: Daniel Schwierzeck daniel.schwierzeck@googlemail.com Shinya Kuribayashi skuribay@pobox.com --- arch/mips/cpu/mips32/Makefile | 2 - arch/mips/cpu/mips32/incaip/Makefile | 46 +++ arch/mips/cpu/mips32/incaip/asc_serial.c | 368 ++++++++++++++++++++++ arch/mips/cpu/mips32/incaip/asc_serial.h | 177 +++++++++++ arch/mips/cpu/mips32/incaip/config.mk | 22 ++ arch/mips/cpu/mips32/{ => incaip}/incaip_clock.c | 0 arch/mips/cpu/mips32/{ => incaip}/incaip_wdt.S | 0 boards.cfg | 8 +- 8 files changed, 617 insertions(+), 6 deletions(-) create mode 100644 arch/mips/cpu/mips32/incaip/Makefile create mode 100644 arch/mips/cpu/mips32/incaip/asc_serial.c create mode 100644 arch/mips/cpu/mips32/incaip/asc_serial.h create mode 100644 arch/mips/cpu/mips32/incaip/config.mk rename arch/mips/cpu/mips32/{ => incaip}/incaip_clock.c (100%) rename arch/mips/cpu/mips32/{ => incaip}/incaip_wdt.S (100%)
diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile index 06df8d1..4339ef0 100644 --- a/arch/mips/cpu/mips32/Makefile +++ b/arch/mips/cpu/mips32/Makefile @@ -29,8 +29,6 @@ START = start.o SOBJS-y = cache.o COBJS-y = cpu.o interrupts.o
-SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o -COBJS-$(CONFIG_INCA_IP) += asc_serial.o incaip_clock.o COBJS-$(CONFIG_PURPLE) += asc_serial.o COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
diff --git a/arch/mips/cpu/mips32/incaip/Makefile b/arch/mips/cpu/mips32/incaip/Makefile new file mode 100644 index 0000000..9c2b1aa --- /dev/null +++ b/arch/mips/cpu/mips32/incaip/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +SOBJS = incaip_wdt.o +COBJS = incaip_clock.o asc_serial.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.c b/arch/mips/cpu/mips32/incaip/asc_serial.c new file mode 100644 index 0000000..be686c2 --- /dev/null +++ b/arch/mips/cpu/mips32/incaip/asc_serial.c @@ -0,0 +1,368 @@ +/* + * (INCA) ASC UART support + */ + +#include <config.h> + +#ifdef CONFIG_PURPLE +#define serial_init asc_serial_init +#define serial_putc asc_serial_putc +#define serial_puts asc_serial_puts +#define serial_getc asc_serial_getc +#define serial_tstc asc_serial_tstc +#define serial_setbrg asc_serial_setbrg +#endif + +#include <common.h> +#include <asm/inca-ip.h> +#include "asc_serial.h" + +#ifdef CONFIG_PURPLE + +#undef ASC_FIFO_PRESENT +#define TOUT_LOOP 100000 + +/* Set base address for second FPI interrupt control register bank */ +#define SFPI_INTCON_BASEADDR 0xBF0F0000 + +/* Register offset from base address */ +#define FBS_ISR 0x00000000 /* Interrupt status register */ +#define FBS_IMR 0x00000008 /* Interrupt mask register */ +#define FBS_IDIS 0x00000010 /* Interrupt disable register */ + +/* Interrupt status register bits */ +#define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */ +#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */ +#define FBS_ISR_AE 0x00000010 /* ASC error interrupt */ +#define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */ +#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */ +#define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */ + +#else + +#define ASC_FIFO_PRESENT + +#endif + + +#define SET_BIT(reg, mask) reg |= (mask) +#define CLEAR_BIT(reg, mask) reg &= (~mask) +#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) +#define SET_BITS(reg, mask) SET_BIT(reg, mask) +#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} + +extern uint incaip_get_fpiclk(void); + +static int serial_setopt (void); + +/* pointer to ASC register base address */ +static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC; + +/****************************************************************************** +* +* serial_init - initialize a INCAASC channel +* +* This routine initializes the number of data bits, parity +* and set the selected baud rate. Interrupts are disabled. +* Set the modem control signals if the option is selected. +* +* RETURNS: N/A +*/ + +int serial_init (void) +{ +#ifdef CONFIG_INCA_IP + /* we have to set PMU.EN13 bit to enable an ASC device*/ + INCAASC_PMU_ENABLE(13); +#endif + + /* and we have to set CLC register*/ + CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS); + SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001); + + /* initialy we are in async mode */ + pAsc->asc_con = ASCCON_M_8ASYNC; + + /* select input port */ + pAsc->asc_pisel = (CONSOLE_TTY & 0x1); + +#ifdef ASC_FIFO_PRESENT + /* TXFIFO's filling level */ + SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK, + ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL); + /* enable TXFIFO */ + SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN); + + /* RXFIFO's filling level */ + SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK, + ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL); + /* enable RXFIFO */ + SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN); +#endif + + /* enable error signals */ + SET_BIT(pAsc->asc_con, ASCCON_FEN); + SET_BIT(pAsc->asc_con, ASCCON_OEN); + +#ifdef CONFIG_INCA_IP + /* acknowledge ASC interrupts */ + ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL); + + /* disable ASC interrupts */ + ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL); +#endif + +#ifdef ASC_FIFO_PRESENT + /* set FIFOs into the transparent mode */ + SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN); + SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN); +#endif + + /* set baud rate */ + serial_setbrg(); + + /* set the options */ + serial_setopt(); + + return 0; +} + +void serial_setbrg (void) +{ + ulong uiReloadValue, fdv; + ulong f_ASC; + +#ifdef CONFIG_INCA_IP + f_ASC = incaip_get_fpiclk(); +#else + f_ASC = ASC_CLOCK_RATE; +#endif + +#ifndef INCAASC_USE_FDV + fdv = 2; + uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1; +#else + fdv = INCAASC_FDV_HIGH_BAUDRATE; + uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1; +#endif /* INCAASC_USE_FDV */ + + if ( (uiReloadValue < 0) || (uiReloadValue > 8191) ) + { +#ifndef INCAASC_USE_FDV + fdv = 3; + uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1; +#else + fdv = INCAASC_FDV_LOW_BAUDRATE; + uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1; +#endif /* INCAASC_USE_FDV */ + + if ( (uiReloadValue < 0) || (uiReloadValue > 8191) ) + { + return; /* can't impossibly generate that baud rate */ + } + } + + /* Disable Baud Rate Generator; BG should only be written when R=0 */ + CLEAR_BIT(pAsc->asc_con, ASCCON_R); + +#ifndef INCAASC_USE_FDV + /* + * Disable Fractional Divider (FDE) + * Divide clock by reload-value + constant (BRS) + */ + /* FDE = 0 */ + CLEAR_BIT(pAsc->asc_con, ASCCON_FDE); + + if ( fdv == 2 ) + CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */ + else + SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */ + +#else /* INCAASC_USE_FDV */ + + /* Enable Fractional Divider */ + SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */ + + /* Set fractional divider value */ + pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK; + +#endif /* INCAASC_USE_FDV */ + + /* Set reload value in BG */ + pAsc->asc_bg = uiReloadValue; + + /* Enable Baud Rate Generator */ + SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */ +} + +/******************************************************************************* +* +* serial_setopt - set the serial options +* +* Set the channel operating mode to that specified. Following options +* are supported: CREAD, CSIZE, PARENB, and PARODD. +* +* Note, this routine disables the transmitter. The calling routine +* may have to re-enable it. +* +* RETURNS: +* Returns 0 to indicate success, otherwise -1 is returned +*/ + +static int serial_setopt (void) +{ + ulong con; + + switch ( ASC_OPTIONS & ASCOPT_CSIZE ) + { + /* 7-bit-data */ + case ASCOPT_CS7: + con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */ + break; + + /* 8-bit-data */ + case ASCOPT_CS8: + if ( ASC_OPTIONS & ASCOPT_PARENB ) + con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */ + else + con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */ + break; + + /* + * only 7 and 8-bit frames are supported + * if we don't use IOCTL extensions + */ + default: + return -1; + } + + if ( ASC_OPTIONS & ASCOPT_STOPB ) + SET_BIT(con, ASCCON_STP); /* 2 stop bits */ + else + CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */ + + if ( ASC_OPTIONS & ASCOPT_PARENB ) + SET_BIT(con, ASCCON_PEN); /* enable parity checking */ + else + CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */ + + if ( ASC_OPTIONS & ASCOPT_PARODD ) + SET_BIT(con, ASCCON_ODD); /* odd parity */ + else + CLEAR_BIT(con, ASCCON_ODD); /* even parity */ + + if ( ASC_OPTIONS & ASCOPT_CREAD ) + SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */ + + pAsc->asc_con |= con; + + return 0; +} + +void serial_putc (const char c) +{ +#ifdef ASC_FIFO_PRESENT + uint txFl = 0; +#else + uint timeout = 0; +#endif + + if (c == '\n') serial_putc ('\r'); + +#ifdef ASC_FIFO_PRESENT + /* check do we have a free space in the TX FIFO */ + /* get current filling level */ + do + { + txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; + } + while ( txFl == INCAASC_TXFIFO_FULL ); +#else + + while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & + FBS_ISR_AB)) + { + if (timeout++ > TOUT_LOOP) + { + break; + } + } +#endif + + pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */ + +#ifndef ASC_FIFO_PRESENT + *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB | + FBS_ISR_AT; +#endif + + /* check for errors */ + if ( pAsc->asc_con & ASCCON_OE ) + { + SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); + return; + } +} + +void serial_puts (const char *s) +{ + while (*s) + { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + ulong symbol_mask; + char c; + + while (!serial_tstc()); + + symbol_mask = + ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff); + + c = (char)(pAsc->asc_rbuf & symbol_mask); + +#ifndef ASC_FIFO_PRESENT + *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR; +#endif + + return c; +} + +int serial_tstc (void) +{ + int res = 1; + +#ifdef ASC_FIFO_PRESENT + if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) + { + res = 0; + } +#else + if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & + FBS_ISR_AR)) + + { + res = 0; + } +#endif + else if ( pAsc->asc_con & ASCCON_FE ) + { + SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE); + res = 0; + } + else if ( pAsc->asc_con & ASCCON_PE ) + { + SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE); + res = 0; + } + else if ( pAsc->asc_con & ASCCON_OE ) + { + SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); + res = 0; + } + + return res; +} diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.h b/arch/mips/cpu/mips32/incaip/asc_serial.h new file mode 100644 index 0000000..7ffdcfa --- /dev/null +++ b/arch/mips/cpu/mips32/incaip/asc_serial.h @@ -0,0 +1,177 @@ +/* incaAscSio.h - (INCA) ASC UART tty driver header */ + +#ifndef __INCincaAscSioh +#define __INCincaAscSioh + +#include <asm/inca-ip.h> + +/* channel operating modes */ +#define ASCOPT_CSIZE 0x00000003 +#define ASCOPT_CS7 0x00000001 +#define ASCOPT_CS8 0x00000002 +#define ASCOPT_PARENB 0x00000004 +#define ASCOPT_STOPB 0x00000008 +#define ASCOPT_PARODD 0x00000010 +#define ASCOPT_CREAD 0x00000020 + +#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) + +/* ASC input select (0 or 1) */ +#define CONSOLE_TTY 0 + +/* use fractional divider for baudrate settings */ +#define INCAASC_USE_FDV + +#ifdef INCAASC_USE_FDV + #define INCAASC_FDV_LOW_BAUDRATE 71 + #define INCAASC_FDV_HIGH_BAUDRATE 453 +#endif /*INCAASC_USE_FDV*/ + + +#define INCAASC_TXFIFO_FL 1 +#define INCAASC_RXFIFO_FL 1 +#define INCAASC_TXFIFO_FULL 16 + +/* interrupt lines masks for the ASC device interrupts*/ +/* change these macroses if it's necessary */ +#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */ + +#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */ +#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */ +#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */ +#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/ + +/* interrupt controller access macros */ +#define ASC_INTERRUPTS_ENABLE(X) \ + *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X; +#define ASC_INTERRUPTS_DISABLE(X) \ + *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X; +#define ASC_INTERRUPTS_CLEAR(X) \ + *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X; + +/* CLC register's bits and bitfields */ +#define ASCCLC_DISR 0x00000001 +#define ASCCLC_DISS 0x00000002 +#define ASCCLC_RMCMASK 0x0000FF00 +#define ASCCLC_RMCOFFSET 8 + +/* CON register's bits and bitfields */ +#define ASCCON_MODEMASK 0x0007 + #define ASCCON_M_8SYNC 0x0 + #define ASCCON_M_8ASYNC 0x1 + #define ASCCON_M_8IRDAASYNC 0x2 + #define ASCCON_M_7ASYNCPAR 0x3 + #define ASCCON_M_9ASYNC 0x4 + #define ASCCON_M_8WAKEUPASYNC 0x5 + #define ASCCON_M_8ASYNCPAR 0x7 +#define ASCCON_STP 0x0008 +#define ASCCON_REN 0x0010 +#define ASCCON_PEN 0x0020 +#define ASCCON_FEN 0x0040 +#define ASCCON_OEN 0x0080 +#define ASCCON_PE 0x0100 +#define ASCCON_FE 0x0200 +#define ASCCON_OE 0x0400 +#define ASCCON_FDE 0x0800 +#define ASCCON_ODD 0x1000 +#define ASCCON_BRS 0x2000 +#define ASCCON_LB 0x4000 +#define ASCCON_R 0x8000 + +/* WHBCON register's bits and bitfields */ +#define ASCWHBCON_CLRREN 0x0010 +#define ASCWHBCON_SETREN 0x0020 +#define ASCWHBCON_CLRPE 0x0100 +#define ASCWHBCON_CLRFE 0x0200 +#define ASCWHBCON_CLROE 0x0400 +#define ASCWHBCON_SETPE 0x0800 +#define ASCWHBCON_SETFE 0x1000 +#define ASCWHBCON_SETOE 0x2000 + +/* ABCON register's bits and bitfields */ +#define ASCABCON_ABEN 0x0001 +#define ASCABCON_AUREN 0x0002 +#define ASCABCON_ABSTEN 0x0004 +#define ASCABCON_ABDETEN 0x0008 +#define ASCABCON_FCDETEN 0x0010 +#define ASCABCON_EMMASK 0x0300 + #define ASCABCON_EMOFF 8 + #define ASCABCON_EM_DISAB 0x0 + #define ASCABCON_EM_DURAB 0x1 + #define ASCABCON_EM_ALWAYS 0x2 +#define ASCABCON_TXINV 0x0400 +#define ASCABCON_RXINV 0x0800 + +/* FDV register mask, offset and bitfields*/ +#define ASCFDV_VALUE_MASK 0x000001FF + +/* WHBABCON register's bits and bitfields */ +#define ASCWHBABCON_SETABEN 0x0001 +#define ASCWHBABCON_CLRABEN 0x0002 + +/* ABSTAT register's bits and bitfields */ +#define ASCABSTAT_FCSDET 0x0001 +#define ASCABSTAT_FCCDET 0x0002 +#define ASCABSTAT_SCSDET 0x0004 +#define ASCABSTAT_SCCDET 0x0008 +#define ASCABSTAT_DETWAIT 0x0010 + +/* WHBABSTAT register's bits and bitfields */ +#define ASCWHBABSTAT_CLRFCSDET 0x0001 +#define ASCWHBABSTAT_SETFCSDET 0x0002 +#define ASCWHBABSTAT_CLRFCCDET 0x0004 +#define ASCWHBABSTAT_SETFCCDET 0x0008 +#define ASCWHBABSTAT_CLRSCSDET 0x0010 +#define ASCWHBABSTAT_SETSCSDET 0x0020 +#define ASCWHBABSTAT_SETSCCDET 0x0040 +#define ASCWHBABSTAT_CLRSCCDET 0x0080 +#define ASCWHBABSTAT_CLRDETWAIT 0x0100 +#define ASCWHBABSTAT_SETDETWAIT 0x0200 + +/* TXFCON register's bits and bitfields */ +#define ASCTXFCON_TXFEN 0x0001 +#define ASCTXFCON_TXFFLU 0x0002 +#define ASCTXFCON_TXTMEN 0x0004 +#define ASCTXFCON_TXFITLMASK 0x3F00 +#define ASCTXFCON_TXFITLOFF 8 + +/* RXFCON register's bits and bitfields */ +#define ASCRXFCON_RXFEN 0x0001 +#define ASCRXFCON_RXFFLU 0x0002 +#define ASCRXFCON_RXTMEN 0x0004 +#define ASCRXFCON_RXFITLMASK 0x3F00 +#define ASCRXFCON_RXFITLOFF 8 + +/* FSTAT register's bits and bitfields */ +#define ASCFSTAT_RXFFLMASK 0x003F +#define ASCFSTAT_TXFFLMASK 0x3F00 +#define ASCFSTAT_TXFFLOFF 8 + +#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT); + +typedef struct /* incaAsc_t */ +{ + volatile unsigned long asc_clc; /*0x0000*/ + volatile unsigned long asc_pisel; /*0x0004*/ + volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/ + volatile unsigned long asc_con; /*0x0010*/ + volatile unsigned long asc_bg; /*0x0014*/ + volatile unsigned long asc_fdv; /*0x0018*/ + volatile unsigned long asc_pmw; /* not used */ /*0x001C*/ + volatile unsigned long asc_tbuf; /*0x0020*/ + volatile unsigned long asc_rbuf; /*0x0024*/ + volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/ + volatile unsigned long asc_abcon; /*0x0030*/ + volatile unsigned long asc_abstat; /* not used */ /*0x0034*/ + volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/ + volatile unsigned long asc_rxfcon; /*0x0040*/ + volatile unsigned long asc_txfcon; /*0x0044*/ + volatile unsigned long asc_fstat; /*0x0048*/ + volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/ + volatile unsigned long asc_whbcon; /*0x0050*/ + volatile unsigned long asc_whbabcon; /*0x0054*/ + volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/ + +} incaAsc_t; + +#endif /* __INCincaAscSioh */ diff --git a/arch/mips/cpu/mips32/incaip/config.mk b/arch/mips/cpu/mips32/incaip/config.mk new file mode 100644 index 0000000..3516213 --- /dev/null +++ b/arch/mips/cpu/mips32/incaip/config.mk @@ -0,0 +1,22 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# diff --git a/arch/mips/cpu/mips32/incaip_clock.c b/arch/mips/cpu/mips32/incaip/incaip_clock.c similarity index 100% rename from arch/mips/cpu/mips32/incaip_clock.c rename to arch/mips/cpu/mips32/incaip/incaip_clock.c diff --git a/arch/mips/cpu/mips32/incaip_wdt.S b/arch/mips/cpu/mips32/incaip/incaip_wdt.S similarity index 100% rename from arch/mips/cpu/mips32/incaip_wdt.S rename to arch/mips/cpu/mips32/incaip/incaip_wdt.S diff --git a/boards.cfg b/boards.cfg index 8f63b6c..4da68ac 100644 --- a/boards.cfg +++ b/boards.cfg @@ -223,10 +223,10 @@ dbau1500 mips mips32 dbau1x00 - dbau1550 mips mips32 dbau1x00 - - dbau1x00:DBAU1550 dbau1550_el mips mips32 dbau1x00 - - dbau1x00:DBAU1550 gth2 mips mips32 -incaip mips mips32 -incaip_100MHz mips mips32 incaip - - incaip:CPU_CLOCK_RATE=100000000 -incaip_133MHz mips mips32 incaip - - incaip:CPU_CLOCK_RATE=133000000 -incaip_150MHz mips mips32 incaip - - incaip:CPU_CLOCK_RATE=150000000 +incaip mips mips32 incaip - incaip +incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000 +incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000 +incaip_150MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=150000000 pb1000 mips mips32 pb1x00 - - pb1x00:PB1000 purple mips mips32 qemu_mips mips mips32 qemu-mips - - qemu-mips -- 1.7.4.1
Purple is a SoC and its specific code should reside in an own SoC subdirectory.
Signed-off-by: Daniel Schwierzeck daniel.schwierzeck@googlemail.com Shinya Kuribayashi skuribay@pobox.com --- arch/mips/cpu/mips32/Makefile | 1 - arch/mips/cpu/mips32/purple/Makefile | 45 ++++++++++++++++++++++++ arch/mips/cpu/mips32/{ => purple}/asc_serial.c | 0 arch/mips/cpu/mips32/{ => purple}/asc_serial.h | 0 arch/mips/cpu/mips32/purple/config.mk | 22 +++++++++++ boards.cfg | 2 +- 6 files changed, 68 insertions(+), 2 deletions(-) create mode 100644 arch/mips/cpu/mips32/purple/Makefile rename arch/mips/cpu/mips32/{ => purple}/asc_serial.c (100%) rename arch/mips/cpu/mips32/{ => purple}/asc_serial.h (100%) create mode 100644 arch/mips/cpu/mips32/purple/config.mk
diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile index 4339ef0..88e3023 100644 --- a/arch/mips/cpu/mips32/Makefile +++ b/arch/mips/cpu/mips32/Makefile @@ -29,7 +29,6 @@ START = start.o SOBJS-y = cache.o COBJS-y = cpu.o interrupts.o
-COBJS-$(CONFIG_PURPLE) += asc_serial.o COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/arch/mips/cpu/mips32/purple/Makefile b/arch/mips/cpu/mips32/purple/Makefile new file mode 100644 index 0000000..e8c81e8 --- /dev/null +++ b/arch/mips/cpu/mips32/purple/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS = asc_serial.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/mips/cpu/mips32/asc_serial.c b/arch/mips/cpu/mips32/purple/asc_serial.c similarity index 100% rename from arch/mips/cpu/mips32/asc_serial.c rename to arch/mips/cpu/mips32/purple/asc_serial.c diff --git a/arch/mips/cpu/mips32/asc_serial.h b/arch/mips/cpu/mips32/purple/asc_serial.h similarity index 100% rename from arch/mips/cpu/mips32/asc_serial.h rename to arch/mips/cpu/mips32/purple/asc_serial.h diff --git a/arch/mips/cpu/mips32/purple/config.mk b/arch/mips/cpu/mips32/purple/config.mk new file mode 100644 index 0000000..3516213 --- /dev/null +++ b/arch/mips/cpu/mips32/purple/config.mk @@ -0,0 +1,22 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# diff --git a/boards.cfg b/boards.cfg index 4da68ac..0eb5b90 100644 --- a/boards.cfg +++ b/boards.cfg @@ -228,7 +228,7 @@ incaip_100MHz mips mips32 incaip - incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000 incaip_150MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=150000000 pb1000 mips mips32 pb1x00 - - pb1x00:PB1000 -purple mips mips32 +purple mips mips32 - - purple qemu_mips mips mips32 qemu-mips - - qemu-mips tb0229 mips mips32 vct_premium mips mips32 vct micronas - vct:VCT_PREMIUM -- 1.7.4.1
From: Daniel Schwierzeck daniel.schwierzeck@googlemail.com
Au1x00 is a SoC and its specific code should reside in an own SoC subdirectory.
Signed-off-by: Daniel Schwierzeck daniel.schwierzeck@googlemail.com Shinya Kuribayashi skuribay@pobox.com --- arch/mips/cpu/mips32/Makefile | 2 - arch/mips/cpu/mips32/au1x00/Makefile | 45 ++++++++++++++++++++ arch/mips/cpu/mips32/{ => au1x00}/au1x00_eth.c | 0 arch/mips/cpu/mips32/{ => au1x00}/au1x00_serial.c | 0 .../mips/cpu/mips32/{ => au1x00}/au1x00_usb_ohci.c | 0 .../mips/cpu/mips32/{ => au1x00}/au1x00_usb_ohci.h | 0 arch/mips/cpu/mips32/au1x00/config.mk | 22 ++++++++++ boards.cfg | 14 +++--- 8 files changed, 74 insertions(+), 9 deletions(-) create mode 100644 arch/mips/cpu/mips32/au1x00/Makefile rename arch/mips/cpu/mips32/{ => au1x00}/au1x00_eth.c (100%) rename arch/mips/cpu/mips32/{ => au1x00}/au1x00_serial.c (100%) rename arch/mips/cpu/mips32/{ => au1x00}/au1x00_usb_ohci.c (100%) rename arch/mips/cpu/mips32/{ => au1x00}/au1x00_usb_ohci.h (100%) create mode 100644 arch/mips/cpu/mips32/au1x00/config.mk
diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile index 88e3023..e315c1b 100644 --- a/arch/mips/cpu/mips32/Makefile +++ b/arch/mips/cpu/mips32/Makefile @@ -29,8 +29,6 @@ START = start.o SOBJS-y = cache.o COBJS-y = cpu.o interrupts.o
-COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o - SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) START := $(addprefix $(obj),$(START)) diff --git a/arch/mips/cpu/mips32/au1x00/Makefile b/arch/mips/cpu/mips32/au1x00/Makefile new file mode 100644 index 0000000..dc58475 --- /dev/null +++ b/arch/mips/cpu/mips32/au1x00/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/mips/cpu/mips32/au1x00_eth.c b/arch/mips/cpu/mips32/au1x00/au1x00_eth.c similarity index 100% rename from arch/mips/cpu/mips32/au1x00_eth.c rename to arch/mips/cpu/mips32/au1x00/au1x00_eth.c diff --git a/arch/mips/cpu/mips32/au1x00_serial.c b/arch/mips/cpu/mips32/au1x00/au1x00_serial.c similarity index 100% rename from arch/mips/cpu/mips32/au1x00_serial.c rename to arch/mips/cpu/mips32/au1x00/au1x00_serial.c diff --git a/arch/mips/cpu/mips32/au1x00_usb_ohci.c b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c similarity index 100% rename from arch/mips/cpu/mips32/au1x00_usb_ohci.c rename to arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c diff --git a/arch/mips/cpu/mips32/au1x00_usb_ohci.h b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h similarity index 100% rename from arch/mips/cpu/mips32/au1x00_usb_ohci.h rename to arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h diff --git a/arch/mips/cpu/mips32/au1x00/config.mk b/arch/mips/cpu/mips32/au1x00/config.mk new file mode 100644 index 0000000..3516213 --- /dev/null +++ b/arch/mips/cpu/mips32/au1x00/config.mk @@ -0,0 +1,22 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# diff --git a/boards.cfg b/boards.cfg index 0eb5b90..493fe86 100644 --- a/boards.cfg +++ b/boards.cfg @@ -217,17 +217,17 @@ M5282EVB m68k mcf52x2 m5282evb freesca M53017EVB m68k mcf52x2 m53017evb freescale EP2500 m68k mcf52x2 ep2500 Mercury microblaze-generic microblaze microblaze microblaze-generic xilinx -dbau1000 mips mips32 dbau1x00 - - dbau1x00:DBAU1000 -dbau1100 mips mips32 dbau1x00 - - dbau1x00:DBAU1100 -dbau1500 mips mips32 dbau1x00 - - dbau1x00:DBAU1500 -dbau1550 mips mips32 dbau1x00 - - dbau1x00:DBAU1550 -dbau1550_el mips mips32 dbau1x00 - - dbau1x00:DBAU1550 -gth2 mips mips32 +dbau1000 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1000 +dbau1100 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1100 +dbau1500 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1500 +dbau1550 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550 +dbau1550_el mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550 +gth2 mips mips32 - - au1x00 incaip mips mips32 incaip - incaip incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000 incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000 incaip_150MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=150000000 -pb1000 mips mips32 pb1x00 - - pb1x00:PB1000 +pb1000 mips mips32 pb1x00 - au1x00 pb1x00:PB1000 purple mips mips32 - - purple qemu_mips mips mips32 qemu-mips - - qemu-mips tb0229 mips mips32
The current Mips CPU config.mk code always expects a Mips 4kc core and toolchain. This is not appropiate for other toolchains and CPUs/SoCs.
Replace the current MIPSFLAGS code by cc-option macro and use -march=mips32r2 as default optimization level for all Mips32 CPUs. Replace the endianess determination code from toolchain prefix by a more generic one inspired by the Linux arch/mips/Makefile. Move the -mtune setting to the SoC specific config.mk makefiles.
Signed-off-by: Daniel Schwierzeck daniel.schwierzeck@googlemail.com Cc: Shinya Kuribayashi skuribay@pobox.com --- arch/mips/cpu/mips32/au1x00/config.mk | 2 ++ arch/mips/cpu/mips32/config.mk | 21 +++++++-------------- arch/mips/cpu/mips32/incaip/config.mk | 2 ++ arch/mips/cpu/mips32/purple/config.mk | 2 ++ 4 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/arch/mips/cpu/mips32/au1x00/config.mk b/arch/mips/cpu/mips32/au1x00/config.mk index 3516213..ecfcb9c 100644 --- a/arch/mips/cpu/mips32/au1x00/config.mk +++ b/arch/mips/cpu/mips32/au1x00/config.mk @@ -20,3 +20,5 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # + +PLATFORM_CPPFLAGS += $(call cc-option,-mtune=4kc) diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk index a173c54..a91dcb4 100644 --- a/arch/mips/cpu/mips32/config.mk +++ b/arch/mips/cpu/mips32/config.mk @@ -20,20 +20,13 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2.[0-9.]+' | cut -d. -f2) -MIPSFLAGS:=$(shell \ -if [ "$v" -lt "14" ]; then \ - echo "-mcpu=4kc"; \ -else \ - echo "-march=4kc -mtune=4kc"; \ -fi)
-ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) -ENDIANNESS = -EL -else -ENDIANNESS = -EB -endif +# Optimization flags for all Mips32 CPUs +MIPSFLAGS = $(call cc-option,-march=mips32r2,-mips32r2 -Wa,-mips32r2)
-MIPSFLAGS += $(ENDIANNESS) +# Determine endianess from toolchain prefix +ENDIANESS = $(shell $(CC) -dumpmachine | \ + grep -q 'mips.*el-.*' && echo -EL || echo -EB) + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) $(ENDIANESS)
-PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/arch/mips/cpu/mips32/incaip/config.mk b/arch/mips/cpu/mips32/incaip/config.mk index 3516213..ecfcb9c 100644 --- a/arch/mips/cpu/mips32/incaip/config.mk +++ b/arch/mips/cpu/mips32/incaip/config.mk @@ -20,3 +20,5 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # + +PLATFORM_CPPFLAGS += $(call cc-option,-mtune=4kc) diff --git a/arch/mips/cpu/mips32/purple/config.mk b/arch/mips/cpu/mips32/purple/config.mk index 3516213..ecfcb9c 100644 --- a/arch/mips/cpu/mips32/purple/config.mk +++ b/arch/mips/cpu/mips32/purple/config.mk @@ -20,3 +20,5 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # + +PLATFORM_CPPFLAGS += $(call cc-option,-mtune=4kc) -- 1.7.4.1
On 3/9/11 10:16 PM, daniel.schwierzeck@googlemail.com wrote:
This patch series refactors the Mips CPU directory and put all current code into an own mips32 subdirectory. Furthermore the SoC specific code of IncaIP, Purple and Au1x00 is moved to separate SoC subdirectories.
Personally I'm not a big fan of current arch/<arch>/cpu/ directory usages in the U-Boot tree. But that's a matter of personal preference, and I've already ended up regarding this area a few years ago. Not having strong opinions now.
When they get ready for merge, please let me know. Then I'll queue them up for the next release, thanks.
participants (5)
-
Aaron Williams -
Daniel Schwierzeck -
daniel.schwierzeck＠googlemail.com
-
Shinya Kuribayashi -
Wolfgang Denk