[U-Boot] [PATCH 0/8] arm-trusted-firmware support for rk3288
This adds support for jumping into aarch32 ATF from u-boot spl similar to how it works on aarch64.
I guess the biggest question might be "why" ;-)
Right now the status quo on Rockchip arm32 socs is, that the linux kernel itself does smp and suspend handling. This precludes us from doing fance things like virtualization but also deep suspend with the DDR in self refresh, due to at least 2 approaches for putting generalized code into sram from the kernel side failed so far.
For Virtualization we need the kernel to start in hyp mode and hence needing to use psci for smp handling as well.
So there are multiple ways for achieving that, we could do - psci in uboot itself is bad for coreboot and barebox who would need to reimplement the same - psci in optee is the solution Rockchip themself choose but only provides precompiled binaries for their arm32 socs and also reimplmenting this in an open way is somewhat of a dead-end because while aarch64 can use op-tee, psci itself is always done in the atf - atf using the somewhat new aarch32 port has the advantage of being able to share a lot of platform code making maintenance together with the aarch64 parts a lot easier
Not having to rely on binary components as part of the boot process is way nicer not only for reproducible builds but also for future proofing projects as binary blobs may not receive updates after some time.
Also it is still possible to use this together with an optee implementation for specific security foobar. The only difference is that while aarch64 can has separate states for secure monitor and secure-os, in aarch32 both need to share the bl32 space, so optee needs to be a payload during the atf build. If no secure-os is needed, atf can use the sp_min payload, which is part of atf.
This works nicely on my rk3288 evb and even virtualization worked already. Full support will still need a modified devicetree to actually make use of the new psci capabilites.
Heiko Stuebner (8): arm: v7: add read_mpidr function for arm32 spl: atf: add arm32 variant rockchip: rk3288: move TPL options to generic position rockchip: rk3288: adjust load addresses rockchip: rk3288: reserve first 2MB when build with ATF support rockchip: rk3288: split evb into its two entities rockchip: rk3288: convert rk3288-evb to use tpl rockchip: rk3288: make both evb variants use atf
arch/arm/dts/Makefile | 3 +- ...evb.dts => rk3288-evb-act8846-u-boot.dtsi} | 33 +- arch/arm/dts/rk3288-evb-act8846.dts | 188 +++++++ arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi | 40 ++ arch/arm/dts/rk3288-evb-rk808.dts | 202 +++++++ arch/arm/dts/rk3288-evb.dtsi | 493 ++++++++---------- arch/arm/include/asm/system.h | 9 + arch/arm/mach-rockchip/Kconfig | 16 + arch/arm/mach-rockchip/rk3288/Kconfig | 16 +- arch/arm/mach-rockchip/rk3288/rk3288.c | 16 + board/rockchip/evb_rk3288/evb-rk3288.c | 14 + board/rockchip/evb_rk3288/fit_spl_atf.its | 52 ++ common/spl/Kconfig | 2 +- common/spl/spl_atf.c | 86 ++- ...defconfig => evb-rk3288-act8846_defconfig} | 14 +- configs/evb-rk3288-rk808_defconfig | 91 ++++ include/atf_common.h | 52 ++ include/configs/rk3288_common.h | 8 +- 18 files changed, 998 insertions(+), 337 deletions(-) rename arch/arm/dts/{rk3288-evb.dts => rk3288-evb-act8846-u-boot.dtsi} (64%) create mode 100644 arch/arm/dts/rk3288-evb-act8846.dts create mode 100644 arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi create mode 100644 arch/arm/dts/rk3288-evb-rk808.dts create mode 100644 board/rockchip/evb_rk3288/fit_spl_atf.its rename configs/{evb-rk3288_defconfig => evb-rk3288-act8846_defconfig} (87%) create mode 100644 configs/evb-rk3288-rk808_defconfig
Function to get the contents of the mpidr register, similar to its arm64 counterpart.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/include/asm/system.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index aed2e3c51e..b5332f4347 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -364,6 +364,15 @@ static inline int is_hyp(void) #endif }
+static inline unsigned long read_mpidr(void) +{ + unsigned long val; + + asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val)); + + return val; +} + static inline unsigned int get_cr(void) { unsigned int val;
On 05/04/2019 10:30, Heiko Stuebner wrote:
Function to get the contents of the mpidr register, similar to its arm64 counterpart.
Signed-off-by: Heiko Stuebner heiko@sntech.de
Reviewed-by: Matthias Brugger mbrugger@suse.com
arch/arm/include/asm/system.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index aed2e3c51e..b5332f4347 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -364,6 +364,15 @@ static inline int is_hyp(void) #endif }
+static inline unsigned long read_mpidr(void) +{
- unsigned long val;
- asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
- return val;
+}
static inline unsigned int get_cr(void) { unsigned int val;
ATF can also support arm32 socs with being a bl32 payload either including optee or the minimal sp_min payload included in ATF itself.
So add the necessary infrasturcture to jump into ATF as bl32 from spl which then will jump into the real u-boot.
We keep using the arm64 datastructures because, while they are named bl31_*, the only difference is not populating the bl31-related fields and making the bl32 ones mandatory, so there really is no need to redefine all of them simply to drop the empty bl31 parts.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- common/spl/Kconfig | 2 +- common/spl/spl_atf.c | 86 ++++++++++++++++++++++++++++++++++++++++++-- include/atf_common.h | 52 +++++++++++++++++++++++++++ 3 files changed, 137 insertions(+), 3 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 206c24076d..ba39c17cf2 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -886,7 +886,7 @@ config SPL_YMODEM_SUPPORT
config SPL_ATF bool "Support ARM Trusted Firmware" - depends on ARM64 + depends on ARM || ARM64 help ATF(ARM Trusted Firmware) is a component for ARM AArch64 which is loaded by SPL (which is considered as BL2 in ATF terminology). diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c index cddab6a735..2fbec29b73 100644 --- a/common/spl/spl_atf.c +++ b/common/spl/spl_atf.c @@ -17,6 +17,9 @@ static struct bl2_to_bl31_params_mem bl31_params_mem; static struct bl31_params *bl2_to_bl31_params;
+typedef void (*atf_entry_t)(struct bl31_params *params, void *plat_params); + +#ifdef CONFIG_ARM64 /** * bl2_plat_get_bl31_params() - prepare params for bl31. * @@ -83,8 +86,6 @@ static inline void raw_write_daif(unsigned int daif) __asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory"); }
-typedef void (*atf_entry_t)(struct bl31_params *params, void *plat_params); - static void bl31_entry(uintptr_t bl31_entry, uintptr_t bl33_entry, uintptr_t fdt_addr) { @@ -98,6 +99,83 @@ static void bl31_entry(uintptr_t bl31_entry, uintptr_t bl33_entry,
atf_entry((void *)bl31_params, (void *)fdt_addr); } +#else /* CONFIG_ARM64 */ +static struct bl31_params *bl2_plat_get_bl32_params(uintptr_t bl33_entry) +{ + struct entry_point_info *bl33_ep_info; + + /* + * Initialise the memory for all the arguments that needs to + * be passed to BL31 + */ + memset(&bl31_params_mem, 0, sizeof(struct bl2_to_bl31_params_mem)); + + /* Assign memory for TF related information */ + bl2_to_bl31_params = &bl31_params_mem.bl31_params; + SET_PARAM_HEAD(bl2_to_bl31_params, ATF_PARAM_BL31, ATF_VERSION_1, 0); + + /* Fill BL31 related information */ + SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, + ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0); + + /* Fill BL32 related information */ + bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, ATF_PARAM_EP, + ATF_VERSION_1, 0); + bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, + ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0); + + /* Fill BL33 related information */ + bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; + bl33_ep_info = &bl31_params_mem.bl33_ep_info; + SET_PARAM_HEAD(bl33_ep_info, ATF_PARAM_EP, ATF_VERSION_1, + ATF_EP_NON_SECURE); + + /* BL33 expects to receive the primary CPU MPID (through r0) */ + bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); + bl33_ep_info->pc = bl33_entry; + bl33_ep_info->spsr = SPSR_MODE32(MODE32_hyp, + SPSR_T_ARM, +#ifdef __ARMEB__ + SPSR_E_BIG, +#else + SPSR_E_LITTLE, +#endif + DISABLE_ALL_EXECPTIONS); + + bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, + ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0); + + return bl2_to_bl31_params; +} + +static inline void raw_write_aif(unsigned int aif) +{ + unsigned int val; + + val = get_cpsr(); + val &= ~SPSR_EXCEPTION_MASK; + val |= aif; + + __asm__ __volatile__("msr cpsr_c, %0\n\t" : : "r" (val) ); +} + +static void bl32_entry(uintptr_t bl32_entry, uintptr_t bl33_entry, + uintptr_t fdt_addr) +{ + struct bl31_params *bl31_params; + atf_entry_t atf_entry = (atf_entry_t)bl32_entry; + + bl31_params = bl2_plat_get_bl32_params(bl33_entry); + + raw_write_aif(SPSR_EXCEPTION_MASK); + dcache_disable(); + + atf_entry((void *)bl31_params, (void *)fdt_addr); +} +#endif /* CONFIG_ARM64 */
static int spl_fit_images_find_uboot(void *blob) { @@ -171,5 +249,9 @@ void spl_invoke_atf(struct spl_image_info *spl_image) * We don't provide a BL3-2 entry yet, but this will be possible * using similar logic. */ +#ifdef CONFIG_ARM64 bl31_entry(spl_image->entry_point, bl33_entry, platform_param); +#else + bl32_entry(spl_image->entry_point, bl33_entry, platform_param); +#endif } diff --git a/include/atf_common.h b/include/atf_common.h index 3a7d40e5f0..9fdb190375 100644 --- a/include/atf_common.h +++ b/include/atf_common.h @@ -32,6 +32,8 @@ #define MODE_RW_64 0x0 #define MODE_RW_32 0x1
+#ifdef CONFIG_ARM64 + #define MODE_EL_SHIFT 0x2 #define MODE_EL_MASK 0x3 #define MODE_EL3 0x3 @@ -66,6 +68,53 @@ #define DISABLE_ALL_EXECPTIONS \ (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
+#else /* CONFIG_ARM64 */ + +#define SPSR_E_SHIFT 9 +#define SPSR_E_MASK 0x1 +#define SPSR_E_LITTLE 0 +#define SPSR_E_BIG 1 + +#define SPSR_T_SHIFT 5 +#define SPSR_T_MASK 0x1 +#define SPSR_T_ARM 0 +#define SPSR_T_THUMB 1 + +#define MODE32_SHIFT 0 +#define MODE32_MASK 0xf +#define MODE32_usr 0x0 +#define MODE32_fiq 0x1 +#define MODE32_irq 0x2 +#define MODE32_svc 0x3 +#define MODE32_mon 0x6 +#define MODE32_abt 0x7 +#define MODE32_hyp 0xa +#define MODE32_und 0xb +#define MODE32_sys 0xf + +#define SPSR_AIF_SHIFT 6 +#define SPSR_AIF_MASK 0x07 + +#define SPSR_MODE32(mode, isa, endian, aif) \ + (MODE_RW_32 << MODE_RW_SHIFT | \ + ((mode) & MODE32_MASK) << MODE32_SHIFT | \ + ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ + ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ + ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) + +#define SPSR_FIQ (1 << 6) +#define SPSR_IRQ (1 << 7) +#define SPSR_SERROR (1 << 8) +#define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR) + +#define AIF_FIQ_BIT (1 << 0) +#define AIF_IRQ_BIT (1 << 1) +#define AIF_ABT_BIT (1 << 2) +#define DISABLE_ALL_EXECPTIONS \ + (AIF_FIQ_BIT | AIF_IRQ_BIT | AIF_ABT_BIT) + +#endif /* CONFIG_ARM64 */ + #ifndef __ASSEMBLY__
/******************************************************************************* @@ -152,6 +201,9 @@ struct image_desc { * BL31 image information is mandatory if this structure is used. If either of * the optional BL32 and BL33 image information is not provided, this is * indicated by the respective image_info pointers being zero. + * + * In ARM32 mode BL31 image information is to be left empty and BL32 + * information becomes mandatory. ******************************************************************************/ struct bl31_params { struct param_header h;
Move the TPL-related options to the generic RK3288 config option protected by "if TPL" conditionals.
This way board wanting TPL support just need to "select TPL" to get all necessary options instead of duplicating all of them.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/mach-rockchip/Kconfig | 15 +++++++++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 15 --------------- 2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b9a026abb5..ba11e8a497 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -63,6 +63,21 @@ config ROCKCHIP_RK3288 select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SPL + select SUPPORT_TPL + select ROCKCHIP_BROM_HELPER if TPL + select TPL_BOOTROM_SUPPORT if TPL + select TPL_CLK if TPL + select TPL_DM if TPL + select TPL_DRIVERS_MISC_SUPPORT if TPL + select TPL_LIBCOMMON_SUPPORT if TPL + select TPL_LIBGENERIC_SUPPORT if TPL + select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL + select TPL_OF_CONTROL if TPL + select TPL_OF_PLATDATA if TPL + select TPL_RAM if TPL + select TPL_REGMAP if TPL + select TPL_SERIAL_SUPPORT if TPL + select TPL_SYSCON if TPL imply USB_FUNCTION_ROCKUSB imply CMD_ROCKUSB help diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index f540b8daec..936faf75ca 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -98,22 +98,7 @@ config TARGET_POPMETAL_RK3288 config TARGET_VYASA_RK3288 bool "Vyasa-RK3288" select BOARD_LATE_INIT - select ROCKCHIP_BROM_HELPER - select SUPPORT_TPL select TPL - select TPL_BOOTROM_SUPPORT - select TPL_CLK - select TPL_DM - select TPL_DRIVERS_MISC_SUPPORT - select TPL_LIBCOMMON_SUPPORT - select TPL_LIBGENERIC_SUPPORT - select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL - select TPL_OF_CONTROL - select TPL_OF_PLATDATA - select TPL_RAM - select TPL_REGMAP - select TPL_SERIAL_SUPPORT - select TPL_SYSCON help Vyasa is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
On Fri, Apr 5, 2019 at 2:04 PM Heiko Stuebner heiko@sntech.de wrote:
Move the TPL-related options to the generic RK3288 config option protected by "if TPL" conditionals.
This way board wanting TPL support just need to "select TPL" to get all necessary options instead of duplicating all of them.
Signed-off-by: Heiko Stuebner heiko@sntech.de
Acked-by: Jagan Teki jagan@amarulasolutions.com
The rk3288 by default uses memory areas for u-boot and runtime parts like pxe+scriptfile that we may want to use for secure firmware and thus mark secure later on. So move the relevant parts a bit away from that.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- include/configs/rk3288_common.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 72a54bc0ab..a36aa96b87 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -20,7 +20,7 @@ #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x0 once return from SPL */ #endif -#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) @@ -48,9 +48,9 @@
/* usb host support */ #define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00000000\0" \ - "pxefile_addr_r=0x00100000\0" \ - "fdt_addr_r=0x01f00000\0" \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x5600000\0" \ "kernel_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x04000000\0"
ATF resides in the first 2MB of ram and will also protect this area from non-secure access.
So similar to other Rockchip socs keep this area from the usable ram.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/mach-rockchip/rk3288/rk3288.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index a725abc5a5..678ab0de65 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -2,11 +2,27 @@ /* * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ +#include <common.h> #include <asm/io.h> #include <asm/arch/hardware.h>
+DECLARE_GLOBAL_DATA_PTR; + #define GRF_SOC_CON2 0xff77024c
+int dram_init_banksize(void) +{ +#ifdef CONFIG_SPL_ATF + size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); + + /* Reserve 0x200000 for ATF bl32 */ + gd->bd->bi_dram[0].start = 0x0200000; + gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; +#endif + + return 0; +} + int arch_cpu_init(void) { /* We do some SoC one time setting here. */
Heiko,
On 04/05/2019 04:30 PM, Heiko Stuebner wrote:
ATF resides in the first 2MB of ram and will also protect this area from non-secure access.
So similar to other Rockchip socs keep this area from the usable ram.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3288/rk3288.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index a725abc5a5..678ab0de65 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -2,11 +2,27 @@ /*
- Copyright (c) 2016 Rockchip Electronics Co., Ltd
*/ +#include <common.h> #include <asm/io.h> #include <asm/arch/hardware.h>
+DECLARE_GLOBAL_DATA_PTR;
#define GRF_SOC_CON2 0xff77024c
+int dram_init_banksize(void)
This break the build for vyasa-rk3288 board: arm: + vyasa-rk3288+spl/arch/arm/mach-rockchip/rk3288-board-spl.o: In function `dram_init_banksize':+arch/arm/mach-rockchip/rk3288-board-spl.c:208: multiple definition of `dram_init_banksize'+spl/arch/arm/mach-rockchip/rk3288/built-in.o:arch/arm/mach-rockchip/rk3288/rk3288.c:25: first defined here
Thanks, - Kever
+{ +#ifdef CONFIG_SPL_ATF
- size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
- /* Reserve 0x200000 for ATF bl32 */
- gd->bd->bi_dram[0].start = 0x0200000;
- gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
+#endif
- return 0;
+}
int arch_cpu_init(void) { /* We do some SoC one time setting here. */
There are actual 2 variants of the rk3288-evb in existence, mainly differing by their pmic. The one currently in u-boot is using the act8846 + syr827 ics for power regulation, while the other variant uses Rockchip's own rk808.
To be able to use u-boot on both, add separate configs and sync down the devicetrees from the Linux kernel for both variants.
As per [0] the SPDX license designation updated a bit as well to match the actual licensing.
[0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?i...
Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/dts/Makefile | 3 +- ...evb.dts => rk3288-evb-act8846-u-boot.dtsi} | 33 +- arch/arm/dts/rk3288-evb-act8846.dts | 188 +++++++ arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi | 40 ++ arch/arm/dts/rk3288-evb-rk808.dts | 202 +++++++ arch/arm/dts/rk3288-evb.dtsi | 493 ++++++++---------- ...defconfig => evb-rk3288-act8846_defconfig} | 4 +- configs/evb-rk3288-rk808_defconfig | 87 ++++ 8 files changed, 738 insertions(+), 312 deletions(-) rename arch/arm/dts/{rk3288-evb.dts => rk3288-evb-act8846-u-boot.dtsi} (64%) create mode 100644 arch/arm/dts/rk3288-evb-act8846.dts create mode 100644 arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi create mode 100644 arch/arm/dts/rk3288-evb-rk808.dts rename configs/{evb-rk3288_defconfig => evb-rk3288-act8846_defconfig} (95%) create mode 100644 configs/evb-rk3288-rk808_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0e2ffdb87f..edbfc34076 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -65,7 +65,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3128-evb.dtb \ rk3188-radxarock.dtb \ rk3229-evb.dtb \ - rk3288-evb.dtb \ + rk3288-evb-act8846.dtb \ + rk3288-evb-rk808.dtb \ rk3288-fennec.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb-act8846-u-boot.dtsi similarity index 64% rename from arch/arm/dts/rk3288-evb.dts rename to arch/arm/dts/rk3288-evb-act8846-u-boot.dtsi index 575de44c05..ee49d3787d 100644 --- a/arch/arm/dts/rk3288-evb.dts +++ b/arch/arm/dts/rk3288-evb-act8846-u-boot.dtsi @@ -1,20 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. */
-/dts-v1/; -#include "rk3288-evb.dtsi" - -/ { - model = "Evb-RK3288"; - compatible = "evb-rk3288,evb-rk3288", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - &dmc { rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 @@ -26,31 +14,26 @@ rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; };
-&pinctrl { +&sdmmc { u-boot,dm-pre-reloc; };
-&pwm1 { - status = "okay"; -}; - -&uart2 { +&emmc { u-boot,dm-pre-reloc; - reg-shift = <2>; };
-&sdmmc { +&gpio3 { u-boot,dm-pre-reloc; };
-&emmc { +&gpio8 { u-boot,dm-pre-reloc; };
-&gpio3 { +&pinctrl { u-boot,dm-pre-reloc; };
-&gpio8 { +&uart2 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288-evb-act8846.dts b/arch/arm/dts/rk3288-evb-act8846.dts new file mode 100644 index 0000000000..6204f8ce8f --- /dev/null +++ b/arch/arm/dts/rk3288-evb-act8846.dts @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3288-evb.dtsi" +#include "rk3288-evb-act8846-u-boot.dtsi" + +/ { + compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288"; + + vcc_lcd: vcc-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_en>; + regulator-name = "vcc_lcd"; + vin-supply = <&vcc_io>; + }; + + vcc_wl: vcc-wl { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwr>; + regulator-name = "vcc_wl"; + vin-supply = <&vcc_18>; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + fcs,suspend-voltage-selector = <1>; + reg = <0x40>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + fcs,suspend-voltage-selector = <1>; + reg = <0x41>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + + interrupt-parent = <&gpio0>; + interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + status = "okay"; + + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "VCC_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "VCCIO_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "VDD10_LCD"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_codec: REG7 { + regulator-name = "VCCA_CODEC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_tp: REG8 { + regulator-name = "VCCA_TP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccio_pmu: REG9 { + regulator-name = "VCCIO_PMU"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_10: REG10 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "VCC18_LCD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&panel { + power-supply = <&vcc_lcd>; +}; + +&pinctrl { + lcd { + lcd_en: lcd-en { + rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_pwr: wifi-pwr { + rockchip,pins = <7 9 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi b/arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi new file mode 100644 index 0000000000..3822526512 --- /dev/null +++ b/arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + */ + +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + /* Add a dummy value to cause of-platdata think this is bytes */ + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio8 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-evb-rk808.dts b/arch/arm/dts/rk3288-evb-rk808.dts new file mode 100644 index 0000000000..76d43a2819 --- /dev/null +++ b/arch/arm/dts/rk3288-evb-rk808.dts @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3288-evb.dtsi" +#include "rk3288-evb-rk808-u-boot.dtsi" + +/ { + compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; +}; + +&i2c0 { + clock-frequency = <400000>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_18>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vccio_pmu>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_codec: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_wl: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_wl"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&panel { + power-supply = <&vcc_lcd>; +}; diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi index 04902c0bd3..21dfe13171 100644 --- a/arch/arm/dts/rk3288-evb.dtsi +++ b/arch/arm/dts/rk3288-evb.dtsi @@ -1,92 +1,58 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> #include "rk3288.dtsi"
/ { - memory { - reg = <0 0x80000000>; + chosen { + stdout-path = &uart2; };
- ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; };
- keys: gpio-keys { - compatible = "gpio-keys"; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>;
- button@0 { - gpio-key,wakeup = <1>; - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = <116>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; + button-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <100000>; }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - };
- vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; + button-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <300000>; + };
- vcc_5v: usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; + menu { + label = "Menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <640000>; + };
- vcc_host_5v: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; + esc { + label = "Esc"; + linux,code = <KEY_ESC>; + press-threshold-microvolt = <1000000>; + };
- vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; + home { + label = "Home"; + linux,code = <KEY_HOME>; + press-threshold-microvolt = <1300000>; + }; };
backlight: backlight { compatible = "pwm-backlight"; - power-supply = <&vcc_sys>; - enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 @@ -120,12 +86,35 @@ 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; - default-brightness-level = <50>; - pwms = <&pwm0 0 25000 0>; + default-brightness-level = <128>; + enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - pwm-delay-us = <10000>; - status = "disabled"; + pinctrl-0 = <&bl_en>; + pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + label = "GPIO Key Power"; + linux,input-type = <1>; + wakeup-source; + debounce-interval = <100>; + }; };
panel: panel { @@ -135,6 +124,57 @@ enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; status = "disabled"; }; + + /* This turns on USB vbus for both host0 (ehci) and host1 (dwc2) */ + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_pwr>; + regulator-name = "vcc_phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* + * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from + * vcc_io directly. Those boards won't be able to power cycle SD cards + * but it shouldn't hurt to toggle this pin there anyway. + */ + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; };
&cpu0 { @@ -142,21 +182,38 @@ };
&emmc { - broken-cd; bus-width = <8>; cap-mmc-highspeed; disable-wp; non-removable; - num-slots = <1>; pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_18>; status = "okay"; };
+&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; +}; + &gmac { + phy-supply = <&vcc_phy>; phy-mode = "rgmii"; clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; + snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; snps,reset-active-low; snps,reset-delays-us = <0 10000 1000000>; assigned-clocks = <&cru SCLK_MAC>; @@ -165,6 +222,11 @@ pinctrl-0 = <&rgmii_pins>; tx_delay = <0x30>; rx_delay = <0x10>; + status = "ok"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; status = "okay"; };
@@ -174,253 +236,124 @@ };
&i2c0 { - clock-frequency = <400000>; status = "okay"; +};
- vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; +&i2c5 { + status = "okay"; +};
- vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; +&wdt { + status = "okay"; +};
- hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio7>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - }; +&pwm0 { + status = "okay"; +};
- act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_hold>; - system-power-controller; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_codec: REG7 { - regulator-name = "vcca_codec"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_tp: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccio_pmu: REG9 { - regulator-name = "vccio_pmu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; };
-&i2c1 { +&uart2 { status = "okay"; };
-&i2c2 { +&uart3 { status = "okay"; };
-&i2c4 { +&uart4 { status = "okay"; };
-&i2c5 { +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ status = "okay"; };
&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; };
- pcfg_output_low: pcfg-output-low { - output-low; + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; };
- act8846 { - pwr_hold: pwr-hold { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_output_high>; + backlight { + bl_en: bl-en { + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; }; };
- hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; }; };
- keys { - pwr_key: pwr-key { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + lcd { + lcd_cs: lcd-cs { + rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; }; };
sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on EVB board so bump up to 8ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + sdmmc_pwr: sdmmc-pwr { rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; }; };
- usb_host { + usb { host_vbus_drv: host-vbus-drv { rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; }; };
- usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + eth_phy { + eth_phy_pwr: eth-phy-pwr { + rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; };
-&pwm0 { +&usbphy { status = "okay"; };
-&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdio0 { - broken-cd; - bus-width = <4>; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; - vmmc-supply = <&vcc_18>; - status = "disabled"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { +&usb_host0_ehci { status = "okay"; };
@@ -428,10 +361,6 @@ status = "okay"; };
-&usb_otg { - status = "okay"; -}; - &vopb { status = "okay"; }; @@ -470,7 +399,3 @@ }; }; }; - -&wdt { - status = "okay"; -}; diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288-act8846_defconfig similarity index 95% rename from configs/evb-rk3288_defconfig rename to configs/evb-rk3288-act8846_defconfig index 8635fd9aaf..878367dea9 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288-act8846_defconfig @@ -12,7 +12,7 @@ CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_SILENT_CONSOLE=y -CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" +CONFIG_DEFAULT_FDT_FILE="rk3288-evb-act8846.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y @@ -33,7 +33,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb" +CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb-act8846" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/evb-rk3288-rk808_defconfig b/configs/evb-rk3288-rk808_defconfig new file mode 100644 index 0000000000..0cc1b2f601 --- /dev/null +++ b/configs/evb-rk3288-rk808_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_TARGET_EVB_RK3288=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_SILENT_CONSOLE=y +CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_PARTITION_UUIDS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb-rk808" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_RK8XX=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x320a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 +CONFIG_DISPLAY_ROCKCHIP_MIPI=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y
We want to use ATF loaded by the SPL, so need support for the itb FIT in SPL which therefore needs real mmc reading capabilities making it too big for the sram. So convert to use TPL for memory init beforehand similar to rk3288-vyasa.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/rk3288/Kconfig | 1 + board/rockchip/evb_rk3288/evb-rk3288.c | 4 ++++ configs/evb-rk3288-act8846_defconfig | 3 +-- configs/evb-rk3288-rk808_defconfig | 3 +-- 5 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ba11e8a497..bfcf12d1ab 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -188,6 +188,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM
config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" + default y if ROCKCHIP_RK3288 default y if ROCKCHIP_RK3368 select ROCKCHIP_BROM_HELPER depends on TPL diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 936faf75ca..800902a683 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -44,6 +44,7 @@ config TARGET_CHROMEBOOK_SPEEDY config TARGET_EVB_RK3288 bool "Evb-RK3288" select BOARD_LATE_INIT + select TPL help EVB-RK3288 is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c index d6992a26ca..ec1d03c86c 100644 --- a/board/rockchip/evb_rk3288/evb-rk3288.c +++ b/board/rockchip/evb_rk3288/evb-rk3288.c @@ -3,6 +3,8 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */
+#ifndef CONFIG_TPL_BUILD + #include <common.h> #include <spl.h>
@@ -12,3 +14,5 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[0] = BOOT_DEVICE_MMC2; spl_boot_list[1] = BOOT_DEVICE_MMC1; } + +#endif \ No newline at end of file diff --git a/configs/evb-rk3288-act8846_defconfig b/configs/evb-rk3288-act8846_defconfig index 878367dea9..9c7be78ad7 100644 --- a/configs/evb-rk3288-act8846_defconfig +++ b/configs/evb-rk3288-act8846_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_EVB_RK3288=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/configs/evb-rk3288-rk808_defconfig b/configs/evb-rk3288-rk808_defconfig index 0cc1b2f601..73d30c9958 100644 --- a/configs/evb-rk3288-rk808_defconfig +++ b/configs/evb-rk3288-rk808_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_EVB_RK3288=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000
Heiko,
On 04/05/2019 04:30 PM, Heiko Stuebner wrote:
We want to use ATF loaded by the SPL, so need support for the itb FIT in SPL which therefore needs real mmc reading capabilities making it too big for the sram. So convert to use TPL for memory init beforehand similar to rk3288-vyasa.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/rk3288/Kconfig | 1 + board/rockchip/evb_rk3288/evb-rk3288.c | 4 ++++ configs/evb-rk3288-act8846_defconfig | 3 +-- configs/evb-rk3288-rk808_defconfig | 3 +-- 5 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ba11e8a497..bfcf12d1ab 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -188,6 +188,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM
config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom"
- default y if ROCKCHIP_RK3288
This TPL_ROCKCHIP_BACK_TO_BROM should be default y to all SoCs, has apply in another patch from me, please rebase this patch.
Thanks, - Kever
default y if ROCKCHIP_RK3368 select ROCKCHIP_BROM_HELPER depends on TPL diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 936faf75ca..800902a683 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -44,6 +44,7 @@ config TARGET_CHROMEBOOK_SPEEDY config TARGET_EVB_RK3288 bool "Evb-RK3288" select BOARD_LATE_INIT
- select TPL help EVB-RK3288 is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c index d6992a26ca..ec1d03c86c 100644 --- a/board/rockchip/evb_rk3288/evb-rk3288.c +++ b/board/rockchip/evb_rk3288/evb-rk3288.c @@ -3,6 +3,8 @@
- (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
+#ifndef CONFIG_TPL_BUILD
#include <common.h> #include <spl.h>
@@ -12,3 +14,5 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[0] = BOOT_DEVICE_MMC2; spl_boot_list[1] = BOOT_DEVICE_MMC1; }
+#endif \ No newline at end of file diff --git a/configs/evb-rk3288-act8846_defconfig b/configs/evb-rk3288-act8846_defconfig index 878367dea9..9c7be78ad7 100644 --- a/configs/evb-rk3288-act8846_defconfig +++ b/configs/evb-rk3288-act8846_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_EVB_RK3288=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/configs/evb-rk3288-rk808_defconfig b/configs/evb-rk3288-rk808_defconfig index 0cc1b2f601..73d30c9958 100644 --- a/configs/evb-rk3288-rk808_defconfig +++ b/configs/evb-rk3288-rk808_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_EVB_RK3288=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000
Enable both rk3288-evb variants to load an ATF binary between spl and u-boot proper.
Doing the regular spl->u-boot load of course still stays possible with this change.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- board/rockchip/evb_rk3288/evb-rk3288.c | 12 +++++- board/rockchip/evb_rk3288/fit_spl_atf.its | 52 +++++++++++++++++++++++ configs/evb-rk3288-act8846_defconfig | 9 +++- configs/evb-rk3288-rk808_defconfig | 9 +++- 4 files changed, 77 insertions(+), 5 deletions(-) create mode 100644 board/rockchip/evb_rk3288/fit_spl_atf.its
diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c index ec1d03c86c..05aea66db6 100644 --- a/board/rockchip/evb_rk3288/evb-rk3288.c +++ b/board/rockchip/evb_rk3288/evb-rk3288.c @@ -15,4 +15,14 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[1] = BOOT_DEVICE_MMC1; }
-#endif \ No newline at end of file +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/board/rockchip/evb_rk3288/fit_spl_atf.its b/board/rockchip/evb_rk3288/fit_spl_atf.its new file mode 100644 index 0000000000..67aff095d6 --- /dev/null +++ b/board/rockchip/evb_rk3288/fit_spl_atf.its @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ +/* + * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * Minimal dts for a SPL FIT image payload. + */ + +/dts-v1/; + +/ { + description = "FIT image with U-Boot proper, ATF bl32, DTB"; + #address-cells = <1>; + + images { + uboot { + description = "U-Boot (64-bit)"; + data = /incbin/("../../../u-boot-nodtb.bin"); + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = <0x00200000>; + }; + atf { + description = "ARM Trusted Firmware"; + data = /incbin/("../../../bl32-rk3288.bin"); + type = "firmware"; + os = "arm-trusted-firmware"; + arch = "arm64"; + compression = "none"; + load = <0x00100000>; + entry = <0x00100000>; + }; + + fdt { + description = "RK3288-EVB flat device-tree"; + data = /incbin/("../../../u-boot.dtb"); + type = "flat_dt"; + compression = "none"; + }; + }; + + configurations { + default = "conf"; + conf { + description = "Rockchip RK3288-EVB"; + firmware = "atf"; + loadables = "uboot"; + fdt = "fdt"; + }; + }; +}; diff --git a/configs/evb-rk3288-act8846_defconfig b/configs/evb-rk3288-act8846_defconfig index 9c7be78ad7..0fcdaaa697 100644 --- a/configs/evb-rk3288-act8846_defconfig +++ b/configs/evb-rk3288-act8846_defconfig @@ -1,21 +1,26 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00100000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_EVB_RK3288=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/rockchip/evb_rk3288/fit_spl_atf.its" CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-evb-act8846.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/evb-rk3288-rk808_defconfig b/configs/evb-rk3288-rk808_defconfig index 73d30c9958..f6b9ce12a1 100644 --- a/configs/evb-rk3288-rk808_defconfig +++ b/configs/evb-rk3288-rk808_defconfig @@ -1,21 +1,26 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00100000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_EVB_RK3288=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/rockchip/evb_rk3288/fit_spl_atf.its" CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y
Hi Heiko,
On 04/05/2019 04:30 PM, Heiko Stuebner wrote:
Enable both rk3288-evb variants to load an ATF binary between spl and u-boot proper.
Does this the same as aarch64 boot/load flow? tpl->spl->atf->u-boot
Doing the regular spl->u-boot load of course still stays possible with this change.
Signed-off-by: Heiko Stuebner heiko@sntech.de
board/rockchip/evb_rk3288/evb-rk3288.c | 12 +++++- board/rockchip/evb_rk3288/fit_spl_atf.its | 52 +++++++++++++++++++++++
Is it possible to re-use arch/arm/mach-rockchip/make_fit_atf.py?
configs/evb-rk3288-act8846_defconfig | 9 +++- configs/evb-rk3288-rk808_defconfig | 9 +++- 4 files changed, 77 insertions(+), 5 deletions(-) create mode 100644 board/rockchip/evb_rk3288/fit_spl_atf.its
diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c index ec1d03c86c..05aea66db6 100644 --- a/board/rockchip/evb_rk3288/evb-rk3288.c +++ b/board/rockchip/evb_rk3288/evb-rk3288.c @@ -15,4 +15,14 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[1] = BOOT_DEVICE_MMC1; }
-#endif \ No newline at end of file +#endif
+#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
- return 0;
+} +#endif diff --git a/board/rockchip/evb_rk3288/fit_spl_atf.its b/board/rockchip/evb_rk3288/fit_spl_atf.its new file mode 100644 index 0000000000..67aff095d6 --- /dev/null +++ b/board/rockchip/evb_rk3288/fit_spl_atf.its @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ +/*
- Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
- Minimal dts for a SPL FIT image payload.
- */
+/dts-v1/;
+/ {
- description = "FIT image with U-Boot proper, ATF bl32, DTB";
Why you name the ATF bl32, isn't it bl31?
Thanks, - Kever
- #address-cells = <1>;
- images {
uboot {description = "U-Boot (64-bit)";data = /incbin/("../../../u-boot-nodtb.bin");type = "standalone";os = "U-Boot";arch = "arm64";compression = "none";load = <0x00200000>;};atf {description = "ARM Trusted Firmware";data = /incbin/("../../../bl32-rk3288.bin");type = "firmware";os = "arm-trusted-firmware";arch = "arm64";compression = "none";load = <0x00100000>;entry = <0x00100000>;};fdt {description = "RK3288-EVB flat device-tree";data = /incbin/("../../../u-boot.dtb");type = "flat_dt";compression = "none";};- };
- configurations {
default = "conf";conf {description = "Rockchip RK3288-EVB";firmware = "atf";loadables = "uboot";fdt = "fdt";};- };
+}; diff --git a/configs/evb-rk3288-act8846_defconfig b/configs/evb-rk3288-act8846_defconfig index 9c7be78ad7..0fcdaaa697 100644 --- a/configs/evb-rk3288-act8846_defconfig +++ b/configs/evb-rk3288-act8846_defconfig @@ -1,21 +1,26 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00100000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_EVB_RK3288=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/rockchip/evb_rk3288/fit_spl_atf.its" CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-evb-act8846.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/evb-rk3288-rk808_defconfig b/configs/evb-rk3288-rk808_defconfig index 73d30c9958..f6b9ce12a1 100644 --- a/configs/evb-rk3288-rk808_defconfig +++ b/configs/evb-rk3288-rk808_defconfig @@ -1,21 +1,26 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00100000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_EVB_RK3288=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/rockchip/evb_rk3288/fit_spl_atf.its" CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y
participants (4)
-
Heiko Stuebner -
Jagan Teki -
Kever Yang -
Matthias Brugger