[U-Boot] [PATCH v9 0/3] Adds support for Exynos5422 odroid xu3 board
This is v9 of the patchset adding support Odroud XU3 board.
link to the previous version: v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html v3: https://www.mail-archive.com/u-boot%40lists.denx.de/msg152677.html v4: https://patchwork.ozlabs.org/patch/407411/ v5: https://patchwork.ozlabs.org/patch/407941/ v6: https://patchwork.ozlabs.org/patch/408647/ v7: https://patchwork.ozlabs.org/patch/410204/ v8: https://patchwork.ozlabs.org/patch/410709/
The patchset by Akshay Saraswat is already merged into u-boot-samsung. Please ignore the instruction about the additional patchset in v8.
How to test this patch: 1. git clone http://git.denx.de/u-boot-samsung.git 2. Apply this patchset 3. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- odroid-xu3_config 4. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j8 5. Now you can use u-boot-dtb.bin for your downloading
WANRNING: The u-boot-dtb.bin must not be bigger than 335872 bytes. Depending on your compiler, it can be. Try another one if you get a problem. I use 'gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4)' on Ubuntu 64-bit machine.
Note: If you use micro SD card for your test you have to apply the below patch additionally. This patch is needed, because micro sd card is recognized as MMC1 instead of MMC0. Additional work is needed to make it work regardless of device id.
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ba591e7..437eaae 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -109,7 +109,7 @@
#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SECURE_BL1_ONLY
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index cda4f26..b46ccad 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -110,15 +110,15 @@ "run kernel_args;" \ "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ "autoboot=" \ - "if test -e mmc 0 Image.itb; then; " \ + "if test -e mmc 1 Image.itb; then; " \ "run boot_fit;" \ - "elif test -e mmc 0 zImage; then; " \ + "elif test -e mmc 1 zImage; then; " \ "run boot_zimg;" \ - "elif test -e mmc 0 uImage; then; " \ + "elif test -e mmc 1 uImage; then; " \ "run boot_uimg;" \ "fi;\0" \ "console=" CONFIG_DEFAULT_CONSOLE \ - "mmcbootdev=0\0" \ + "mmcbootdev=1\0" \ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \
Changes for v2: - Add a patch to add new common setup header file for Odroid X2/U3 and Odroid XU3
Changes for v3: - Remove the patch which adds new common setup header file from v2 - Remove the wrong patch to fix GPIO information of Exynos 5800 - Remove unnecessary node from DT file - Remove unnecessary features from config file - Fix some trivial typos in comments
Changes for v4: - Add MMC FIFO buffer's configuration to DT file - Make CONFIG_OF_CONTROL be set by the target information - Add basic document to doc/README.odroid-xu3 - Add CONFIG_CMD_EXT4 to config file - Add environment size and offset to config file - Add extra default environment to make bootable without modification - Remove unnecessary features from config file
Changes for v5: - Add the specific build instruction - Update the information of patchset by Akshay Saraswat - Convert /include/ to #include in DT file
Changes for v6: - Separate out the documentation to new commit - Remove unnecessary header file inclusuib from the board-specific setup file - Make the function board_clock_init be declared, only when CONFIG_BOARD_EARLY_INIT_F is defined
Changes for v7: - Fix several errata in the documentation - Remove OF_CONTROL dependency from !SPL_BUILD
Changes for v8: - Remove unnecessary properties in DT mmc node
Changes for v9: - Remove the first patch which change GPIO entries order. It became useless, after DT support is added - Remove useless variables in the default environment - Add the new contents to the documentation of Odroid X2/U2, instead of making new document for Odorid XU3 - Remove the detailed information in the header file, and leave the reference to the documentation
Hyungwon Hwang (2): Odroid-XU3: Add support for Odroid-XU3 Odroid-XU3: Add documentation for Odroid-XU3
arch/arm/cpu/armv7/exynos/Kconfig | 5 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 57 +++++++++++++++ board/samsung/odroid-xu3/Kconfig | 12 +++ board/samsung/odroid-xu3/MAINTAINERS | 6 ++ board/samsung/odroid-xu3/Makefile | 7 ++ board/samsung/odroid-xu3/odroid-xu3.c | 122 +++++++++++++++++++++++++++++++ board/samsung/odroid-xu3/setup.h | 95 ++++++++++++++++++++++++ configs/odroid-xu3_defconfig | 4 + doc/README.odroid | 46 ++++++++---- include/configs/odroid.h | 5 -- include/configs/odroid_xu3.h | 133 ++++++++++++++++++++++++++++++++++ 12 files changed, 473 insertions(+), 22 deletions(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 include/configs/odroid_xu3.h
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Tested-by: Lukasz Majewski l.majewski@samsung.com Acked-by: Lukasz Majewski l.majewski@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com --- Changes for v3: - Remove unnecessary node from DT file - Remove unnecessary features from config file - Remove unnecessary macros from board-specific header file - Fix some trivial typos in comments
Changes for v4: - Add MMC FIFO buffer's configuration to DT file - Make CONFIG_OF_CONTROL be set by the target information - Add basic document to doc/README.odroid-xu3 - Add CONFIG_CMD_EXT4 to config file - Add environment size and offset to config file - Add extra default environment to make bootable without modification - Remove unnecessary features from config file
Changes for v5: - Convert /include/ to #include in DT file
Changes for v6: - Separate out the documentation to new commit - Remove unnecessary header file inclusions from the board-specific setup file - Make the function board_clock_init be declared, only when CONFIG_BOARD_EARLY_INIT_F is defined
Changes for v7: - Remove OF_CONTROL dependency from !SPL_BUILD
Changes for v8: - Remove unnecessary properties in DT mmc node
Changes for v9: - Remove useless variables in the default environment - Replace the detailed information to the reference to the documentation
arch/arm/cpu/armv7/exynos/Kconfig | 5 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 57 +++++++++++++++ board/samsung/odroid-xu3/Kconfig | 12 +++ board/samsung/odroid-xu3/MAINTAINERS | 6 ++ board/samsung/odroid-xu3/Makefile | 7 ++ board/samsung/odroid-xu3/odroid-xu3.c | 122 +++++++++++++++++++++++++++++++ board/samsung/odroid-xu3/setup.h | 95 ++++++++++++++++++++++++ configs/odroid-xu3_defconfig | 4 + include/configs/odroid.h | 5 -- include/configs/odroid_xu3.h | 133 ++++++++++++++++++++++++++++++++++ 11 files changed, 443 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 include/configs/odroid_xu3.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 13dbd95..16c9a0e 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -24,6 +24,10 @@ config TARGET_TRATS2 config TARGET_ODROID bool "Exynos4412 Odroid board"
+config TARGET_ODROID_XU3 + bool "Exynos5422 Odroid board" + select OF_CONTROL + config TARGET_ARNDALE bool "Exynos5250 Arndale board" select SUPPORT_SPL @@ -65,6 +69,7 @@ source "board/samsung/universal_c210/Kconfig" source "board/samsung/origen/Kconfig" source "board/samsung/trats2/Kconfig" source "board/samsung/odroid/Kconfig" +source "board/samsung/odroid-xu3/Kconfig" source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e5846ea..a811b1b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -13,7 +13,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ exynos5420-peach-pit.dtb \ - exynos5800-peach-pi.dtb + exynos5800-peach-pi.dtb \ + exynos5422-odroidxu3.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644 index 0000000..533d88e --- /dev/null +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -0,0 +1,57 @@ +/* + * Odroid XU3 device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos54xx.dtsi" + +/ { + model = "Odroid XU3 based on EXYNOS5422"; + compatible = "samsung,odroidxu3", "samsung,exynos5"; + + aliases { + serial0 = "/serial@12C00000"; + console = "/serial@12C20000"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000 + 0x60000000 0x10000000 + 0x70000000 0x10000000 + 0x80000000 0x10000000 + 0x90000000 0x10000000 + 0xa0000000 0x10000000 + 0xb0000000 0xea00000>; + }; + + serial@12C20000 { + status="okay"; + }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + fifoth_val = <0x200f0020>; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + fifoth_val = <0x200f0020>; + }; + + mmc@12230000 { + status = "disabled"; + }; +}; diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig new file mode 100644 index 0000000..6159692 --- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3 + +config SYS_BOARD + default "odroid-xu3" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "odroid_xu3" + +endif diff --git a/board/samsung/odroid-xu3/MAINTAINERS b/board/samsung/odroid-xu3/MAINTAINERS new file mode 100644 index 0000000..50cf928 --- /dev/null +++ b/board/samsung/odroid-xu3/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID-XU3 BOARD +M: Hyungwon Hwang human.hwang@samsung.com +S: Maintained +F: board/samsung/odroid-xu3/ +F: include/configs/odroid_xu3.h +F: configs/odroid-xu3_defconfig diff --git a/board/samsung/odroid-xu3/Makefile b/board/samsung/odroid-xu3/Makefile new file mode 100644 index 0000000..85ae5c5 --- /dev/null +++ b/board/samsung/odroid-xu3/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := odroid-xu3.o diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..8c54842 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Hyungwon Hwang human.hwang@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include "setup.h" + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int get_board_rev(void) +{ + return 0; +} + +int exynos_init(void) +{ + return 0; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +static int board_clock_init(void) +{ + unsigned int set, clr, clr_src_cpu, clr_pll_con0; + struct exynos5420_clock *clk = (struct exynos5420_clock *) + samsung_get_base_clock(); + /* + * CMU_CPU clocks src to MPLL + * Bit values: 0 ; 1 + * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL + * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL + * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C + * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL + */ + + /* Set CMU_CPU clocks src to OSCCLK */ + clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1); + set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1); + + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); + + while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu))) + continue; + + /* Set APLL to 1200MHz */ + clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | + PLL_ENABLE(1); + set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1); + + clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); + + while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) + continue; + + /* Set CMU_CPU clocks src to APLL */ + set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0); + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); + + while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu))) + continue; + + clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) | + PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7); + set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) | + PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0); + + clrsetbits_le32(&clk->div_cpu0, clr, set); + + while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) + continue; + + /* Set MPLL to 800MHz */ + set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1); + + clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); + + while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) + continue; + + /* Set CLKMUX_UART src to MPLL */ + clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | UART3_SEL(7); + set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | UART3_SEL(3); + + clrsetbits_le32(&clk->src_peric0, clr, set); + + /* Set SCLK_UART to 400 MHz (MPLL / 2) */ + clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | + UART3_RATIO(15); + set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) | + UART3_RATIO(1); + + clrsetbits_le32(&clk->div_peric0, clr, set); + + while (readl(&clk->div_stat_peric0) & DIV_STAT_PERIC0_CHANGING) + continue; + + /* Set CLKMUX_MMC src to MPLL */ + clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7); + set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3); + + clrsetbits_le32(&clk->src_fsys, clr, set); + + clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | MMC2_RATIO(0x3ff); + set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0); + + clrsetbits_le32(&clk->div_fsys1, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) + continue; + + return 0; +} + +int exynos_early_init_f(void) +{ + return board_clock_init(); +} +#endif diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h new file mode 100644 index 0000000..143c189 --- /dev/null +++ b/board/samsung/odroid-xu3/setup.h @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2014 Samsung Electronics + * Hyungwon Hwang human.hwang@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ODROID_XU3_SETUP__ +#define __ODROID_XU3_SETUP__ + +#define SDIV(x) ((x) & 0x7) +#define PDIV(x) (((x) & 0x3f) << 8) +#define MDIV(x) (((x) & 0x3ff) << 16) +#define FSEL(x) (((x) & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) (((x) & 0x1) << 31) + +/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) ((x) & 0x1) +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16) + +/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) ((x) & 0x7) +#define CORE_SEL(x) (((x) & 0x7) << 16) +#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) || \ + (x) & APLL_SEL(1) || \ + (x) & CORE_SEL(0) || \ + (x) & CORE_SEL(1)) + +/* CLK_DIV_CPU0 */ +#define ARM_RATIO(x) ((x) & 0x7) +#define CPUD_RATIO(x) (((x) & 0x7) << 4) +#define ATB_RATIO(x) (((x) & 0x7) << 16) +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) +#define APLL_RATIO(x) (((x) & 0x7) << 24) +#define ARM2_RATIO(x) (((x) & 0x7) << 28) + +/* CLK_DIV_STAT_CPU0 */ +#define DIV_CPUD(x) (((x) & 0x1) << 4) +#define DIV_ATB(x) (((x) & 0x1) << 16) +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) +#define DIV_APLL(x) (((x) & 0x1) << 24) +#define DIV_ARM2(x) (((x) & 0x1) << 28) + +#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \ + DIV_ATB(DIV_STAT_CHANGING) | \ + DIV_PCLK_DBG(DIV_STAT_CHANGING) | \ + DIV_APLL(DIV_STAT_CHANGING) | \ + DIV_ARM2(DIV_STAT_CHANGING)) + +/* Set CLK_SRC_PERIC0 */ +#define UART0_SEL(x) (((x) & 0xf) << 4) +#define UART1_SEL(x) (((x) & 0xf) << 8) +#define UART2_SEL(x) (((x) & 0xf) << 12) +#define UART3_SEL(x) (((x) & 0xf) << 16) + +/* Set CLK_DIV_PERIC0 */ +#define UART0_RATIO(x) (((x) & 0xf) << 8) +#define UART1_RATIO(x) (((x) & 0xf) << 12) +#define UART2_RATIO(x) (((x) & 0xf) << 16) +#define UART3_RATIO(x) (((x) & 0xf) << 20) + +/* Set CLK_DIV_STAT_PERIC0 */ +#define DIV_UART0(x) ((x) & 0x1) +#define DIV_UART1(x) (((x) & 0x1) << 4) +#define DIV_UART2(x) (((x) & 0x1) << 8) +#define DIV_UART3(x) (((x) & 0x1) << 12) +#define DIV_UART4(x) (((x) & 0x1) << 16) + +#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \ + DIV_UART3(DIV_STAT_CHANGING) | \ + DIV_UART2(DIV_STAT_CHANGING) | \ + DIV_UART1(DIV_STAT_CHANGING) | \ + DIV_UART0(DIV_STAT_CHANGING)) + +/* CLK_SRC_FSYS */ +#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8) +#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12) +#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16) + +/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0x3ff) +#define MMC1_RATIO(x) (((x) & 0x3ff) << 10) +#define MMC2_RATIO(x) (((x) & 0x3ff) << 20) + +#define DIV_MMC0(x) (((x) & 1) << 20) +#define DIV_MMC1(x) (((x) & 1) << 24) +#define DIV_MMC2(x) (((x) & 1) << 28) + +#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \ + DIV_MMC1(DIV_STAT_CHANGING) | \ + DIV_MMC2(DIV_STAT_CHANGING)) + +#endif diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig new file mode 100644 index 0000000..74aa0cf --- /dev/null +++ b/configs/odroid-xu3_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID_XU3=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 807e96b..660b6ae 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -166,11 +166,6 @@ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \ - "bootdelay=0\0" \ - "dfu_alt_system="CONFIG_DFU_ALT \ - "dfu_alt_info=Please reset the board\0" \ - "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \ - "consoleoff=set console console=ram; save; reset\0" \ "initrdname=uInitrd\0" \ "initrdaddr=42000000\0" \ "fdtaddr=40800000\0" diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h new file mode 100644 index 0000000..1d53653 --- /dev/null +++ b/include/configs/odroid_xu3.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Hyungwon Hwang human.hwang@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H + +#include "exynos5-common.h" + +#define CONFIG_SYS_PROMPT "ODROID-XU3 # " +#define CONFIG_IDENT_STRING " for ODROID-XU3" + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 + +/* select serial console configuration */ +#define CONFIG_SERIAL2 /* use SERIAL 2 */ + +#define TZPC_BASE_OFFSET 0x10000 + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT + +/* + * FIXME: The number of bank is actually 8. But there is no way to reserver the + * last 16 Mib in the last bank now. So I just excluded the last bank + * temporally. + */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#define CONFIG_ENV_IS_IN_MMC + +#undef CONFIG_ENV_SIZE +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +#define CONFIG_BOOTCOMMAND "run autoboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" + +/* + * For details, refer the documentation: doc/README.odroid +*/ +#ifdef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_EXTRA_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ + "${kernelname}\0" \ + "loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ + "${initrdname}\0" \ + "loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \ + "${fdtfile}\0" \ + "check_ramdisk=" \ + "if run loadinitrd; then " \ + "setenv initrd_addr ${initrdaddr};" \ + "else " \ + "setenv initrd_addr -;" \ + "fi;\0" \ + "check_dtb=" \ + "if run loaddtb; then " \ + "setenv fdt_addr ${fdtaddr};" \ + "else " \ + "setenv fdt_addr;" \ + "fi;\0" \ + "kernel_args=" \ + "setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \ + " rootwait ${console} ${opts}\0" \ + "boot_fit=" \ + "setenv kerneladdr 0x42000000;" \ + "setenv kernelname Image.itb;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr}#${boardname}\0" \ + "boot_uimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname uImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "boot_zimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname zImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "autoboot=" \ + "if test -e mmc 0 Image.itb; then; " \ + "run boot_fit;" \ + "elif test -e mmc 0 zImage; then; " \ + "run boot_zimg;" \ + "elif test -e mmc 0 uImage; then; " \ + "run boot_uimg;" \ + "fi;\0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ + "mmcbootdev=0\0" \ + "mmcbootpart=1\0" \ + "mmcrootdev=0\0" \ + "mmcrootpart=2\0" \ + "bootdelay=0\0" \ + "dfu_alt_info=Please reset the board\0" \ + "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ + "consoleoff=set console console=ram; save; reset\0" \ + "initrdname=uInitrd\0" \ + "initrdaddr=42000000\0" \ + "fdtaddr=40800000\0" + +/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ +#undef CONFIG_EXYNOS_TMU +#undef CONFIG_TMU_CMD_DTT + +#ifdef CONFIG_CMD_NET +#undef CONFIG_CMD_NET +#undef CONFIG_SMC911X +#undef CONFIG_CMD_PXE +#undef CONFIG_MENU +#endif + +#endif /* __CONFIG_H */
On 11/27/2014 10:21 PM, Hyungwon Hwang wrote:
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Tested-by: Lukasz Majewski l.majewski@samsung.com Acked-by: Lukasz Majewski l.majewski@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com
Changes for v3:
- Remove unnecessary node from DT file
- Remove unnecessary features from config file
- Remove unnecessary macros from board-specific header file
- Fix some trivial typos in comments
Changes for v4:
- Add MMC FIFO buffer's configuration to DT file
- Make CONFIG_OF_CONTROL be set by the target information
- Add basic document to doc/README.odroid-xu3
- Add CONFIG_CMD_EXT4 to config file
- Add environment size and offset to config file
- Add extra default environment to make bootable without modification
- Remove unnecessary features from config file
Changes for v5:
- Convert /include/ to #include in DT file
Changes for v6:
- Separate out the documentation to new commit
- Remove unnecessary header file inclusions from the board-specific setup file
- Make the function board_clock_init be declared, only when CONFIG_BOARD_EARLY_INIT_F is defined
Changes for v7:
- Remove OF_CONTROL dependency from !SPL_BUILD
Changes for v8:
- Remove unnecessary properties in DT mmc node
Changes for v9:
- Remove useless variables in the default environment
- Replace the detailed information to the reference to the documentation
arch/arm/cpu/armv7/exynos/Kconfig | 5 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 57 +++++++++++++++ board/samsung/odroid-xu3/Kconfig | 12 +++ board/samsung/odroid-xu3/MAINTAINERS | 6 ++ board/samsung/odroid-xu3/Makefile | 7 ++ board/samsung/odroid-xu3/odroid-xu3.c | 122 +++++++++++++++++++++++++++++++ board/samsung/odroid-xu3/setup.h | 95 ++++++++++++++++++++++++ configs/odroid-xu3_defconfig | 4 + include/configs/odroid.h | 5 -- include/configs/odroid_xu3.h | 133 ++++++++++++++++++++++++++++++++++ 11 files changed, 443 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 include/configs/odroid_xu3.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 13dbd95..16c9a0e 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -24,6 +24,10 @@ config TARGET_TRATS2 config TARGET_ODROID bool "Exynos4412 Odroid board"
+config TARGET_ODROID_XU3
- bool "Exynos5422 Odroid board"
- select OF_CONTROL
config TARGET_ARNDALE bool "Exynos5250 Arndale board" select SUPPORT_SPL @@ -65,6 +69,7 @@ source "board/samsung/universal_c210/Kconfig" source "board/samsung/origen/Kconfig" source "board/samsung/trats2/Kconfig" source "board/samsung/odroid/Kconfig" +source "board/samsung/odroid-xu3/Kconfig" source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e5846ea..a811b1b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -13,7 +13,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ exynos5420-peach-pit.dtb \
- exynos5800-peach-pi.dtb
- exynos5800-peach-pi.dtb \
- exynos5422-odroidxu3.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644 index 0000000..533d88e --- /dev/null +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -0,0 +1,57 @@ +/*
- Odroid XU3 device tree source
- Copyright (c) 2014 Samsung Electronics Co., Ltd.
http://www.samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+/dts-v1/; +#include "exynos54xx.dtsi"
+/ {
- model = "Odroid XU3 based on EXYNOS5422";
- compatible = "samsung,odroidxu3", "samsung,exynos5";
- aliases {
serial0 = "/serial@12C00000";console = "/serial@12C20000";- };
- memory {
device_type = "memory";reg = <0x40000000 0x100000000x50000000 0x100000000x60000000 0x100000000x70000000 0x100000000x80000000 0x100000000x90000000 0x100000000xa0000000 0x100000000xb0000000 0xea00000>;- };
- serial@12C20000 {
status="okay";- };
- mmc@12200000 {
samsung,bus-width = <8>;samsung,timing = <1 3 3>;fifoth_val = <0x200f0020>;
If you resend the patch, i want to change the fifoth_val from 0x200f0020 to 0x201f0020. (Well, i'm not sure what's right. but when i have checked, the fifoth_depth is 0x40. Then Rx_MASK = FIFOTH_DEPTH/2 - 1, TX_MASK = FIFOTH_DEPTH/2.
- };
- mmc@12210000 {
status = "disabled";- };
- mmc@12220000 {
samsung,bus-width = <4>;samsung,timing = <1 2 3>;fifoth_val = <0x200f0020>;
Ditto.
- };
- mmc@12230000 {
status = "disabled";- };
+}; diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig new file mode 100644 index 0000000..6159692 --- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3
+config SYS_BOARD
- default "odroid-xu3"
+config SYS_VENDOR
- default "samsung"
+config SYS_CONFIG_NAME
- default "odroid_xu3"
+endif diff --git a/board/samsung/odroid-xu3/MAINTAINERS b/board/samsung/odroid-xu3/MAINTAINERS new file mode 100644 index 0000000..50cf928 --- /dev/null +++ b/board/samsung/odroid-xu3/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID-XU3 BOARD +M: Hyungwon Hwang human.hwang@samsung.com +S: Maintained +F: board/samsung/odroid-xu3/ +F: include/configs/odroid_xu3.h +F: configs/odroid-xu3_defconfig diff --git a/board/samsung/odroid-xu3/Makefile b/board/samsung/odroid-xu3/Makefile new file mode 100644 index 0000000..85ae5c5 --- /dev/null +++ b/board/samsung/odroid-xu3/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := odroid-xu3.o diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..8c54842 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,122 @@ +/*
- Copyright (C) 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include "setup.h"
+DECLARE_GLOBAL_DATA_PTR;
+unsigned int get_board_rev(void) +{
- return 0;
+}
+int exynos_init(void) +{
- return 0;
+}
+#ifdef CONFIG_BOARD_EARLY_INIT_F +static int board_clock_init(void) +{
- unsigned int set, clr, clr_src_cpu, clr_pll_con0;
- struct exynos5420_clock *clk = (struct exynos5420_clock *)
samsung_get_base_clock();- /*
* CMU_CPU clocks src to MPLL* Bit values: 0 ; 1* MUX_APLL_SEL: FIN_PLL ; FOUT_APLL* MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL- */
- /* Set CMU_CPU clocks src to OSCCLK */
- clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);
- set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- /* Set APLL to 1200MHz */
- clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
PLL_ENABLE(1);- set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
- while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CMU_CPU clocks src to APLL */
- set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |
PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);- set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |
PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);- clrsetbits_le32(&clk->div_cpu0, clr, set);
- while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
continue;- /* Set MPLL to 800MHz */
- set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
- while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CLKMUX_UART src to MPLL */
- clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | UART3_SEL(7);
- set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | UART3_SEL(3);
- clrsetbits_le32(&clk->src_peric0, clr, set);
- /* Set SCLK_UART to 400 MHz (MPLL / 2) */
- clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
UART3_RATIO(15);- set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |
UART3_RATIO(1);- clrsetbits_le32(&clk->div_peric0, clr, set);
- while (readl(&clk->div_stat_peric0) & DIV_STAT_PERIC0_CHANGING)
continue;- /* Set CLKMUX_MMC src to MPLL */
- clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);
- set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);
- clrsetbits_le32(&clk->src_fsys, clr, set);
- clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | MMC2_RATIO(0x3ff);
- set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);
- clrsetbits_le32(&clk->div_fsys1, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
continue;- return 0;
+}
+int exynos_early_init_f(void) +{
- return board_clock_init();
+} +#endif diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h new file mode 100644 index 0000000..143c189 --- /dev/null +++ b/board/samsung/odroid-xu3/setup.h @@ -0,0 +1,95 @@ +/*
- (C) Copyright 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __ODROID_XU3_SETUP__ +#define __ODROID_XU3_SETUP__
+#define SDIV(x) ((x) & 0x7) +#define PDIV(x) (((x) & 0x3f) << 8) +#define MDIV(x) (((x) & 0x3ff) << 16) +#define FSEL(x) (((x) & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) (((x) & 0x1) << 31)
+/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) ((x) & 0x1) +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
+/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) ((x) & 0x7) +#define CORE_SEL(x) (((x) & 0x7) << 16) +#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) || \
(x) & APLL_SEL(1) || \(x) & CORE_SEL(0) || \(x) & CORE_SEL(1))+/* CLK_DIV_CPU0 */ +#define ARM_RATIO(x) ((x) & 0x7) +#define CPUD_RATIO(x) (((x) & 0x7) << 4) +#define ATB_RATIO(x) (((x) & 0x7) << 16) +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) +#define APLL_RATIO(x) (((x) & 0x7) << 24) +#define ARM2_RATIO(x) (((x) & 0x7) << 28)
+/* CLK_DIV_STAT_CPU0 */ +#define DIV_CPUD(x) (((x) & 0x1) << 4) +#define DIV_ATB(x) (((x) & 0x1) << 16) +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) +#define DIV_APLL(x) (((x) & 0x1) << 24) +#define DIV_ARM2(x) (((x) & 0x1) << 28)
+#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \
DIV_ATB(DIV_STAT_CHANGING) | \DIV_PCLK_DBG(DIV_STAT_CHANGING) | \DIV_APLL(DIV_STAT_CHANGING) | \DIV_ARM2(DIV_STAT_CHANGING))+/* Set CLK_SRC_PERIC0 */ +#define UART0_SEL(x) (((x) & 0xf) << 4) +#define UART1_SEL(x) (((x) & 0xf) << 8) +#define UART2_SEL(x) (((x) & 0xf) << 12) +#define UART3_SEL(x) (((x) & 0xf) << 16)
+/* Set CLK_DIV_PERIC0 */ +#define UART0_RATIO(x) (((x) & 0xf) << 8) +#define UART1_RATIO(x) (((x) & 0xf) << 12) +#define UART2_RATIO(x) (((x) & 0xf) << 16) +#define UART3_RATIO(x) (((x) & 0xf) << 20)
+/* Set CLK_DIV_STAT_PERIC0 */ +#define DIV_UART0(x) ((x) & 0x1) +#define DIV_UART1(x) (((x) & 0x1) << 4) +#define DIV_UART2(x) (((x) & 0x1) << 8) +#define DIV_UART3(x) (((x) & 0x1) << 12) +#define DIV_UART4(x) (((x) & 0x1) << 16)
+#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
DIV_UART3(DIV_STAT_CHANGING) | \DIV_UART2(DIV_STAT_CHANGING) | \DIV_UART1(DIV_STAT_CHANGING) | \DIV_UART0(DIV_STAT_CHANGING))+/* CLK_SRC_FSYS */ +#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8) +#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12) +#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16)
+/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0x3ff) +#define MMC1_RATIO(x) (((x) & 0x3ff) << 10) +#define MMC2_RATIO(x) (((x) & 0x3ff) << 20)
+#define DIV_MMC0(x) (((x) & 1) << 20) +#define DIV_MMC1(x) (((x) & 1) << 24) +#define DIV_MMC2(x) (((x) & 1) << 28)
+#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
DIV_MMC1(DIV_STAT_CHANGING) | \DIV_MMC2(DIV_STAT_CHANGING))+#endif diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig new file mode 100644 index 0000000..74aa0cf --- /dev/null +++ b/configs/odroid-xu3_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID_XU3=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 807e96b..660b6ae 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -166,11 +166,6 @@ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \
- "bootdelay=0\0" \
- "dfu_alt_system="CONFIG_DFU_ALT \
- "dfu_alt_info=Please reset the board\0" \
- "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \
- "consoleoff=set console console=ram; save; reset\0" \ "initrdname=uInitrd\0" \ "initrdaddr=42000000\0" \ "fdtaddr=40800000\0"
This is not XU3, separate the patch.
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h new file mode 100644 index 0000000..1d53653 --- /dev/null +++ b/include/configs/odroid_xu3.h @@ -0,0 +1,133 @@ +/*
- Copyright (C) 2013 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H
+#include "exynos5-common.h"
+#define CONFIG_SYS_PROMPT "ODROID-XU3 # " +#define CONFIG_IDENT_STRING " for ODROID-XU3"
+#define CONFIG_BOARD_COMMON
+#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000
+/* select serial console configuration */ +#define CONFIG_SERIAL2 /* use SERIAL 2 */
+#define TZPC_BASE_OFFSET 0x10000
+#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT
+/*
- FIXME: The number of bank is actually 8. But there is no way to reserver the
- last 16 Mib in the last bank now. So I just excluded the last bank
- temporally.
- */
+#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_SIZE +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+#define CONFIG_BOOTCOMMAND "run autoboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
+/*
- For details, refer the documentation: doc/README.odroid
+*/ +#ifdef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_EXTRA_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \
"${kernelname}\0" \- "loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \
"${initrdname}\0" \- "loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \
"${fdtfile}\0" \- "check_ramdisk=" \
"if run loadinitrd; then " \"setenv initrd_addr ${initrdaddr};" \"else " \"setenv initrd_addr -;" \"fi;\0" \- "check_dtb=" \
"if run loaddtb; then " \"setenv fdt_addr ${fdtaddr};" \"else " \"setenv fdt_addr;" \"fi;\0" \- "kernel_args=" \
"setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \" rootwait ${console} ${opts}\0" \- "boot_fit=" \
"setenv kerneladdr 0x42000000;" \"setenv kernelname Image.itb;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kerneladdr}#${boardname}\0" \- "boot_uimg=" \
"setenv kerneladdr 0x40007FC0;" \"setenv kernelname uImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \- "boot_zimg=" \
"setenv kerneladdr 0x40007FC0;" \"setenv kernelname zImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \- "autoboot=" \
"if test -e mmc 0 Image.itb; then; " \"run boot_fit;" \"elif test -e mmc 0 zImage; then; " \"run boot_zimg;" \"elif test -e mmc 0 uImage; then; " \"run boot_uimg;" \"fi;\0" \- "console=" CONFIG_DEFAULT_CONSOLE \
- "mmcbootdev=0\0" \
- "mmcbootpart=1\0" \
- "mmcrootdev=0\0" \
- "mmcrootpart=2\0" \
- "bootdelay=0\0" \
- "dfu_alt_info=Please reset the board\0" \
- "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
- "consoleoff=set console console=ram; save; reset\0" \
I think you want to remove these.
Best Regards, Jaehoon Chung
- "initrdname=uInitrd\0" \
- "initrdaddr=42000000\0" \
- "fdtaddr=40800000\0"
+/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ +#undef CONFIG_EXYNOS_TMU +#undef CONFIG_TMU_CMD_DTT
+#ifdef CONFIG_CMD_NET +#undef CONFIG_CMD_NET +#undef CONFIG_SMC911X +#undef CONFIG_CMD_PXE +#undef CONFIG_MENU +#endif
+#endif /* __CONFIG_H */
On Fri, 28 Nov 2014 00:16:15 +0900 Jaehoon Chung jh80.chung@samsung.com wrote:
On 11/27/2014 10:21 PM, Hyungwon Hwang wrote:
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Tested-by: Lukasz Majewski l.majewski@samsung.com Acked-by: Lukasz Majewski l.majewski@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com
Changes for v3:
- Remove unnecessary node from DT file
- Remove unnecessary features from config file
- Remove unnecessary macros from board-specific header file
- Fix some trivial typos in comments
Changes for v4:
- Add MMC FIFO buffer's configuration to DT file
- Make CONFIG_OF_CONTROL be set by the target information
- Add basic document to doc/README.odroid-xu3
- Add CONFIG_CMD_EXT4 to config file
- Add environment size and offset to config file
- Add extra default environment to make bootable without
modification
- Remove unnecessary features from config file
Changes for v5:
- Convert /include/ to #include in DT file
Changes for v6:
- Separate out the documentation to new commit
- Remove unnecessary header file inclusions from the board-specific
setup file
- Make the function board_clock_init be declared, only when CONFIG_BOARD_EARLY_INIT_F is defined
Changes for v7:
- Remove OF_CONTROL dependency from !SPL_BUILD
Changes for v8:
- Remove unnecessary properties in DT mmc node
Changes for v9:
- Remove useless variables in the default environment
- Replace the detailed information to the reference to the
documentation
arch/arm/cpu/armv7/exynos/Kconfig | 5 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 57 +++++++++++++++ board/samsung/odroid-xu3/Kconfig | 12 +++ board/samsung/odroid-xu3/MAINTAINERS | 6 ++ board/samsung/odroid-xu3/Makefile | 7 ++ board/samsung/odroid-xu3/odroid-xu3.c | 122 +++++++++++++++++++++++++++++++ board/samsung/odroid-xu3/setup.h | 95 ++++++++++++++++++++++++ configs/odroid-xu3_defconfig | 4 + include/configs/odroid.h | 5 -- include/configs/odroid_xu3.h | 133 ++++++++++++++++++++++++++++++++++ 11 files changed, 443 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 include/configs/odroid_xu3.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 13dbd95..16c9a0e 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -24,6 +24,10 @@ config TARGET_TRATS2 config TARGET_ODROID bool "Exynos4412 Odroid board"
+config TARGET_ODROID_XU3
- bool "Exynos5422 Odroid board"
- select OF_CONTROL
config TARGET_ARNDALE bool "Exynos5250 Arndale board" select SUPPORT_SPL @@ -65,6 +69,7 @@ source "board/samsung/universal_c210/Kconfig" source "board/samsung/origen/Kconfig" source "board/samsung/trats2/Kconfig" source "board/samsung/odroid/Kconfig" +source "board/samsung/odroid-xu3/Kconfig" source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e5846ea..a811b1b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -13,7 +13,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ exynos5420-peach-pit.dtb \
- exynos5800-peach-pi.dtb
- exynos5800-peach-pi.dtb \
- exynos5422-odroidxu3.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644 index 0000000..533d88e --- /dev/null +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -0,0 +1,57 @@ +/*
- Odroid XU3 device tree source
- Copyright (c) 2014 Samsung Electronics Co., Ltd.
http://www.samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+/dts-v1/; +#include "exynos54xx.dtsi"
+/ {
- model = "Odroid XU3 based on EXYNOS5422";
- compatible = "samsung,odroidxu3", "samsung,exynos5";
- aliases {
serial0 = "/serial@12C00000";console = "/serial@12C20000";- };
- memory {
device_type = "memory";reg = <0x40000000 0x100000000x50000000 0x100000000x60000000 0x100000000x70000000 0x100000000x80000000 0x100000000x90000000 0x100000000xa0000000 0x100000000xb0000000 0xea00000>;- };
- serial@12C20000 {
status="okay";- };
- mmc@12200000 {
samsung,bus-width = <8>;samsung,timing = <1 3 3>;fifoth_val = <0x200f0020>;If you resend the patch, i want to change the fifoth_val from 0x200f0020 to 0x201f0020. (Well, i'm not sure what's right. but when i have checked, the fifoth_depth is 0x40. Then Rx_MASK = FIFOTH_DEPTH/2 - 1, TX_MASK = FIFOTH_DEPTH/2.
You are right. I checked the document, and found that RX_MASK is recommened to be set by (FIFOTH_DEPTH/2 - 1) as you said.
- };
- mmc@12210000 {
status = "disabled";- };
- mmc@12220000 {
samsung,bus-width = <4>;samsung,timing = <1 2 3>;fifoth_val = <0x200f0020>;Ditto.
- };
- mmc@12230000 {
status = "disabled";- };
+}; diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig new file mode 100644 index 0000000..6159692 --- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3
+config SYS_BOARD
- default "odroid-xu3"
+config SYS_VENDOR
- default "samsung"
+config SYS_CONFIG_NAME
- default "odroid_xu3"
+endif diff --git a/board/samsung/odroid-xu3/MAINTAINERS b/board/samsung/odroid-xu3/MAINTAINERS new file mode 100644 index 0000000..50cf928 --- /dev/null +++ b/board/samsung/odroid-xu3/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID-XU3 BOARD +M: Hyungwon Hwang human.hwang@samsung.com +S: Maintained +F: board/samsung/odroid-xu3/ +F: include/configs/odroid_xu3.h +F: configs/odroid-xu3_defconfig diff --git a/board/samsung/odroid-xu3/Makefile b/board/samsung/odroid-xu3/Makefile new file mode 100644 index 0000000..85ae5c5 --- /dev/null +++ b/board/samsung/odroid-xu3/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := odroid-xu3.o diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..8c54842 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,122 @@ +/*
- Copyright (C) 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include "setup.h"
+DECLARE_GLOBAL_DATA_PTR;
+unsigned int get_board_rev(void) +{
- return 0;
+}
+int exynos_init(void) +{
- return 0;
+}
+#ifdef CONFIG_BOARD_EARLY_INIT_F +static int board_clock_init(void) +{
- unsigned int set, clr, clr_src_cpu, clr_pll_con0;
- struct exynos5420_clock *clk = (struct exynos5420_clock *)
samsung_get_base_clock();
- /*
* CMU_CPU clocks src to MPLL* Bit values: 0 ; 1* MUX_APLL_SEL: FIN_PLL ; FOUT_APLL* MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL- */
- /* Set CMU_CPU clocks src to OSCCLK */
- clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);
- set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- /* Set APLL to 1200MHz */
- clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
PLL_ENABLE(1);- set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
- while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CMU_CPU clocks src to APLL */
- set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |
PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);- set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |
PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);- clrsetbits_le32(&clk->div_cpu0, clr, set);
- while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
continue;- /* Set MPLL to 800MHz */
- set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
- while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CLKMUX_UART src to MPLL */
- clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) |
UART3_SEL(7);
- set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) |
UART3_SEL(3); +
- clrsetbits_le32(&clk->src_peric0, clr, set);
- /* Set SCLK_UART to 400 MHz (MPLL / 2) */
- clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
UART3_RATIO(15);- set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |
UART3_RATIO(1);- clrsetbits_le32(&clk->div_peric0, clr, set);
- while (readl(&clk->div_stat_peric0) &
DIV_STAT_PERIC0_CHANGING)
continue;- /* Set CLKMUX_MMC src to MPLL */
- clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);
- set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);
- clrsetbits_le32(&clk->src_fsys, clr, set);
- clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) |
MMC2_RATIO(0x3ff);
- set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);
- clrsetbits_le32(&clk->div_fsys1, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_fsys1) &
DIV_STAT_FSYS1_CHANGING)
continue;- return 0;
+}
+int exynos_early_init_f(void) +{
- return board_clock_init();
+} +#endif diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h new file mode 100644 index 0000000..143c189 --- /dev/null +++ b/board/samsung/odroid-xu3/setup.h @@ -0,0 +1,95 @@ +/*
- (C) Copyright 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __ODROID_XU3_SETUP__ +#define __ODROID_XU3_SETUP__
+#define SDIV(x) ((x) & 0x7) +#define PDIV(x) (((x) & 0x3f) << 8) +#define MDIV(x) (((x) & 0x3ff) << 16) +#define FSEL(x) (((x) & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) (((x) & 0x1) << 31)
+/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) ((x) & 0x1) +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
+/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) ((x) & 0x7) +#define CORE_SEL(x) (((x) & 0x7) << 16) +#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) || \
(x) & APLL_SEL(1)|| \
(x) & CORE_SEL(0)|| \
(x) & CORE_SEL(1))+/* CLK_DIV_CPU0 */ +#define ARM_RATIO(x) ((x) & 0x7) +#define CPUD_RATIO(x) (((x) & 0x7) << 4) +#define ATB_RATIO(x) (((x) & 0x7) << 16) +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) +#define APLL_RATIO(x) (((x) & 0x7) << 24) +#define ARM2_RATIO(x) (((x) & 0x7) << 28)
+/* CLK_DIV_STAT_CPU0 */ +#define DIV_CPUD(x) (((x) & 0x1) << 4) +#define DIV_ATB(x) (((x) & 0x1) << 16) +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) +#define DIV_APLL(x) (((x) & 0x1) << 24) +#define DIV_ARM2(x) (((x) & 0x1) << 28)
+#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \
DIV_ATB(DIV_STAT_CHANGING) | \DIV_PCLK_DBG(DIV_STAT_CHANGING) |\
DIV_APLL(DIV_STAT_CHANGING) | \DIV_ARM2(DIV_STAT_CHANGING))+/* Set CLK_SRC_PERIC0 */ +#define UART0_SEL(x) (((x) & 0xf) << 4) +#define UART1_SEL(x) (((x) & 0xf) << 8) +#define UART2_SEL(x) (((x) & 0xf) << 12) +#define UART3_SEL(x) (((x) & 0xf) << 16)
+/* Set CLK_DIV_PERIC0 */ +#define UART0_RATIO(x) (((x) & 0xf) << 8) +#define UART1_RATIO(x) (((x) & 0xf) << 12) +#define UART2_RATIO(x) (((x) & 0xf) << 16) +#define UART3_RATIO(x) (((x) & 0xf) << 20)
+/* Set CLK_DIV_STAT_PERIC0 */ +#define DIV_UART0(x) ((x) & 0x1) +#define DIV_UART1(x) (((x) & 0x1) << 4) +#define DIV_UART2(x) (((x) & 0x1) << 8) +#define DIV_UART3(x) (((x) & 0x1) << 12) +#define DIV_UART4(x) (((x) & 0x1) << 16)
+#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
DIV_UART3(DIV_STAT_CHANGING) | \DIV_UART2(DIV_STAT_CHANGING) | \DIV_UART1(DIV_STAT_CHANGING) | \DIV_UART0(DIV_STAT_CHANGING))+/* CLK_SRC_FSYS */ +#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8) +#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12) +#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16)
+/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0x3ff) +#define MMC1_RATIO(x) (((x) & 0x3ff) << 10) +#define MMC2_RATIO(x) (((x) & 0x3ff) << 20)
+#define DIV_MMC0(x) (((x) & 1) << 20) +#define DIV_MMC1(x) (((x) & 1) << 24) +#define DIV_MMC2(x) (((x) & 1) << 28)
+#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
DIV_MMC1(DIV_STAT_CHANGING) | \DIV_MMC2(DIV_STAT_CHANGING))+#endif diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig new file mode 100644 index 0000000..74aa0cf --- /dev/null +++ b/configs/odroid-xu3_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID_XU3=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 807e96b..660b6ae 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -166,11 +166,6 @@ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \
- "bootdelay=0\0" \
- "dfu_alt_system="CONFIG_DFU_ALT \
- "dfu_alt_info=Please reset the board\0" \
- "consoleon=set console console=ttySAC1,115200n8; save;
reset\0" \
- "consoleoff=set console console=ram; save; reset\0" \ "initrdname=uInitrd\0" \ "initrdaddr=42000000\0" \ "fdtaddr=40800000\0"
This is not XU3, separate the patch.
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h new file mode 100644 index 0000000..1d53653 --- /dev/null +++ b/include/configs/odroid_xu3.h @@ -0,0 +1,133 @@ +/*
- Copyright (C) 2013 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H
+#include "exynos5-common.h"
+#define CONFIG_SYS_PROMPT "ODROID-XU3 # " +#define CONFIG_IDENT_STRING " for ODROID-XU3"
+#define CONFIG_BOARD_COMMON
+#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000
+/* select serial console configuration */ +#define CONFIG_SERIAL2 /* use SERIAL 2 */
+#define TZPC_BASE_OFFSET 0x10000
+#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT
+/*
- FIXME: The number of bank is actually 8. But there is no way to
reserver the
- last 16 Mib in the last bank now. So I just excluded the last
bank
- temporally.
- */
+#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_SIZE +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +#define CONFIG_BOOTCOMMAND "run autoboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" + +/*
- For details, refer the documentation: doc/README.odroid
+*/ +#ifdef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_EXTRA_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart}
${kerneladdr} " \
"${kernelname}\0" \- "loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart}
${initrdaddr} " \
"${initrdname}\0" \- "loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart}
${fdtaddr} " \
"${fdtfile}\0" \- "check_ramdisk=" \
"if run loadinitrd; then " \"setenv initrd_addr ${initrdaddr};" \"else " \"setenv initrd_addr -;" \"fi;\0" \- "check_dtb=" \
"if run loaddtb; then " \"setenv fdt_addr ${fdtaddr};" \"else " \"setenv fdt_addr;" \"fi;\0" \- "kernel_args=" \
"setenv bootargsroot=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \
" rootwait ${console} ${opts}\0" \- "boot_fit=" \
"setenv kerneladdr 0x42000000;" \"setenv kernelname Image.itb;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kerneladdr}#${boardname}\0" \- "boot_uimg=" \
"setenv kerneladdr 0x40007FC0;" \"setenv kernelname uImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kerneladdr} ${initrd_addr}${fdt_addr};\0" \
- "boot_zimg=" \
"setenv kerneladdr 0x40007FC0;" \"setenv kernelname zImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootz ${kerneladdr} ${initrd_addr}${fdt_addr};\0" \
- "autoboot=" \
"if test -e mmc 0 Image.itb; then; " \"run boot_fit;" \"elif test -e mmc 0 zImage; then; " \"run boot_zimg;" \"elif test -e mmc 0 uImage; then; " \"run boot_uimg;" \"fi;\0" \- "console=" CONFIG_DEFAULT_CONSOLE \
- "mmcbootdev=0\0" \
- "mmcbootpart=1\0" \
- "mmcrootdev=0\0" \
- "mmcrootpart=2\0" \
- "bootdelay=0\0" \
- "dfu_alt_info=Please reset the board\0" \
- "consoleon=set console console=ttySAC2,115200n8; save;
reset\0" \
- "consoleoff=set console console=ram; save; reset\0" \
I think you want to remove these.
I thought I removed it. There was a mistake when I made this patch. I am Sorry for that.
Best Regards, Jaehoon Chung
- "initrdname=uInitrd\0" \
- "initrdaddr=42000000\0" \
- "fdtaddr=40800000\0"
+/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ +#undef CONFIG_EXYNOS_TMU +#undef CONFIG_TMU_CMD_DTT
+#ifdef CONFIG_CMD_NET +#undef CONFIG_CMD_NET +#undef CONFIG_SMC911X +#undef CONFIG_CMD_PXE +#undef CONFIG_MENU +#endif
+#endif /* __CONFIG_H */
On Thu, 2014-11-27 at 22:21 +0900, Hyungwon Hwang wrote:
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Tested-by: Lukasz Majewski l.majewski@samsung.com Acked-by: Lukasz Majewski l.majewski@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com
index 0000000..533d88e --- /dev/null +++ b/arch/arm/dts/exynos5422-odroidxu3.dts
- mmc@12200000 {
samsung,bus-width = <8>;samsung,timing = <1 3 3>;fifoth_val = <0x200f0020>;- };
Apart from the fifoth_val, all this information is already part of the incude exynos54xx dtsi, so those fields can be removed.
As
- mmc@12210000 {
status = "disabled";- };
Not needed, Already disabled in exynos54xx dtsi
- mmc@12220000 {
samsung,bus-width = <4>;samsung,timing = <1 2 3>;fifoth_val = <0x200f0020>;- };
Same as above
- mmc@12230000 {
status = "disabled";- };
+};
Same as above, Already disabled in exynos54xx dtsi
diff --git a/board/samsung/odroid-xu3/Makefile b/board/samsung/odroid-xu3/Makefile new file mode 100644 index 0000000..85ae5c5 --- /dev/null +++ b/board/samsung/odroid-xu3/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := odroid-xu3.o diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..8c54842 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,122 @@ +/*
- Copyright (C) 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include "setup.h"
+DECLARE_GLOBAL_DATA_PTR;
+unsigned int get_board_rev(void) +{
- return 0;
+}
+int exynos_init(void) +{
- return 0;
+}
+#ifdef CONFIG_BOARD_EARLY_INIT_F +static int board_clock_init(void) +{
- unsigned int set, clr, clr_src_cpu, clr_pll_con0;
- struct exynos5420_clock *clk = (struct exynos5420_clock *)
samsung_get_base_clock();- /*
* CMU_CPU clocks src to MPLL* Bit values: 0 ; 1* MUX_APLL_SEL: FIN_PLL ; FOUT_APLL* MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL- */
- /* Set CMU_CPU clocks src to OSCCLK */
- clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);
- set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- /* Set APLL to 1200MHz */
- clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
PLL_ENABLE(1);- set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
- while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CMU_CPU clocks src to APLL */
- set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |
PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);- set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |
PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);- clrsetbits_le32(&clk->div_cpu0, clr, set);
- while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
continue;- /* Set MPLL to 800MHz */
- set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
- while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CLKMUX_UART src to MPLL */
- clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | UART3_SEL(7);
- set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | UART3_SEL(3);
- clrsetbits_le32(&clk->src_peric0, clr, set);
- /* Set SCLK_UART to 400 MHz (MPLL / 2) */
- clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
UART3_RATIO(15);- set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |
UART3_RATIO(1);- clrsetbits_le32(&clk->div_peric0, clr, set);
- while (readl(&clk->div_stat_peric0) & DIV_STAT_PERIC0_CHANGING)
continue;- /* Set CLKMUX_MMC src to MPLL */
- clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);
- set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);
- clrsetbits_le32(&clk->src_fsys, clr, set);
- clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | MMC2_RATIO(0x3ff);
- set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);
- clrsetbits_le32(&clk->div_fsys1, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
continue;- return 0;
+}
+int exynos_early_init_f(void) +{
- return board_clock_init();
+} +#endif diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h new file mode 100644 index 0000000..143c189 --- /dev/null +++ b/board/samsung/odroid-xu3/setup.h @@ -0,0 +1,95 @@ +/*
- (C) Copyright 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __ODROID_XU3_SETUP__ +#define __ODROID_XU3_SETUP__
+#define SDIV(x) ((x) & 0x7) +#define PDIV(x) (((x) & 0x3f) << 8) +#define MDIV(x) (((x) & 0x3ff) << 16) +#define FSEL(x) (((x) & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) (((x) & 0x1) << 31)
+/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) ((x) & 0x1) +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
+/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) ((x) & 0x7) +#define CORE_SEL(x) (((x) & 0x7) << 16) +#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) || \
(x) & APLL_SEL(1) || \(x) & CORE_SEL(0) || \(x) & CORE_SEL(1))+/* CLK_DIV_CPU0 */ +#define ARM_RATIO(x) ((x) & 0x7) +#define CPUD_RATIO(x) (((x) & 0x7) << 4) +#define ATB_RATIO(x) (((x) & 0x7) << 16) +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) +#define APLL_RATIO(x) (((x) & 0x7) << 24) +#define ARM2_RATIO(x) (((x) & 0x7) << 28)
+/* CLK_DIV_STAT_CPU0 */ +#define DIV_CPUD(x) (((x) & 0x1) << 4) +#define DIV_ATB(x) (((x) & 0x1) << 16) +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) +#define DIV_APLL(x) (((x) & 0x1) << 24) +#define DIV_ARM2(x) (((x) & 0x1) << 28)
+#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \
DIV_ATB(DIV_STAT_CHANGING) | \DIV_PCLK_DBG(DIV_STAT_CHANGING) | \DIV_APLL(DIV_STAT_CHANGING) | \DIV_ARM2(DIV_STAT_CHANGING))+/* Set CLK_SRC_PERIC0 */ +#define UART0_SEL(x) (((x) & 0xf) << 4) +#define UART1_SEL(x) (((x) & 0xf) << 8) +#define UART2_SEL(x) (((x) & 0xf) << 12) +#define UART3_SEL(x) (((x) & 0xf) << 16)
+/* Set CLK_DIV_PERIC0 */ +#define UART0_RATIO(x) (((x) & 0xf) << 8) +#define UART1_RATIO(x) (((x) & 0xf) << 12) +#define UART2_RATIO(x) (((x) & 0xf) << 16) +#define UART3_RATIO(x) (((x) & 0xf) << 20)
+/* Set CLK_DIV_STAT_PERIC0 */ +#define DIV_UART0(x) ((x) & 0x1) +#define DIV_UART1(x) (((x) & 0x1) << 4) +#define DIV_UART2(x) (((x) & 0x1) << 8) +#define DIV_UART3(x) (((x) & 0x1) << 12) +#define DIV_UART4(x) (((x) & 0x1) << 16)
+#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
DIV_UART3(DIV_STAT_CHANGING) | \DIV_UART2(DIV_STAT_CHANGING) | \DIV_UART1(DIV_STAT_CHANGING) | \DIV_UART0(DIV_STAT_CHANGING))+/* CLK_SRC_FSYS */ +#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8) +#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12) +#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16)
+/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0x3ff) +#define MMC1_RATIO(x) (((x) & 0x3ff) << 10) +#define MMC2_RATIO(x) (((x) & 0x3ff) << 20)
+#define DIV_MMC0(x) (((x) & 1) << 20) +#define DIV_MMC1(x) (((x) & 1) << 24) +#define DIV_MMC2(x) (((x) & 1) << 28)
+#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
DIV_MMC1(DIV_STAT_CHANGING) | \DIV_MMC2(DIV_STAT_CHANGING))+#endif diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig new file mode 100644 index 0000000..74aa0cf --- /dev/null +++ b/configs/odroid-xu3_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID_XU3=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 807e96b..660b6ae 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -166,11 +166,6 @@ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \
- "bootdelay=0\0" \
- "dfu_alt_system="CONFIG_DFU_ALT \
- "dfu_alt_info=Please reset the board\0" \
- "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \
- "consoleoff=set console console=ram; save; reset\0" \ "initrdname=uInitrd\0" \ "initrdaddr=42000000\0" \ "fdtaddr=40800000\0"
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h new file mode 100644 index 0000000..1d53653 --- /dev/null +++ b/include/configs/odroid_xu3.h @@ -0,0 +1,133 @@ +/*
- Copyright (C) 2013 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H
+#include "exynos5-common.h"
+#define CONFIG_SYS_PROMPT "ODROID-XU3 # " +#define CONFIG_IDENT_STRING " for ODROID-XU3"
+#define CONFIG_BOARD_COMMON
+#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000
+/* select serial console configuration */ +#define CONFIG_SERIAL2 /* use SERIAL 2 */
+#define TZPC_BASE_OFFSET 0x10000
+#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT
+/*
- FIXME: The number of bank is actually 8. But there is no way to reserver the
- last 16 Mib in the last bank now. So I just excluded the last bank
- temporally.
- */
+#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_SIZE +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+#define CONFIG_BOOTCOMMAND "run autoboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
+/*
- For details, refer the documentation: doc/README.odroid
+*/ +#ifdef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_EXTRA_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \
"${kernelname}\0" \- "loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \
"${initrdname}\0" \- "loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \
"${fdtfile}\0" \- "check_ramdisk=" \
"if run loadinitrd; then " \"setenv initrd_addr ${initrdaddr};" \"else " \"setenv initrd_addr -;" \"fi;\0" \- "check_dtb=" \
"if run loaddtb; then " \"setenv fdt_addr ${fdtaddr};" \"else " \"setenv fdt_addr;" \"fi;\0" \- "kernel_args=" \
"setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \" rootwait ${console} ${opts}\0" \- "boot_fit=" \
"setenv kerneladdr 0x42000000;" \"setenv kernelname Image.itb;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kerneladdr}#${boardname}\0" \- "boot_uimg=" \
"setenv kerneladdr 0x40007FC0;" \"setenv kernelname uImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \- "boot_zimg=" \
"setenv kerneladdr 0x40007FC0;" \"setenv kernelname zImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \- "autoboot=" \
"if test -e mmc 0 Image.itb; then; " \"run boot_fit;" \"elif test -e mmc 0 zImage; then; " \"run boot_zimg;" \"elif test -e mmc 0 uImage; then; " \"run boot_uimg;" \"fi;\0" \- "console=" CONFIG_DEFAULT_CONSOLE \
- "mmcbootdev=0\0" \
- "mmcbootpart=1\0" \
- "mmcrootdev=0\0" \
- "mmcrootpart=2\0" \
- "bootdelay=0\0" \
- "dfu_alt_info=Please reset the board\0" \
- "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
- "consoleoff=set console console=ram; save; reset\0" \
- "initrdname=uInitrd\0" \
- "initrdaddr=42000000\0" \
- "fdtaddr=40800000\0"
Would be nice if config_distro_defaults.h config_distro_bootcmd.h could be used instead an odroid XU3 specific default environment & settings..
On Thu, 27 Nov 2014 17:35:05 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
Would be nice if config_distro_defaults.h config_distro_bootcmd.h could be used instead an odroid XU3 specific default environment & settings..
You have the peach-pi board. Right? Does it boot without typing something to boot linux kernel withour modification? I explored the source code, but could not find the point where makes the peach-pi board boot automatically with the configuration.
On Fri, 2014-11-28 at 14:00 +0900, Hyungwon Hwang wrote:
On Thu, 27 Nov 2014 17:35:05 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
Would be nice if config_distro_defaults.h config_distro_bootcmd.h could be used instead an odroid XU3 specific default environment & settings..
You have the peach-pi board. Right? Does it boot without typing something to boot linux kernel withour modification? I explored the source code, but could not find the point where makes the peach-pi board boot automatically with the configuration.
exynos5-common includes config_distro_bootcmd.h and defines CONFIG_EXTRA_ENV_SETTINGS to include BOOTENV. BOOTENV in turn is defines in the config_distro_bootcmd.h file and defined a bootcmd which searches for a boot script on various devies.
So simply not overriding CONFIG_EXTRA_ENV_SETTINGS should do the right thing.
On Thu, 2014-11-27 at 22:21 +0900, Hyungwon Hwang wrote:
This patch adds support for Odroid-XU3.
I can't seem to access the EMMC with this patch, is that expected?
--- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3
+config SYS_BOARD
- default "odroid-xu3"
+config SYS_VENDOR
- default "samsung"
+config SYS_CONFIG_NAME
- default "odroid_xu3"
+endif
I was studying the different between the peach-pi and the XU3 hardware enablement a bit. I was wondering whta's the rationale for the XU3 having it's own board file and reconfiguring various clocks? Does the hardkernel SPL/bl2 not setup things correctly?
diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..8c54842 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,122 @@ +/*
- Copyright (C) 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include "setup.h"
+DECLARE_GLOBAL_DATA_PTR;
+unsigned int get_board_rev(void) +{
- return 0;
+}
+int exynos_init(void) +{
- return 0;
+}
+#ifdef CONFIG_BOARD_EARLY_INIT_F +static int board_clock_init(void) +{
- unsigned int set, clr, clr_src_cpu, clr_pll_con0;
- struct exynos5420_clock *clk = (struct exynos5420_clock *)
samsung_get_base_clock();- /*
* CMU_CPU clocks src to MPLL* Bit values: 0 ; 1* MUX_APLL_SEL: FIN_PLL ; FOUT_APLL* MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL- */
- /* Set CMU_CPU clocks src to OSCCLK */
- clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);
- set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- /* Set APLL to 1200MHz */
- clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
PLL_ENABLE(1);- set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
- while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CMU_CPU clocks src to APLL */
- set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |
PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);- set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |
PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);- clrsetbits_le32(&clk->div_cpu0, clr, set);
- while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
continue;- /* Set MPLL to 800MHz */
- set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
- while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CLKMUX_UART src to MPLL */
- clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | UART3_SEL(7);
- set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | UART3_SEL(3);
- clrsetbits_le32(&clk->src_peric0, clr, set);
- /* Set SCLK_UART to 400 MHz (MPLL / 2) */
- clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
UART3_RATIO(15);- set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |
UART3_RATIO(1);- clrsetbits_le32(&clk->div_peric0, clr, set);
- while (readl(&clk->div_stat_peric0) & DIV_STAT_PERIC0_CHANGING)
continue;- /* Set CLKMUX_MMC src to MPLL */
- clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);
- set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);
- clrsetbits_le32(&clk->src_fsys, clr, set);
- clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | MMC2_RATIO(0x3ff);
- set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);
- clrsetbits_le32(&clk->div_fsys1, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
continue;- return 0;
+}
+int exynos_early_init_f(void) +{
- return board_clock_init();
+} +#endif
On Thu, 27 Nov 2014 22:45:18 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
On Thu, 2014-11-27 at 22:21 +0900, Hyungwon Hwang wrote:
This patch adds support for Odroid-XU3.
I can't seem to access the EMMC with this patch, is that expected?
Yes. EMMC is not supported yet. Actually even I did not test whether it works or not. EMMC support will be done soon.
--- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3
+config SYS_BOARD
- default "odroid-xu3"
+config SYS_VENDOR
- default "samsung"
+config SYS_CONFIG_NAME
- default "odroid_xu3"
+endif
I was studying the different between the peach-pi and the XU3 hardware enablement a bit. I was wondering whta's the rationale for the XU3 having it's own board file and reconfiguring various clocks? Does the hardkernel SPL/bl2 not setup things correctly?
Hmm. It is my first time to make codes to add support for new board, and I am not sure what is right. Is it needless to set clocks for the cases when SPL/BL2 is expected to set clocks already?
diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..8c54842 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,122 @@ +/*
- Copyright (C) 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include "setup.h"
+DECLARE_GLOBAL_DATA_PTR;
+unsigned int get_board_rev(void) +{
- return 0;
+}
+int exynos_init(void) +{
- return 0;
+}
+#ifdef CONFIG_BOARD_EARLY_INIT_F +static int board_clock_init(void) +{
- unsigned int set, clr, clr_src_cpu, clr_pll_con0;
- struct exynos5420_clock *clk = (struct exynos5420_clock *)
samsung_get_base_clock();
- /*
* CMU_CPU clocks src to MPLL* Bit values: 0 ; 1* MUX_APLL_SEL: FIN_PLL ; FOUT_APLL* MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL- */
- /* Set CMU_CPU clocks src to OSCCLK */
- clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);
- set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- /* Set APLL to 1200MHz */
- clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
PLL_ENABLE(1);- set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
- while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CMU_CPU clocks src to APLL */
- set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |
PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);- set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |
PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);- clrsetbits_le32(&clk->div_cpu0, clr, set);
- while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
continue;- /* Set MPLL to 800MHz */
- set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
- while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CLKMUX_UART src to MPLL */
- clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) |
UART3_SEL(7);
- set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) |
UART3_SEL(3); +
- clrsetbits_le32(&clk->src_peric0, clr, set);
- /* Set SCLK_UART to 400 MHz (MPLL / 2) */
- clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
UART3_RATIO(15);- set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |
UART3_RATIO(1);- clrsetbits_le32(&clk->div_peric0, clr, set);
- while (readl(&clk->div_stat_peric0) &
DIV_STAT_PERIC0_CHANGING)
continue;- /* Set CLKMUX_MMC src to MPLL */
- clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);
- set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);
- clrsetbits_le32(&clk->src_fsys, clr, set);
- clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) |
MMC2_RATIO(0x3ff);
- set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);
- clrsetbits_le32(&clk->div_fsys1, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_fsys1) &
DIV_STAT_FSYS1_CHANGING)
continue;- return 0;
+}
+int exynos_early_init_f(void) +{
- return board_clock_init();
+} +#endif
On Fri, 2014-11-28 at 11:13 +0900, Hyungwon Hwang wrote:
On Thu, 27 Nov 2014 22:45:18 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
On Thu, 2014-11-27 at 22:21 +0900, Hyungwon Hwang wrote:
This patch adds support for Odroid-XU3.
I can't seem to access the EMMC with this patch, is that expected?
Yes. EMMC is not supported yet. Actually even I did not test whether it works or not. EMMC support will be done soon.
--- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3
+config SYS_BOARD
- default "odroid-xu3"
+config SYS_VENDOR
- default "samsung"
+config SYS_CONFIG_NAME
- default "odroid_xu3"
+endif
I was studying the different between the peach-pi and the XU3 hardware enablement a bit. I was wondering whta's the rationale for the XU3 having it's own board file and reconfiguring various clocks? Does the hardkernel SPL/bl2 not setup things correctly?
Hmm. It is my first time to make codes to add support for new board, and I am not sure what is right. Is it needless to set clocks for the cases when SPL/BL2 is expected to set clocks already?
That is my impresssion indeed. If you look at the enablement for the SMDK5420 board and the peach pi/pit boards they don't do any setup of these clocks, the only time that's done is in exynos5420_system_clock_init (from clock_init_exynos5.c) which only gets executed on SPL builds.
I did a quick test changing SYS_BOARD to smdk5420 and that worked without any problems. So in principle you should be able to drop the odroid-xu3 board directory and simply add your Kconfig snippet to board/samsung/smdk5420/Kconfig as is done for the Peach boards
diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..8c54842 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,122 @@ +/*
- Copyright (C) 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include "setup.h"
+DECLARE_GLOBAL_DATA_PTR;
+unsigned int get_board_rev(void) +{
- return 0;
+}
+int exynos_init(void) +{
- return 0;
+}
+#ifdef CONFIG_BOARD_EARLY_INIT_F +static int board_clock_init(void) +{
- unsigned int set, clr, clr_src_cpu, clr_pll_con0;
- struct exynos5420_clock *clk = (struct exynos5420_clock *)
samsung_get_base_clock();
- /*
* CMU_CPU clocks src to MPLL* Bit values: 0 ; 1* MUX_APLL_SEL: FIN_PLL ; FOUT_APLL* MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL- */
- /* Set CMU_CPU clocks src to OSCCLK */
- clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);
- set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- /* Set APLL to 1200MHz */
- clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
PLL_ENABLE(1);- set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
- while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CMU_CPU clocks src to APLL */
- set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |
PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);- set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |
PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);- clrsetbits_le32(&clk->div_cpu0, clr, set);
- while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
continue;- /* Set MPLL to 800MHz */
- set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
- while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CLKMUX_UART src to MPLL */
- clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) |
UART3_SEL(7);
- set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) |
UART3_SEL(3); +
- clrsetbits_le32(&clk->src_peric0, clr, set);
- /* Set SCLK_UART to 400 MHz (MPLL / 2) */
- clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
UART3_RATIO(15);- set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |
UART3_RATIO(1);- clrsetbits_le32(&clk->div_peric0, clr, set);
- while (readl(&clk->div_stat_peric0) &
DIV_STAT_PERIC0_CHANGING)
continue;- /* Set CLKMUX_MMC src to MPLL */
- clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);
- set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);
- clrsetbits_le32(&clk->src_fsys, clr, set);
- clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) |
MMC2_RATIO(0x3ff);
- set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);
- clrsetbits_le32(&clk->div_fsys1, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_fsys1) &
DIV_STAT_FSYS1_CHANGING)
continue;- return 0;
+}
+int exynos_early_init_f(void) +{
- return board_clock_init();
+} +#endif
On 11/28/2014 11:13 AM, Hyungwon Hwang wrote:
On Thu, 27 Nov 2014 22:45:18 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
On Thu, 2014-11-27 at 22:21 +0900, Hyungwon Hwang wrote:
This patch adds support for Odroid-XU3.
I can't seem to access the EMMC with this patch, is that expected?
Yes. EMMC is not supported yet. Actually even I did not test whether it works or not. EMMC support will be done soon.
Actually, eMMC doesn't work with these patches. But I have enabled the eMMC based on these..but I needs more time to support booting.
Best Regards, Jaehoon Chung
--- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3
+config SYS_BOARD
- default "odroid-xu3"
+config SYS_VENDOR
- default "samsung"
+config SYS_CONFIG_NAME
- default "odroid_xu3"
+endif
I was studying the different between the peach-pi and the XU3 hardware enablement a bit. I was wondering whta's the rationale for the XU3 having it's own board file and reconfiguring various clocks? Does the hardkernel SPL/bl2 not setup things correctly?
Hmm. It is my first time to make codes to add support for new board, and I am not sure what is right. Is it needless to set clocks for the cases when SPL/BL2 is expected to set clocks already?
diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..8c54842 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,122 @@ +/*
- Copyright (C) 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include "setup.h"
+DECLARE_GLOBAL_DATA_PTR;
+unsigned int get_board_rev(void) +{
- return 0;
+}
+int exynos_init(void) +{
- return 0;
+}
+#ifdef CONFIG_BOARD_EARLY_INIT_F +static int board_clock_init(void) +{
- unsigned int set, clr, clr_src_cpu, clr_pll_con0;
- struct exynos5420_clock *clk = (struct exynos5420_clock *)
samsung_get_base_clock();
- /*
* CMU_CPU clocks src to MPLL* Bit values: 0 ; 1* MUX_APLL_SEL: FIN_PLL ; FOUT_APLL* MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL- */
- /* Set CMU_CPU clocks src to OSCCLK */
- clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);
- set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- /* Set APLL to 1200MHz */
- clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
PLL_ENABLE(1);- set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
- while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CMU_CPU clocks src to APLL */
- set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
continue;- clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |
PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);- set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |
PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);- clrsetbits_le32(&clk->div_cpu0, clr, set);
- while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
continue;- /* Set MPLL to 800MHz */
- set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
- while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
continue;- /* Set CLKMUX_UART src to MPLL */
- clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) |
UART3_SEL(7);
- set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) |
UART3_SEL(3); +
- clrsetbits_le32(&clk->src_peric0, clr, set);
- /* Set SCLK_UART to 400 MHz (MPLL / 2) */
- clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
UART3_RATIO(15);- set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |
UART3_RATIO(1);- clrsetbits_le32(&clk->div_peric0, clr, set);
- while (readl(&clk->div_stat_peric0) &
DIV_STAT_PERIC0_CHANGING)
continue;- /* Set CLKMUX_MMC src to MPLL */
- clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);
- set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);
- clrsetbits_le32(&clk->src_fsys, clr, set);
- clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) |
MMC2_RATIO(0x3ff);
- set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);
- clrsetbits_le32(&clk->div_fsys1, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_fsys1) &
DIV_STAT_FSYS1_CHANGING)
continue;- return 0;
+}
+int exynos_early_init_f(void) +{
- return board_clock_init();
+} +#endif
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hey Jaehoon,
On Fri, 2014-11-28 at 17:54 +0900, Jaehoon Chung wrote:
On 11/28/2014 11:13 AM, Hyungwon Hwang wrote:
On Thu, 27 Nov 2014 22:45:18 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
On Thu, 2014-11-27 at 22:21 +0900, Hyungwon Hwang wrote:
This patch adds support for Odroid-XU3.
I can't seem to access the EMMC with this patch, is that expected?
Yes. EMMC is not supported yet. Actually even I did not test whether it works or not. EMMC support will be done soon.
Actually, eMMC doesn't work with these patches. But I have enabled the eMMC based on these..but I needs more time to support booting.
If you have initial patches for eMMC would be great if you could share those. I'm quite interested in testing that even if it's still quite raw
Hi,
On 27 November 2014 at 06:21, Hyungwon Hwang human.hwang@samsung.com wrote:
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Tested-by: Lukasz Majewski l.majewski@samsung.com Acked-by: Lukasz Majewski l.majewski@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com
Changes for v3:
- Remove unnecessary node from DT file
- Remove unnecessary features from config file
- Remove unnecessary macros from board-specific header file
- Fix some trivial typos in comments
Changes for v4:
- Add MMC FIFO buffer's configuration to DT file
- Make CONFIG_OF_CONTROL be set by the target information
- Add basic document to doc/README.odroid-xu3
- Add CONFIG_CMD_EXT4 to config file
- Add environment size and offset to config file
- Add extra default environment to make bootable without modification
- Remove unnecessary features from config file
Changes for v5:
- Convert /include/ to #include in DT file
Changes for v6:
- Separate out the documentation to new commit
- Remove unnecessary header file inclusions from the board-specific setup file
- Make the function board_clock_init be declared, only when CONFIG_BOARD_EARLY_INIT_F is defined
Changes for v7:
- Remove OF_CONTROL dependency from !SPL_BUILD
Changes for v8:
- Remove unnecessary properties in DT mmc node
Changes for v9:
- Remove useless variables in the default environment
- Replace the detailed information to the reference to the documentation
Great to see this series. I wanted to test it earlier but had problems with it not being reliable. I tracked this down to a uSD card (which works fine on other boards but boots reliably only to SPL on XU3).
arch/arm/cpu/armv7/exynos/Kconfig | 5 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 57 +++++++++++++++ board/samsung/odroid-xu3/Kconfig | 12 +++ board/samsung/odroid-xu3/MAINTAINERS | 6 ++ board/samsung/odroid-xu3/Makefile | 7 ++ board/samsung/odroid-xu3/odroid-xu3.c | 122 +++++++++++++++++++++++++++++++ board/samsung/odroid-xu3/setup.h | 95 ++++++++++++++++++++++++ configs/odroid-xu3_defconfig | 4 + include/configs/odroid.h | 5 -- include/configs/odroid_xu3.h | 133 ++++++++++++++++++++++++++++++++++ 11 files changed, 443 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 include/configs/odroid_xu3.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 13dbd95..16c9a0e 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -24,6 +24,10 @@ config TARGET_TRATS2 config TARGET_ODROID bool "Exynos4412 Odroid board"
+config TARGET_ODROID_XU3
bool "Exynos5422 Odroid board"select OF_CONTROLconfig TARGET_ARNDALE bool "Exynos5250 Arndale board" select SUPPORT_SPL @@ -65,6 +69,7 @@ source "board/samsung/universal_c210/Kconfig" source "board/samsung/origen/Kconfig" source "board/samsung/trats2/Kconfig" source "board/samsung/odroid/Kconfig" +source "board/samsung/odroid-xu3/Kconfig" source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e5846ea..a811b1b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -13,7 +13,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ exynos5420-peach-pit.dtb \
exynos5800-peach-pi.dtb
exynos5800-peach-pi.dtb \exynos5422-odroidxu3.dtb
Is it 5422 or 45800? Is there any difference really?
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644 index 0000000..533d88e --- /dev/null +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -0,0 +1,57 @@ +/*
- Odroid XU3 device tree source
- Copyright (c) 2014 Samsung Electronics Co., Ltd.
http://www.samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+/dts-v1/; +#include "exynos54xx.dtsi"
+/ {
model = "Odroid XU3 based on EXYNOS5422";compatible = "samsung,odroidxu3", "samsung,exynos5";aliases {serial0 = "/serial@12C00000";console = "/serial@12C20000";};memory {device_type = "memory";reg = <0x40000000 0x100000000x50000000 0x100000000x60000000 0x100000000x70000000 0x100000000x80000000 0x100000000x90000000 0x100000000xa0000000 0x100000000xb0000000 0xea00000>;};serial@12C20000 {status="okay";};mmc@12200000 {samsung,bus-width = <8>;samsung,timing = <1 3 3>;fifoth_val = <0x200f0020>;};mmc@12210000 {status = "disabled";};mmc@12220000 {samsung,bus-width = <4>;samsung,timing = <1 2 3>;fifoth_val = <0x200f0020>;};mmc@12230000 {status = "disabled";};+}; diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig new file mode 100644 index 0000000..6159692 --- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3
+config SYS_BOARD
default "odroid-xu3"+config SYS_VENDOR
default "samsung"+config SYS_CONFIG_NAME
default "odroid_xu3"+endif diff --git a/board/samsung/odroid-xu3/MAINTAINERS b/board/samsung/odroid-xu3/MAINTAINERS new file mode 100644 index 0000000..50cf928 --- /dev/null +++ b/board/samsung/odroid-xu3/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID-XU3 BOARD +M: Hyungwon Hwang human.hwang@samsung.com +S: Maintained +F: board/samsung/odroid-xu3/ +F: include/configs/odroid_xu3.h +F: configs/odroid-xu3_defconfig diff --git a/board/samsung/odroid-xu3/Makefile b/board/samsung/odroid-xu3/Makefile new file mode 100644 index 0000000..85ae5c5 --- /dev/null +++ b/board/samsung/odroid-xu3/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := odroid-xu3.o diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..8c54842 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,122 @@ +/*
- Copyright (C) 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include "setup.h"
+DECLARE_GLOBAL_DATA_PTR;
+unsigned int get_board_rev(void) +{
return 0;+}
+int exynos_init(void) +{
return 0;+}
+#ifdef CONFIG_BOARD_EARLY_INIT_F +static int board_clock_init(void) +{
unsigned int set, clr, clr_src_cpu, clr_pll_con0;struct exynos5420_clock *clk = (struct exynos5420_clock *)samsung_get_base_clock();
This stuff needs to move into SPL - if it works then perhaps hardkernel can do this work. It doesn't make sense to set up the clocks in SPL and then again in U-Boot.
At the least this should be commented as a temporary hack, and enable with a CONFIG_EXYNOS_REINIT_CLOCKS option, or something.
/** CMU_CPU clocks src to MPLL* Bit values: 0 ; 1* MUX_APLL_SEL: FIN_PLL ; FOUT_APLL* MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL*//* Set CMU_CPU clocks src to OSCCLK */clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))continue;/* Set APLL to 1200MHz */
Why not 1.7GHz?
clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |PLL_ENABLE(1);set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))continue;/* Set CMU_CPU clocks src to APLL */set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))continue;clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);clrsetbits_le32(&clk->div_cpu0, clr, set);while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)continue;/* Set MPLL to 800MHz */set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))continue;/* Set CLKMUX_UART src to MPLL */clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | UART3_SEL(7);set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | UART3_SEL(3);clrsetbits_le32(&clk->src_peric0, clr, set);/* Set SCLK_UART to 400 MHz (MPLL / 2) */clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |UART3_RATIO(15);set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |UART3_RATIO(1);clrsetbits_le32(&clk->div_peric0, clr, set);while (readl(&clk->div_stat_peric0) & DIV_STAT_PERIC0_CHANGING)continue;/* Set CLKMUX_MMC src to MPLL */clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);clrsetbits_le32(&clk->src_fsys, clr, set);clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | MMC2_RATIO(0x3ff);set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);clrsetbits_le32(&clk->div_fsys1, clr, set);/* Wait for divider ready status */while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)continue;return 0;+}
+int exynos_early_init_f(void) +{
return board_clock_init();+} +#endif diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h new file mode 100644 index 0000000..143c189 --- /dev/null +++ b/board/samsung/odroid-xu3/setup.h @@ -0,0 +1,95 @@ +/*
- (C) Copyright 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __ODROID_XU3_SETUP__ +#define __ODROID_XU3_SETUP__
+#define SDIV(x) ((x) & 0x7) +#define PDIV(x) (((x) & 0x3f) << 8) +#define MDIV(x) (((x) & 0x3ff) << 16) +#define FSEL(x) (((x) & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) (((x) & 0x1) << 31)
+/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) ((x) & 0x1) +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
+/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) ((x) & 0x7) +#define CORE_SEL(x) (((x) & 0x7) << 16) +#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) || \
(x) & APLL_SEL(1) || \(x) & CORE_SEL(0) || \(x) & CORE_SEL(1))+/* CLK_DIV_CPU0 */ +#define ARM_RATIO(x) ((x) & 0x7) +#define CPUD_RATIO(x) (((x) & 0x7) << 4) +#define ATB_RATIO(x) (((x) & 0x7) << 16) +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) +#define APLL_RATIO(x) (((x) & 0x7) << 24) +#define ARM2_RATIO(x) (((x) & 0x7) << 28)
+/* CLK_DIV_STAT_CPU0 */ +#define DIV_CPUD(x) (((x) & 0x1) << 4) +#define DIV_ATB(x) (((x) & 0x1) << 16) +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) +#define DIV_APLL(x) (((x) & 0x1) << 24) +#define DIV_ARM2(x) (((x) & 0x1) << 28)
+#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \
DIV_ATB(DIV_STAT_CHANGING) | \DIV_PCLK_DBG(DIV_STAT_CHANGING) | \DIV_APLL(DIV_STAT_CHANGING) | \DIV_ARM2(DIV_STAT_CHANGING))+/* Set CLK_SRC_PERIC0 */ +#define UART0_SEL(x) (((x) & 0xf) << 4) +#define UART1_SEL(x) (((x) & 0xf) << 8) +#define UART2_SEL(x) (((x) & 0xf) << 12) +#define UART3_SEL(x) (((x) & 0xf) << 16)
+/* Set CLK_DIV_PERIC0 */ +#define UART0_RATIO(x) (((x) & 0xf) << 8) +#define UART1_RATIO(x) (((x) & 0xf) << 12) +#define UART2_RATIO(x) (((x) & 0xf) << 16) +#define UART3_RATIO(x) (((x) & 0xf) << 20)
+/* Set CLK_DIV_STAT_PERIC0 */ +#define DIV_UART0(x) ((x) & 0x1) +#define DIV_UART1(x) (((x) & 0x1) << 4) +#define DIV_UART2(x) (((x) & 0x1) << 8) +#define DIV_UART3(x) (((x) & 0x1) << 12) +#define DIV_UART4(x) (((x) & 0x1) << 16)
+#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
DIV_UART3(DIV_STAT_CHANGING) | \DIV_UART2(DIV_STAT_CHANGING) | \DIV_UART1(DIV_STAT_CHANGING) | \DIV_UART0(DIV_STAT_CHANGING))+/* CLK_SRC_FSYS */ +#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8) +#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12) +#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16)
+/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0x3ff) +#define MMC1_RATIO(x) (((x) & 0x3ff) << 10) +#define MMC2_RATIO(x) (((x) & 0x3ff) << 20)
+#define DIV_MMC0(x) (((x) & 1) << 20) +#define DIV_MMC1(x) (((x) & 1) << 24) +#define DIV_MMC2(x) (((x) & 1) << 28)
+#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
DIV_MMC1(DIV_STAT_CHANGING) | \DIV_MMC2(DIV_STAT_CHANGING))+#endif diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig new file mode 100644 index 0000000..74aa0cf --- /dev/null +++ b/configs/odroid-xu3_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID_XU3=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 807e96b..660b6ae 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -166,11 +166,6 @@ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \
"bootdelay=0\0" \"dfu_alt_system="CONFIG_DFU_ALT \"dfu_alt_info=Please reset the board\0" \"consoleon=set console console=ttySAC1,115200n8; save; reset\0" \"consoleoff=set console console=ram; save; reset\0" \ "initrdname=uInitrd\0" \ "initrdaddr=42000000\0" \ "fdtaddr=40800000\0"diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h new file mode 100644 index 0000000..1d53653 --- /dev/null +++ b/include/configs/odroid_xu3.h @@ -0,0 +1,133 @@ +/*
- Copyright (C) 2013 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H
+#include "exynos5-common.h"
Should include exynos5420-common.h. If there are things in there that should not be common, then you could add a patch to move them out.
This causes a build warning in I2C.
+#define CONFIG_SYS_PROMPT "ODROID-XU3 # " +#define CONFIG_IDENT_STRING " for ODROID-XU3"
+#define CONFIG_BOARD_COMMON
+#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000
+/* select serial console configuration */ +#define CONFIG_SERIAL2 /* use SERIAL 2 */
+#define TZPC_BASE_OFFSET 0x10000
+#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT
+/*
- FIXME: The number of bank is actually 8. But there is no way to reserver the
- last 16 Mib in the last bank now. So I just excluded the last bank
- temporally.
- */
+#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_SIZE +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+#define CONFIG_BOOTCOMMAND "run autoboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
+/*
- For details, refer the documentation: doc/README.odroid
+*/ +#ifdef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_EXTRA_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \
"loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \"${kernelname}\0" \"loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \"${initrdname}\0" \"loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \"${fdtfile}\0" \"check_ramdisk=" \"if run loadinitrd; then " \"setenv initrd_addr ${initrdaddr};" \"else " \"setenv initrd_addr -;" \"fi;\0" \"check_dtb=" \"if run loaddtb; then " \"setenv fdt_addr ${fdtaddr};" \"else " \"setenv fdt_addr;" \"fi;\0" \"kernel_args=" \"setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \" rootwait ${console} ${opts}\0" \"boot_fit=" \"setenv kerneladdr 0x42000000;" \"setenv kernelname Image.itb;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kerneladdr}#${boardname}\0" \"boot_uimg=" \"setenv kerneladdr 0x40007FC0;" \"setenv kernelname uImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \"boot_zimg=" \"setenv kerneladdr 0x40007FC0;" \"setenv kernelname zImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \"autoboot=" \"if test -e mmc 0 Image.itb; then; " \"run boot_fit;" \"elif test -e mmc 0 zImage; then; " \"run boot_zimg;" \"elif test -e mmc 0 uImage; then; " \"run boot_uimg;" \"fi;\0" \"console=" CONFIG_DEFAULT_CONSOLE \"mmcbootdev=0\0" \"mmcbootpart=1\0" \"mmcrootdev=0\0" \"mmcrootpart=2\0" \"bootdelay=0\0" \"dfu_alt_info=Please reset the board\0" \"consoleon=set console console=ttySAC2,115200n8; save; reset\0" \"consoleoff=set console console=ram; save; reset\0" \"initrdname=uInitrd\0" \"initrdaddr=42000000\0" \"fdtaddr=40800000\0"+/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ +#undef CONFIG_EXYNOS_TMU +#undef CONFIG_TMU_CMD_DTT
+#ifdef CONFIG_CMD_NET +#undef CONFIG_CMD_NET +#undef CONFIG_SMC911X +#undef CONFIG_CMD_PXE +#undef CONFIG_MENU +#endif
Why remove net?
+#endif /* __CONFIG_H */
1.9.1
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Regards, SImon
On Mon, 01 Dec 2014 10:30:15 -0700 Simon Glass sjg@chromium.org wrote:
Hi,
On 27 November 2014 at 06:21, Hyungwon Hwang human.hwang@samsung.com wrote:
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Tested-by: Lukasz Majewski l.majewski@samsung.com Acked-by: Lukasz Majewski l.majewski@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com
Changes for v3:
- Remove unnecessary node from DT file
- Remove unnecessary features from config file
- Remove unnecessary macros from board-specific header file
- Fix some trivial typos in comments
Changes for v4:
- Add MMC FIFO buffer's configuration to DT file
- Make CONFIG_OF_CONTROL be set by the target information
- Add basic document to doc/README.odroid-xu3
- Add CONFIG_CMD_EXT4 to config file
- Add environment size and offset to config file
- Add extra default environment to make bootable without
modification
- Remove unnecessary features from config file
Changes for v5:
- Convert /include/ to #include in DT file
Changes for v6:
- Separate out the documentation to new commit
- Remove unnecessary header file inclusions from the board-specific
setup file
- Make the function board_clock_init be declared, only when CONFIG_BOARD_EARLY_INIT_F is defined
Changes for v7:
- Remove OF_CONTROL dependency from !SPL_BUILD
Changes for v8:
- Remove unnecessary properties in DT mmc node
Changes for v9:
- Remove useless variables in the default environment
- Replace the detailed information to the reference to the
documentation
Great to see this series. I wanted to test it earlier but had problems with it not being reliable. I tracked this down to a uSD card (which works fine on other boards but boots reliably only to SPL on XU3).
arch/arm/cpu/armv7/exynos/Kconfig | 5 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 57 +++++++++++++++ board/samsung/odroid-xu3/Kconfig | 12 +++ board/samsung/odroid-xu3/MAINTAINERS | 6 ++ board/samsung/odroid-xu3/Makefile | 7 ++ board/samsung/odroid-xu3/odroid-xu3.c | 122 +++++++++++++++++++++++++++++++ board/samsung/odroid-xu3/setup.h | 95 ++++++++++++++++++++++++ configs/odroid-xu3_defconfig | 4 + include/configs/odroid.h | 5 -- include/configs/odroid_xu3.h | 133 ++++++++++++++++++++++++++++++++++ 11 files changed, 443 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 include/configs/odroid_xu3.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 13dbd95..16c9a0e 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -24,6 +24,10 @@ config TARGET_TRATS2 config TARGET_ODROID bool "Exynos4412 Odroid board"
+config TARGET_ODROID_XU3
bool "Exynos5422 Odroid board"select OF_CONTROLconfig TARGET_ARNDALE bool "Exynos5250 Arndale board" select SUPPORT_SPL @@ -65,6 +69,7 @@ source "board/samsung/universal_c210/Kconfig" source "board/samsung/origen/Kconfig" source "board/samsung/trats2/Kconfig" source "board/samsung/odroid/Kconfig" +source "board/samsung/odroid-xu3/Kconfig" source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e5846ea..a811b1b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -13,7 +13,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ exynos5420-peach-pit.dtb \
exynos5800-peach-pi.dtb
exynos5800-peach-pi.dtb \exynos5422-odroidxu3.dtbIs it 5422 or 45800? Is there any difference really?
Actually the processor in XU3 is Exynos5422. Exynos5800 is a variant of Exynos5422 for Chromebook. You can find the information about it from: http://www.samsung.com/global/business/semiconductor/minisite/Exynos/w/solut...
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644 index 0000000..533d88e --- /dev/null +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -0,0 +1,57 @@ +/*
- Odroid XU3 device tree source
- Copyright (c) 2014 Samsung Electronics Co., Ltd.
http://www.samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+/dts-v1/; +#include "exynos54xx.dtsi"
+/ {
model = "Odroid XU3 based on EXYNOS5422";compatible = "samsung,odroidxu3", "samsung,exynos5";aliases {serial0 = "/serial@12C00000";console = "/serial@12C20000";};memory {device_type = "memory";reg = <0x40000000 0x100000000x50000000 0x100000000x60000000 0x100000000x70000000 0x100000000x80000000 0x100000000x90000000 0x100000000xa0000000 0x100000000xb0000000 0xea00000>;};serial@12C20000 {status="okay";};mmc@12200000 {samsung,bus-width = <8>;samsung,timing = <1 3 3>;fifoth_val = <0x200f0020>;};mmc@12210000 {status = "disabled";};mmc@12220000 {samsung,bus-width = <4>;samsung,timing = <1 2 3>;fifoth_val = <0x200f0020>;};mmc@12230000 {status = "disabled";};+}; diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig new file mode 100644 index 0000000..6159692 --- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3
+config SYS_BOARD
default "odroid-xu3"+config SYS_VENDOR
default "samsung"+config SYS_CONFIG_NAME
default "odroid_xu3"+endif diff --git a/board/samsung/odroid-xu3/MAINTAINERS b/board/samsung/odroid-xu3/MAINTAINERS new file mode 100644 index 0000000..50cf928 --- /dev/null +++ b/board/samsung/odroid-xu3/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID-XU3 BOARD +M: Hyungwon Hwang human.hwang@samsung.com +S: Maintained +F: board/samsung/odroid-xu3/ +F: include/configs/odroid_xu3.h +F: configs/odroid-xu3_defconfig diff --git a/board/samsung/odroid-xu3/Makefile b/board/samsung/odroid-xu3/Makefile new file mode 100644 index 0000000..85ae5c5 --- /dev/null +++ b/board/samsung/odroid-xu3/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := odroid-xu3.o diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..8c54842 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,122 @@ +/*
- Copyright (C) 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include "setup.h"
+DECLARE_GLOBAL_DATA_PTR;
+unsigned int get_board_rev(void) +{
return 0;+}
+int exynos_init(void) +{
return 0;+}
+#ifdef CONFIG_BOARD_EARLY_INIT_F +static int board_clock_init(void) +{
unsigned int set, clr, clr_src_cpu, clr_pll_con0;struct exynos5420_clock *clk = (struct exynos5420_clock *)samsung_get_base_clock();
This stuff needs to move into SPL - if it works then perhaps hardkernel can do this work. It doesn't make sense to set up the clocks in SPL and then again in U-Boot.
At the least this should be commented as a temporary hack, and enable with a CONFIG_EXYNOS_REINIT_CLOCKS option, or something.
OK. As we discussed, I found that it is needless. I will remove it from next version.
/** CMU_CPU clocks src to MPLL* Bit values: 0 ; 1* MUX_APLL_SEL: FIN_PLL ; FOUT_APLL* MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL*//* Set CMU_CPU clocks src to OSCCLK */clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))continue;/* Set APLL to 1200MHz */Why not 1.7GHz?
This function will be removed in whole.
clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |PLL_ENABLE(1);set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))continue;/* Set CMU_CPU clocks src to APLL */set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))continue;clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);clrsetbits_le32(&clk->div_cpu0, clr, set);while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)continue;/* Set MPLL to 800MHz */set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))continue;/* Set CLKMUX_UART src to MPLL */clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) |UART3_SEL(7);
set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) |UART3_SEL(3); +
clrsetbits_le32(&clk->src_peric0, clr, set);/* Set SCLK_UART to 400 MHz (MPLL / 2) */clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |UART3_RATIO(15);set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |UART3_RATIO(1);clrsetbits_le32(&clk->div_peric0, clr, set);while (readl(&clk->div_stat_peric0) &DIV_STAT_PERIC0_CHANGING)
continue;/* Set CLKMUX_MMC src to MPLL */clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);clrsetbits_le32(&clk->src_fsys, clr, set);clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) |MMC2_RATIO(0x3ff);
set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);clrsetbits_le32(&clk->div_fsys1, clr, set);/* Wait for divider ready status */while (readl(&clk->div_stat_fsys1) &DIV_STAT_FSYS1_CHANGING)
continue;return 0;+}
+int exynos_early_init_f(void) +{
return board_clock_init();+} +#endif diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h new file mode 100644 index 0000000..143c189 --- /dev/null +++ b/board/samsung/odroid-xu3/setup.h @@ -0,0 +1,95 @@ +/*
- (C) Copyright 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __ODROID_XU3_SETUP__ +#define __ODROID_XU3_SETUP__
+#define SDIV(x) ((x) & 0x7) +#define PDIV(x) (((x) & 0x3f) << 8) +#define MDIV(x) (((x) & 0x3ff) << 16) +#define FSEL(x) (((x) & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) (((x) & 0x1) << 31)
+/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) ((x) & 0x1) +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
+/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) ((x) & 0x7) +#define CORE_SEL(x) (((x) & 0x7) << 16) +#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) || \
(x) & APLL_SEL(1)|| \
(x) & CORE_SEL(0)|| \
(x) & CORE_SEL(1))+/* CLK_DIV_CPU0 */ +#define ARM_RATIO(x) ((x) & 0x7) +#define CPUD_RATIO(x) (((x) & 0x7) << 4) +#define ATB_RATIO(x) (((x) & 0x7) << 16) +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) +#define APLL_RATIO(x) (((x) & 0x7) << 24) +#define ARM2_RATIO(x) (((x) & 0x7) << 28)
+/* CLK_DIV_STAT_CPU0 */ +#define DIV_CPUD(x) (((x) & 0x1) << 4) +#define DIV_ATB(x) (((x) & 0x1) << 16) +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) +#define DIV_APLL(x) (((x) & 0x1) << 24) +#define DIV_ARM2(x) (((x) & 0x1) << 28)
+#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \
DIV_ATB(DIV_STAT_CHANGING) | \DIV_PCLK_DBG(DIV_STAT_CHANGING) | \DIV_APLL(DIV_STAT_CHANGING) | \DIV_ARM2(DIV_STAT_CHANGING))+/* Set CLK_SRC_PERIC0 */ +#define UART0_SEL(x) (((x) & 0xf) << 4) +#define UART1_SEL(x) (((x) & 0xf) << 8) +#define UART2_SEL(x) (((x) & 0xf) << 12) +#define UART3_SEL(x) (((x) & 0xf) << 16)
+/* Set CLK_DIV_PERIC0 */ +#define UART0_RATIO(x) (((x) & 0xf) << 8) +#define UART1_RATIO(x) (((x) & 0xf) << 12) +#define UART2_RATIO(x) (((x) & 0xf) << 16) +#define UART3_RATIO(x) (((x) & 0xf) << 20)
+/* Set CLK_DIV_STAT_PERIC0 */ +#define DIV_UART0(x) ((x) & 0x1) +#define DIV_UART1(x) (((x) & 0x1) << 4) +#define DIV_UART2(x) (((x) & 0x1) << 8) +#define DIV_UART3(x) (((x) & 0x1) << 12) +#define DIV_UART4(x) (((x) & 0x1) << 16)
+#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
DIV_UART3(DIV_STAT_CHANGING) | \DIV_UART2(DIV_STAT_CHANGING) | \DIV_UART1(DIV_STAT_CHANGING) | \DIV_UART0(DIV_STAT_CHANGING))+/* CLK_SRC_FSYS */ +#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8) +#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12) +#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16)
+/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0x3ff) +#define MMC1_RATIO(x) (((x) & 0x3ff) << 10) +#define MMC2_RATIO(x) (((x) & 0x3ff) << 20)
+#define DIV_MMC0(x) (((x) & 1) << 20) +#define DIV_MMC1(x) (((x) & 1) << 24) +#define DIV_MMC2(x) (((x) & 1) << 28)
+#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
DIV_MMC1(DIV_STAT_CHANGING) | \DIV_MMC2(DIV_STAT_CHANGING))+#endif diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig new file mode 100644 index 0000000..74aa0cf --- /dev/null +++ b/configs/odroid-xu3_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID_XU3=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 807e96b..660b6ae 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -166,11 +166,6 @@ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \
"bootdelay=0\0" \"dfu_alt_system="CONFIG_DFU_ALT \"dfu_alt_info=Please reset the board\0" \"consoleon=set console console=ttySAC1,115200n8; save;reset\0" \
"consoleoff=set console console=ram; save; reset\0" \ "initrdname=uInitrd\0" \ "initrdaddr=42000000\0" \ "fdtaddr=40800000\0"diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h new file mode 100644 index 0000000..1d53653 --- /dev/null +++ b/include/configs/odroid_xu3.h @@ -0,0 +1,133 @@ +/*
- Copyright (C) 2013 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H
+#include "exynos5-common.h"
Should include exynos5420-common.h. If there are things in there that should not be common, then you could add a patch to move them out.
This causes a build warning in I2C.
Yes. I agree with you. I will fix it.
+#define CONFIG_SYS_PROMPT "ODROID-XU3 # " +#define CONFIG_IDENT_STRING " for ODROID-XU3"
+#define CONFIG_BOARD_COMMON
+#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000
+/* select serial console configuration */ +#define CONFIG_SERIAL2 /* use SERIAL 2 */
+#define TZPC_BASE_OFFSET 0x10000
+#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT
+/*
- FIXME: The number of bank is actually 8. But there is no way to
reserver the
- last 16 Mib in the last bank now. So I just excluded the last
bank
- temporally.
- */
+#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_SIZE +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +#define CONFIG_BOOTCOMMAND "run autoboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
+/*
- For details, refer the documentation: doc/README.odroid
+*/ +#ifdef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_EXTRA_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \
"loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart}${kerneladdr} " \
"${kernelname}\0" \"loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart}${initrdaddr} " \
"${initrdname}\0" \"loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart}${fdtaddr} " \
"${fdtfile}\0" \"check_ramdisk=" \"if run loadinitrd; then " \"setenv initrd_addr ${initrdaddr};" \"else " \"setenv initrd_addr -;" \"fi;\0" \"check_dtb=" \"if run loaddtb; then " \"setenv fdt_addr ${fdtaddr};" \"else " \"setenv fdt_addr;" \"fi;\0" \"kernel_args=" \"setenv bootargsroot=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \
" rootwait ${console} ${opts}\0" \"boot_fit=" \"setenv kerneladdr 0x42000000;" \"setenv kernelname Image.itb;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kerneladdr}#${boardname}\0" \"boot_uimg=" \"setenv kerneladdr 0x40007FC0;" \"setenv kernelname uImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0"\
"boot_zimg=" \"setenv kerneladdr 0x40007FC0;" \"setenv kernelname zImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0"\
"autoboot=" \"if test -e mmc 0 Image.itb; then; " \"run boot_fit;" \"elif test -e mmc 0 zImage; then; " \"run boot_zimg;" \"elif test -e mmc 0 uImage; then; " \"run boot_uimg;" \"fi;\0" \"console=" CONFIG_DEFAULT_CONSOLE \"mmcbootdev=0\0" \"mmcbootpart=1\0" \"mmcrootdev=0\0" \"mmcrootpart=2\0" \"bootdelay=0\0" \"dfu_alt_info=Please reset the board\0" \"consoleon=set console console=ttySAC2,115200n8; save;reset\0" \
"consoleoff=set console console=ram; save; reset\0" \"initrdname=uInitrd\0" \"initrdaddr=42000000\0" \"fdtaddr=40800000\0"+/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ +#undef CONFIG_EXYNOS_TMU +#undef CONFIG_TMU_CMD_DTT
+#ifdef CONFIG_CMD_NET +#undef CONFIG_CMD_NET +#undef CONFIG_SMC911X +#undef CONFIG_CMD_PXE +#undef CONFIG_MENU +#endif
Why remove net?
I removed it to make u-boot binary smaller. I will test it again after remove these lines. If the u-boot binary is small enough, I will remove them. But if it fails, I will remain them until the size issue is resovled.
+#endif /* __CONFIG_H */
1.9.1
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Regards, SImon
This patch adds documentation for Odroid-XU3. This documentation is based on that of Odroid (doc/README-odroid) made by Przemyslaw Marczak. The documentation includes basic information about boot media layout, environment, partition layout, and the instruction to burn the u-boot image to boot media.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Tested-by: Lukasz Majewski l.majewski@samsung.com Acked-by: Lukasz Majewski l.majewski@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com --- Changes for v6: - Newly added
Changes for v7: - Fix several errata in the documentation
Changes for v8: - None
Changes for v9: - Add the new contents to the documentation of Odroid X2/U2, instead of making new document for Odorid XU3
doc/README.odroid | 46 ++++++++++++++++++++++++++++++---------------- 1 file changed, 30 insertions(+), 16 deletions(-)
diff --git a/doc/README.odroid b/doc/README.odroid index 25b962b..99693d4 100644 --- a/doc/README.odroid +++ b/doc/README.odroid @@ -1,28 +1,39 @@ - U-boot for Odroid X2/U3 + U-boot for Odroid X2/U3/XU3 ========================
1. Summary ========== -This is a quick instruction for setup Odroid boards based on Exynos4412. -Board config: odroid_config +This is a quick instruction for setup Odroid boards. +Board config: odroid_config for X2/U3 +Board config: odroid-xu3_config for XU3
2. Supported devices ==================== -This U-BOOT config can be used on two boards: +This U-BOOT config can be used on three boards: - Odroid U3 - Odroid X2 with CPU Exynos 4412 rev 2.0 and 2GB of RAM +- Odroid XU3 +with CPU Exynos5422 and 2GB of RAM
3. Boot sequence ================ iROM->BL1->(BL2 + TrustZone)->U-BOOT
-This version of U-BOOT doesn't implement SPL but it is required(BL2) -and can be found in "boot.tar.gz" from here: +This version of U-BOOT doesn't implement SPL. So, BL1, BL2, and TrustZone +binaries are needed to boot up. + +<< X2/U3 >> +It can be found in "boot.tar.gz" from here: http://dev.odroid.com/projects/4412boot/wiki/FrontPage?action=download&v... or here: http://odroid.in/guides/ubuntu-lfs/boot.tar.gz
+<< XU3 >> +It can be downloaded from: +https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardker... + + 4. Boot media layout ==================== The table below shows SD/eMMC cards layout for U-boot. @@ -35,18 +46,20 @@ The block offset is starting from 0 and the block size is 512B. | Bl2 | 31 | 30 | 1 (boot) | | U-boot | 63 | 62 | 1 (boot) | | Tzsw | 2111 | 2110 | 1 (boot) | -| Uboot Env | 2500 | 2500 | 0 (user) | +| Uboot Env | 2560 | 2560 | 0 (user) | -------------------------------------
5. Prepare the SD boot card - with SD card reader ================================================= To prepare bootable media you need boot binaries provided by hardkernel. -File "boot.tar.gz" (link in point 3.) contains: -- E4412_S.bl1.HardKernel.bin -- E4412_S.tzsw.signed.bin -- bl2.signed.bin +From the downloaded files, You can find: +- bl1.bin +- tzsw.bin +- bl2.bin - sd_fusing.sh - u-boot.bin +(The file names can be slightly different, but you can distinguish what they are +without problem)
This is all you need to boot this board. But if you want to use your custom u-boot then you need to change u-boot.bin with your own u-boot binary* @@ -56,7 +69,7 @@ and run the script "sd_fusing.sh" - this script is valid only for SD card. The proper binary file of current U-boot is u-boot-dtb.bin.
quick steps for Linux: -- extract boot.tar.gz +- Download all files from the link at point 3 and extract it if needed. - put any SD card into the SD reader - check the device with "dmesg" - run ./sd_fusing.sh /dev/sdX - where X is SD card device (but not a partition) @@ -66,7 +79,7 @@ Check if Hardkernel U-boot is booting, and next do the same with your U-boot. with a eMMC card reader (boot from eMMC card slot) ===================================================== To boot the device from the eMMC slot you should use a special card reader -which supports eMMC partiion switch. All of the boot binaries are stored +which supports eMMC partition switch. All of the boot binaries are stored on the eMMC boot partition which is normally hidden.
The "sd_fusing.sh" script can be used after updating offsets of binaries @@ -81,8 +94,8 @@ But then the device can boot only from the SD card slot.
8. Prepare the boot media using Hardkernel U-boot ================================================= -You can update the U-boot to the custom one if you have an working bootloader -delivered with the board on a eMMC/SD card. Then follow the steps: +You can update the U-boot to the custom one if you have a working bootloader +delivered with the board on the eMMC/SD card. Then follow the steps: - install the android fastboot tool - connect a micro usb cable to the board - on the U-boot prompt, run command: fastboot (as a root) @@ -91,7 +104,7 @@ delivered with the board on a eMMC/SD card. Then follow the steps:
9. Partition layout ==================== -Default U-boot environment is setup for fixed partiion layout. +Default U-boot environment is setup for fixed partition layout.
Partition table: MSDOS. Disk layout and files as listed in the table below. ----- ------ ------ ------ -------- --------------------------------- @@ -106,6 +119,7 @@ Partition table: MSDOS. Disk layout and files as listed in the table below. Supported fdt files are: - exynos4412-odroidx2.dtb - exynos4412-odroidu3.dtb +- exynos5422-odroidxu3.dtb
Supported kernel files are: - Image.itb
On Thu, 2014-11-27 at 22:21 +0900, Hyungwon Hwang wrote:
This patch adds documentation for Odroid-XU3. This documentation is based on that of Odroid (doc/README-odroid) made by Przemyslaw Marczak. The documentation includes basic information about boot media layout, environment, partition layout, and the instruction to burn the u-boot image to boot media.
- Boot media layout
==================== The table below shows SD/eMMC cards layout for U-boot. @@ -35,18 +46,20 @@ The block offset is starting from 0 and the block size is 512B. | Bl2 | 31 | 30 | 1 (boot) | | U-boot | 63 | 62 | 1 (boot) | | Tzsw | 2111 | 2110 | 1 (boot) | -| Uboot Env | 2500 | 2500 | 0 (user) |
+| Uboot Env | 2560 | 2560 | 0 (user) |
Where the previous values incorrect? Also this doesn't seem to match the hardkerel script which has:
signed_bl1_position=1 bl2_position=31 uboot_position=63 tzsw_position=719 env_position=1231
for the various locations.. Which also explains the limit 335872 bytes in your initial mail.. Awkward one though. Wonder if that's an SoC issue or something hardkernel could fix by having a different bl1/bl2?
On Thu, 27 Nov 2014 15:33:05 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
On Thu, 2014-11-27 at 22:21 +0900, Hyungwon Hwang wrote:
This patch adds documentation for Odroid-XU3. This documentation is based on that of Odroid (doc/README-odroid) made by Przemyslaw Marczak. The documentation includes basic information about boot media layout, environment, partition layout, and the instruction to burn the u-boot image to boot media.
- Boot media layout
==================== The table below shows SD/eMMC cards layout for U-boot. @@ -35,18 +46,20 @@ The block offset is starting from 0 and the block size is 512B. | Bl2 | 31 | 30 | 1 (boot) | | U-boot | 63 | 62 | 1 (boot) | | Tzsw | 2111 | 2110 | 1 (boot) | -| Uboot Env | 2500 | 2500 | 0 (user) |
+| Uboot Env | 2560 | 2560 | 0 (user) |
Where the previous values incorrect? Also this doesn't seem to match the hardkerel script which has:
This boot media layout is for x2/u3. I will update it in next version.
But the env offset is #define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ as you can see in odroid.h and odroid_xu3.h.
CONFIG_ENV_OFFSET / 512 = 2560, not 2500.
signed_bl1_position=1 bl2_position=31 uboot_position=63 tzsw_position=719 env_position=1231
for the various locations.. Which also explains the limit 335872 bytes in your initial mail.. Awkward one though. Wonder if that's an SoC issue or something hardkernel could fix by having a different bl1/bl2?
(719 - 63) * 512 = 335876 bytes. The limitation is needed not to overwrite tzsw.
Are you saying that the limitation can be removed? Yes, with different bl1/bl2. But I do not think that another bl1/bl2 will be released to relieve the limitation.
On Fri, 2014-11-28 at 13:45 +0900, Hyungwon Hwang wrote:
On Thu, 27 Nov 2014 15:33:05 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
signed_bl1_position=1 bl2_position=31 uboot_position=63 tzsw_position=719 env_position=1231
for the various locations.. Which also explains the limit 335872 bytes in your initial mail.. Awkward one though. Wonder if that's an SoC issue or something hardkernel could fix by having a different bl1/bl2?
(719 - 63) * 512 = 335876 bytes. The limitation is needed not to overwrite tzsw.
Are you saying that the limitation can be removed? Yes, with different bl1/bl2. But I do not think that another bl1/bl2 will be released to relieve the limitation.
It was a something i was wondering. After send this e-mail i had a chat with Mauro Ribeiro on #linux-exynos. He indicate that the BL2 determines the u-boot load location and that it's an u-boot SPL build from their u-boot branch. Also he indicated that he would be happy to sign a modified SPL build which e.g. loads u-boot from behind the TZSW.
You can find the IRC log here: http://irclog.whitequark.org/linux-exynos/2014-11-27
I have yet to take him up on that offer though, but it sounds like a good way forward. The current layout really isn't practical.
Hi Sjoerd,
On Fri, 2014-11-28 at 13:45 +0900, Hyungwon Hwang wrote:
On Thu, 27 Nov 2014 15:33:05 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
signed_bl1_position=1 bl2_position=31 uboot_position=63 tzsw_position=719 env_position=1231
for the various locations.. Which also explains the limit 335872 bytes in your initial mail.. Awkward one though. Wonder if that's an SoC issue or something hardkernel could fix by having a different bl1/bl2?
(719 - 63) * 512 = 335876 bytes. The limitation is needed not to overwrite tzsw.
Are you saying that the limitation can be removed? Yes, with different bl1/bl2. But I do not think that another bl1/bl2 will be released to relieve the limitation.
It was a something i was wondering. After send this e-mail i had a chat with Mauro Ribeiro on #linux-exynos. He indicate that the BL2 determines the u-boot load location and that it's an u-boot SPL build from their u-boot branch. Also he indicated that he would be happy to sign a modified SPL build which e.g. loads u-boot from behind the TZSW.
You can find the IRC log here: http://irclog.whitequark.org/linux-exynos/2014-11-27
I have yet to take him up on that offer though, but it sounds like a good way forward. The current layout really isn't practical.
It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board.
Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the "normal" user do things.
He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel.
For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB.
It is challenging but for sure doable.
Best regards, Lukasz Majewski
On Fri, 2014-11-28 at 09:39 +0100, Lukasz Majewski wrote:
Hi Sjoerd,
On Fri, 2014-11-28 at 13:45 +0900, Hyungwon Hwang wrote:
On Thu, 27 Nov 2014 15:33:05 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
signed_bl1_position=1 bl2_position=31 uboot_position=63 tzsw_position=719 env_position=1231
for the various locations.. Which also explains the limit 335872 bytes in your initial mail.. Awkward one though. Wonder if that's an SoC issue or something hardkernel could fix by having a different bl1/bl2?
(719 - 63) * 512 = 335876 bytes. The limitation is needed not to overwrite tzsw.
Are you saying that the limitation can be removed? Yes, with different bl1/bl2. But I do not think that another bl1/bl2 will be released to relieve the limitation.
It was a something i was wondering. After send this e-mail i had a chat with Mauro Ribeiro on #linux-exynos. He indicate that the BL2 determines the u-boot load location and that it's an u-boot SPL build from their u-boot branch. Also he indicated that he would be happy to sign a modified SPL build which e.g. loads u-boot from behind the TZSW.
You can find the IRC log here: http://irclog.whitequark.org/linux-exynos/2014-11-27
I have yet to take him up on that offer though, but it sounds like a good way forward. The current layout really isn't practical.
It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board.
Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the "normal" user do things.
He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel.
For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB.
I don't see a big issue with telling the "normal" user[0] to replace both the BL2 and u-boot itself. If the hardkernel folks indeed do sign the BL2 for us, i'm more then happy to make that publically available.
0: Do normal users replace u-boot?
Hi Sjoerd,
On Fri, 2014-11-28 at 09:39 +0100, Lukasz Majewski wrote:
Hi Sjoerd,
On Fri, 2014-11-28 at 13:45 +0900, Hyungwon Hwang wrote:
On Thu, 27 Nov 2014 15:33:05 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
signed_bl1_position=1 bl2_position=31 uboot_position=63 tzsw_position=719 env_position=1231
for the various locations.. Which also explains the limit 335872 bytes in your initial mail.. Awkward one though. Wonder if that's an SoC issue or something hardkernel could fix by having a different bl1/bl2?
(719 - 63) * 512 = 335876 bytes. The limitation is needed not to overwrite tzsw.
Are you saying that the limitation can be removed? Yes, with different bl1/bl2. But I do not think that another bl1/bl2 will be released to relieve the limitation.
It was a something i was wondering. After send this e-mail i had a chat with Mauro Ribeiro on #linux-exynos. He indicate that the BL2 determines the u-boot load location and that it's an u-boot SPL build from their u-boot branch. Also he indicated that he would be happy to sign a modified SPL build which e.g. loads u-boot from behind the TZSW.
You can find the IRC log here: http://irclog.whitequark.org/linux-exynos/2014-11-27
I have yet to take him up on that offer though, but it sounds like a good way forward. The current layout really isn't practical.
It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board.
Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the "normal" user do things.
He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel.
For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB.
I don't see a big issue with telling the "normal" user[0] to replace both the BL2 and u-boot itself. If the hardkernel folks indeed do sign the BL2 for us, i'm more then happy to make that publically available.
I just would like to avoid having two incompatible BL2s floating around.
Does your use case require u-boot size larger than 328 KiB? Hyungwon has managed to provide functional one with size less than 328 KiB.
Another issue is the exact SPL source code from which you would like to build BL2 with modified layout.
Do you plan to use HardKernel's source code and only modify the layout or use SPL from cutting edge mainline?
Please note that even for tests BL2 must be signed by HardKernel to cooperate with Samsung's proprietary BL1.
0: Do normal users replace u-boot?
I know a few developers who did this because they needed new features missing in HardKernel's version (like UMS support).
Best regards, Lukasz Majewski
On Fri, 2014-11-28 at 13:47 +0100, Lukasz Majewski wrote:
Hi Sjoerd,
On Fri, 2014-11-28 at 09:39 +0100, Lukasz Majewski wrote:
Hi Sjoerd,
On Fri, 2014-11-28 at 13:45 +0900, Hyungwon Hwang wrote:
On Thu, 27 Nov 2014 15:33:05 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
signed_bl1_position=1 bl2_position=31 uboot_position=63 tzsw_position=719 env_position=1231
for the various locations.. Which also explains the limit 335872 bytes in your initial mail.. Awkward one though. Wonder if that's an SoC issue or something hardkernel could fix by having a different bl1/bl2?
(719 - 63) * 512 = 335876 bytes. The limitation is needed not to overwrite tzsw.
Are you saying that the limitation can be removed? Yes, with different bl1/bl2. But I do not think that another bl1/bl2 will be released to relieve the limitation.
It was a something i was wondering. After send this e-mail i had a chat with Mauro Ribeiro on #linux-exynos. He indicate that the BL2 determines the u-boot load location and that it's an u-boot SPL build from their u-boot branch. Also he indicated that he would be happy to sign a modified SPL build which e.g. loads u-boot from behind the TZSW.
You can find the IRC log here: http://irclog.whitequark.org/linux-exynos/2014-11-27
I have yet to take him up on that offer though, but it sounds like a good way forward. The current layout really isn't practical.
It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board.
Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the "normal" user do things.
He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel.
For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB.
I don't see a big issue with telling the "normal" user[0] to replace both the BL2 and u-boot itself. If the hardkernel folks indeed do sign the BL2 for us, i'm more then happy to make that publically available.
I just would like to avoid having two incompatible BL2s floating around.
Does your use case require u-boot size larger than 328 KiB? Hyungwon has managed to provide functional one with size less than 328 KiB.
Even with that functionality it's incredibly on the edge, if build with gcc-4.7 it's too big. gcc-4.9 manages to make it *just* small enough. And that's without support for USB networking, which is pretty useful.
I've done some quick hacks locally to add USB/tftp boot support and re-use exynos5-dt-common.h/exynos5420-common.h, which already resulted in it growing to ~440kb.
Another issue is the exact SPL source code from which you would like to build BL2 with modified layout.
Do you plan to use HardKernel's source code and only modify the layout or use SPL from cutting edge mainline?
Please note that even for tests BL2 must be signed by HardKernel to cooperate with Samsung's proprietary BL1.
Yeah, I was planning to just use the SPL from Hardkernels source code and modify the layout so the behaviour SPL only differ in where they load u-boot from not in other behaviour.
0: Do normal users replace u-boot?
I know a few developers who did this because they needed new features missing in HardKernel's version (like UMS support).
That was a bit tongue in cheek. I'm currently chainloading my u-boot (which is too big to boot from SD) over tftp from hardkernels u-boot, so that i can tftp boot a kernel + initramfs with the new version.. As hardkernels u-boot seems to corrupt the initramfs (fun!)..
But apart from that anecdote, the main reason developers replace u-boot is that the vendors one is missing features. So ideally the default build of upstream u-boot should be feature-packed, which means the size gets bigger, which means this limitation in itself is quite annoying again.
Hello Lukasz,
On Fri, Nov 28, 2014 at 9:39 AM, Lukasz Majewski l.majewski@majess.pl wrote:
I have yet to take him up on that offer though, but it sounds like a good way forward. The current layout really isn't practical.
It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board.
Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the "normal" user do things.
He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel.
I agree with Sjoed that normal users don't replace the low-level components that are provided by the board vendor.
After all you can boot a mainline kernel using the vendor u-boot, just append the DTB and create a uImage. The practical reason why someone would want to replace the vendor u-boot is to have more features but is very hard to do if there is a constraint in the maximum u-boot image size (even harder if the maximum is such small like in the XU3).
For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB.
It is challenging but for sure doable.
It is doable but I don't see why the default BL2 _must_ be used.
A user that wants to replace the kernel or u-boot is already tech-savy and can for sure replace the BL2 as well if it's publicly available. Maybe hardkernel folks can even make the modified BL2 available on their website and the link added in the comment explaining the layout?
Also, it is an artificial constraint after all and can be easily modified. In fact I think we should push hardkernel to change that layout by default and use a BL2/SPL that has more sensible size for the u-boot binary even if they don't need it for their vendor u-boot which seems to be quite small.
Best regards, Lukasz Majewski
Best regards, Javier
Hello Javier,
Hello Lukasz,
On Fri, Nov 28, 2014 at 9:39 AM, Lukasz Majewski l.majewski@majess.pl wrote:
I have yet to take him up on that offer though, but it sounds like a good way forward. The current layout really isn't practical.
It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board.
Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the "normal" user do things.
He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel.
I agree with Sjoed that normal users don't replace the low-level components that are provided by the board vendor.
After all you can boot a mainline kernel using the vendor u-boot, just append the DTB and create a uImage. The practical reason why someone would want to replace the vendor u-boot is to have more features but is very hard to do if there is a constraint in the maximum u-boot image size (even harder if the maximum is such small like in the XU3).
I agree that 328 KiB size for u-boot is a constraint. I don't know HardKernel's justification for this.
For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB.
It is challenging but for sure doable.
It is doable but I don't see why the default BL2 _must_ be used.
For practical/pragmatic reasons:
1. It is difficult to have signed BL2 - each time we need to ask HardKernel for signing it. It is impractical and hampers usage of mainline SPL (BL2) with XU3.
2. All the documentation on the HardKernel wiki site refers to the default BL2.
3. We will have "new" BL2, which source code is based on 2012.07 mainline u-boot.
4. Two BL2 binaries - IMHO will hurt (i.e. brick) some device sooner or latter.
A user that wants to replace the kernel or u-boot is already tech-savy and can for sure replace the BL2 as well if it's publicly available.
Sorry, but I'm a bit sceptical about updating such low level code. Bad things do happen.
Maybe hardkernel folks can even make the modified BL2 available on their website and the link added in the comment explaining the layout?
We would then require HardKernel to:
1. Provide updated BL2.img 2. Update their wiki to reflect the new BL2.
Also, it is an artificial constraint after all and can be easily modified. In fact I think we should push hardkernel to change that layout by default and use a BL2/SPL that has more sensible size for the u-boot binary even if they don't need it for their vendor u-boot which seems to be quite small.
I totally agree.
I'd like to propose a following plan:
1. Accept Hyungwon's patches to have XU3 u-boot < 328 KiB (with link to default BL2) to have XU3 support in place (and treat it as a starting point)
2. If u-boot's size less than 328 KiB is _really_ a problem to somebody then ask hardkernel to change BL2 or: - modify their sources to change the layout (I regard this as a "quick hack" solution) - with a lot of pain develop BL2/SPL (by whom?) which base on newest mainline (then for each test hardkernel must sign the binary).
Best regards, Lukasz Majewski
Best regards, Javier
Best regards, Lukasz Majewski
On Fri, 2014-11-28 at 14:46 +0100, Lukasz Majewski wrote:
Hello Javier,
Hello Lukasz,
On Fri, Nov 28, 2014 at 9:39 AM, Lukasz Majewski l.majewski@majess.pl wrote:
I'd like to propose a following plan:
- Accept Hyungwon's patches to have XU3 u-boot < 328 KiB (with link to
default BL2) to have XU3 support in place (and treat it as a starting point)
Oh, i never said this is a blocker for his patches. So yeah, ofcourse, lets polish these further so they can land :)
On Fri, 28 Nov 2014 16:06:54 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
On Fri, 2014-11-28 at 14:46 +0100, Lukasz Majewski wrote:
Hello Javier,
Hello Lukasz,
On Fri, Nov 28, 2014 at 9:39 AM, Lukasz Majewski l.majewski@majess.pl wrote:
I'd like to propose a following plan:
- Accept Hyungwon's patches to have XU3 u-boot < 328 KiB (with
link to default BL2) to have XU3 support in place (and treat it as a starting point)
Oh, i never said this is a blocker for his patches. So yeah, ofcourse, lets polish these further so they can land :)
+1 :-)
Best regards, Lukasz Majewski
Hi,
On 28 November 2014 at 06:46, Lukasz Majewski l.majewski@majess.pl wrote:
Hello Javier,
Hello Lukasz,
On Fri, Nov 28, 2014 at 9:39 AM, Lukasz Majewski l.majewski@majess.pl wrote:
I have yet to take him up on that offer though, but it sounds like a good way forward. The current layout really isn't practical.
It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board.
Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the "normal" user do things.
He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel.
I agree with Sjoed that normal users don't replace the low-level components that are provided by the board vendor.
After all you can boot a mainline kernel using the vendor u-boot, just append the DTB and create a uImage. The practical reason why someone would want to replace the vendor u-boot is to have more features but is very hard to do if there is a constraint in the maximum u-boot image size (even harder if the maximum is such small like in the XU3).
I agree that 328 KiB size for u-boot is a constraint. I don't know HardKernel's justification for this.
For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB.
It is challenging but for sure doable.
It is doable but I don't see why the default BL2 _must_ be used.
For practical/pragmatic reasons:
- It is difficult to have signed BL2 - each time we need to ask
HardKernel for signing it. It is impractical and hampers usage of mainline SPL (BL2) with XU3.
- All the documentation on the HardKernel wiki site refers to the
default BL2.
- We will have "new" BL2, which source code is based on 2012.07
mainline u-boot.
- Two BL2 binaries - IMHO will hurt (i.e. brick) some device sooner
or latter.
A user that wants to replace the kernel or u-boot is already tech-savy and can for sure replace the BL2 as well if it's publicly available.
Sorry, but I'm a bit sceptical about updating such low level code. Bad things do happen.
Maybe hardkernel folks can even make the modified BL2 available on their website and the link added in the comment explaining the layout?
We would then require HardKernel to:
- Provide updated BL2.img
- Update their wiki to reflect the new BL2.
Also, it is an artificial constraint after all and can be easily modified. In fact I think we should push hardkernel to change that layout by default and use a BL2/SPL that has more sensible size for the u-boot binary even if they don't need it for their vendor u-boot which seems to be quite small.
I totally agree.
I'd like to propose a following plan:
- Accept Hyungwon's patches to have XU3 u-boot < 328 KiB (with link to
default BL2) to have XU3 support in place (and treat it as a starting point)
- If u-boot's size less than 328 KiB is _really_ a problem to somebody
then ask hardkernel to change BL2 or: - modify their sources to change the layout (I regard this as a "quick hack" solution) - with a lot of pain develop BL2/SPL (by whom?) which base on newest mainline (then for each test hardkernel must sign the binary).
My 2p worth...
The current Hardkernel BL1 looks broken to me - it is just too old. While it is shipped with the board if you get an eMMC, the main way people will get this is by downloading it from their site. So why not download something different?
Re the plan, I think 1 is fine so long as it is protected by a big ugly hack CONFIG and we can turn it off soon and revert the code.
For 2, the size issue is one problem, but the clock code in U-Boot is another IMO. We should try to get both resolved. Maybe it is possible to use the peach-pit BL2 and get hardkernel to test it and sign it? Then people will download that one instead.
is there a contact at hardkernel on the mailing list?
Regards, Simon
Hi Simon,
Hi,
On 28 November 2014 at 06:46, Lukasz Majewski l.majewski@majess.pl wrote:
Hello Javier,
Hello Lukasz,
On Fri, Nov 28, 2014 at 9:39 AM, Lukasz Majewski l.majewski@majess.pl wrote:
I have yet to take him up on that offer though, but it sounds like a good way forward. The current layout really isn't practical.
It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board.
Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the "normal" user do things.
He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel.
I agree with Sjoed that normal users don't replace the low-level components that are provided by the board vendor.
After all you can boot a mainline kernel using the vendor u-boot, just append the DTB and create a uImage. The practical reason why someone would want to replace the vendor u-boot is to have more features but is very hard to do if there is a constraint in the maximum u-boot image size (even harder if the maximum is such small like in the XU3).
I agree that 328 KiB size for u-boot is a constraint. I don't know HardKernel's justification for this.
For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB.
It is challenging but for sure doable.
It is doable but I don't see why the default BL2 _must_ be used.
For practical/pragmatic reasons:
- It is difficult to have signed BL2 - each time we need to ask
HardKernel for signing it. It is impractical and hampers usage of mainline SPL (BL2) with XU3.
- All the documentation on the HardKernel wiki site refers to the
default BL2.
- We will have "new" BL2, which source code is based on 2012.07
mainline u-boot.
- Two BL2 binaries - IMHO will hurt (i.e. brick) some device sooner
or latter.
A user that wants to replace the kernel or u-boot is already tech-savy and can for sure replace the BL2 as well if it's publicly available.
Sorry, but I'm a bit sceptical about updating such low level code. Bad things do happen.
Maybe hardkernel folks can even make the modified BL2 available on their website and the link added in the comment explaining the layout?
We would then require HardKernel to:
- Provide updated BL2.img
- Update their wiki to reflect the new BL2.
Also, it is an artificial constraint after all and can be easily modified. In fact I think we should push hardkernel to change that layout by default and use a BL2/SPL that has more sensible size for the u-boot binary even if they don't need it for their vendor u-boot which seems to be quite small.
I totally agree.
I'd like to propose a following plan:
- Accept Hyungwon's patches to have XU3 u-boot < 328 KiB (with
link to default BL2) to have XU3 support in place (and treat it as a starting point)
- If u-boot's size less than 328 KiB is _really_ a problem to
somebody then ask hardkernel to change BL2 or: - modify their sources to change the layout (I regard this as a "quick hack" solution) - with a lot of pain develop BL2/SPL (by whom?) which base on newest mainline (then for each test hardkernel must sign the binary).
My 2p worth...
The current Hardkernel BL1 looks broken to me - it is just too old.
+1
While it is shipped with the board if you get an eMMC, the main way people will get this is by downloading it from their site. So why not download something different?
As far as I remember U3 and probably XU3 in their README only points for HardKernel's site to grab BL1 and BL2. We don't plan to include their binaries to u-boot repository.
Re the plan, I think 1 is fine so long as it is protected by a big ugly hack CONFIG and we can turn it off soon and revert the code.
Hyungwon's patches only touch u-boot and rely (temporary I hope) on BL1 and BL2/SPL from Hardkernel.
For 2, the size issue is one problem, but the clock code in U-Boot is another IMO. We should try to get both resolved. Maybe it is possible to use the peach-pit BL2 and get hardkernel to test it and sign it?
I guess that SPL from peach-pit should be tunable to work with XU3 (in a finite number of iterations including signing from HardKernel).
As it is based on recent u-boot it should be easy to produce BL2/SPL only for XU3 (if needed).
Then people will download that one instead.
is there a contact at hardkernel on the mailing list?
As fair as I know no.
I was posting questions on their forum. Maybe it is a right place to ask for contact point? As fair as I remember they were willing to sign SPL/BL2 when sent to them.
Regards, Simon
Best regards, Lukasz Majewski
Hello Simon, Lukasz,
On Tue, Dec 2, 2014 at 2:29 PM, Lukasz Majewski l.majewski@majess.pl wrote:
Hi Simon,
Hi,
On 28 November 2014 at 06:46, Lukasz Majewski l.majewski@majess.pl wrote:
Hello Javier,
Hello Lukasz,
On Fri, Nov 28, 2014 at 9:39 AM, Lukasz Majewski l.majewski@majess.pl wrote:
I have yet to take him up on that offer though, but it sounds like a good way forward. The current layout really isn't practical.
It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board.
Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the "normal" user do things.
He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel.
I agree with Sjoed that normal users don't replace the low-level components that are provided by the board vendor.
After all you can boot a mainline kernel using the vendor u-boot, just append the DTB and create a uImage. The practical reason why someone would want to replace the vendor u-boot is to have more features but is very hard to do if there is a constraint in the maximum u-boot image size (even harder if the maximum is such small like in the XU3).
I agree that 328 KiB size for u-boot is a constraint. I don't know HardKernel's justification for this.
For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB.
It is challenging but for sure doable.
It is doable but I don't see why the default BL2 _must_ be used.
For practical/pragmatic reasons:
- It is difficult to have signed BL2 - each time we need to ask
HardKernel for signing it. It is impractical and hampers usage of mainline SPL (BL2) with XU3.
- All the documentation on the HardKernel wiki site refers to the
default BL2.
- We will have "new" BL2, which source code is based on 2012.07
mainline u-boot.
- Two BL2 binaries - IMHO will hurt (i.e. brick) some device sooner
or latter.
A user that wants to replace the kernel or u-boot is already tech-savy and can for sure replace the BL2 as well if it's publicly available.
Sorry, but I'm a bit sceptical about updating such low level code. Bad things do happen.
Maybe hardkernel folks can even make the modified BL2 available on their website and the link added in the comment explaining the layout?
We would then require HardKernel to:
- Provide updated BL2.img
- Update their wiki to reflect the new BL2.
Also, it is an artificial constraint after all and can be easily modified. In fact I think we should push hardkernel to change that layout by default and use a BL2/SPL that has more sensible size for the u-boot binary even if they don't need it for their vendor u-boot which seems to be quite small.
I totally agree.
I'd like to propose a following plan:
- Accept Hyungwon's patches to have XU3 u-boot < 328 KiB (with
link to default BL2) to have XU3 support in place (and treat it as a starting point)
- If u-boot's size less than 328 KiB is _really_ a problem to
somebody then ask hardkernel to change BL2 or: - modify their sources to change the layout (I regard this as a "quick hack" solution) - with a lot of pain develop BL2/SPL (by whom?) which base on newest mainline (then for each test hardkernel must sign the binary).
My 2p worth...
The current Hardkernel BL1 looks broken to me - it is just too old.
+1
While it is shipped with the board if you get an eMMC, the main way people will get this is by downloading it from their site. So why not download something different?
As far as I remember U3 and probably XU3 in their README only points for HardKernel's site to grab BL1 and BL2. We don't plan to include their binaries to u-boot repository.
Re the plan, I think 1 is fine so long as it is protected by a big ugly hack CONFIG and we can turn it off soon and revert the code.
Hyungwon's patches only touch u-boot and rely (temporary I hope) on BL1 and BL2/SPL from Hardkernel.
For 2, the size issue is one problem, but the clock code in U-Boot is another IMO. We should try to get both resolved. Maybe it is possible to use the peach-pit BL2 and get hardkernel to test it and sign it?
I guess that SPL from peach-pit should be tunable to work with XU3 (in a finite number of iterations including signing from HardKernel).
As it is based on recent u-boot it should be easy to produce BL2/SPL only for XU3 (if needed).
Then people will download that one instead.
is there a contact at hardkernel on the mailing list?
As fair as I know no.
I was posting questions on their forum. Maybe it is a right place to ask for contact point? As fair as I remember they were willing to sign SPL/BL2 when sent to them.
I have gotten a BL2 signed (based of their repository) which allows a bigger U-Boot for testing, and it works. I have currently requested another signed BL2 which lets one use a 1MB U-Boot image which should be adequate. This is in the works. I do not work for hardkernel but I do have a working relationship with them. From the looks of it they are more than willing to accomodate this BL2 change. I can take this action point of getting this BL2 and its related paraphernalia hosted on their website once they are OK with its testing.
Regards - Suriyan
Regards, Simon
Best regards, Lukasz Majewski
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Lukasz Majewski l.majewski@majess.pl writes:
[...]
On 28 November 2014 at 06:46, Lukasz Majewski l.majewski@majess.pl wrote:
Hello Javier,
Hello Lukasz,
On Fri, Nov 28, 2014 at 9:39 AM, Lukasz Majewski l.majewski@majess.pl wrote:
I have yet to take him up on that offer though, but it sounds like a good way forward. The current layout really isn't practical.
It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board.
Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the "normal" user do things.
He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel.
I agree with Sjoed that normal users don't replace the low-level components that are provided by the board vendor.
After all you can boot a mainline kernel using the vendor u-boot, just append the DTB and create a uImage. The practical reason why someone would want to replace the vendor u-boot is to have more features but is very hard to do if there is a constraint in the maximum u-boot image size (even harder if the maximum is such small like in the XU3).
I agree that 328 KiB size for u-boot is a constraint. I don't know HardKernel's justification for this.
For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB.
It is challenging but for sure doable.
It is doable but I don't see why the default BL2 _must_ be used.
For practical/pragmatic reasons:
- It is difficult to have signed BL2 - each time we need to ask
HardKernel for signing it. It is impractical and hampers usage of mainline SPL (BL2) with XU3.
- All the documentation on the HardKernel wiki site refers to the
default BL2.
- We will have "new" BL2, which source code is based on 2012.07
mainline u-boot.
- Two BL2 binaries - IMHO will hurt (i.e. brick) some device sooner
or latter.
A user that wants to replace the kernel or u-boot is already tech-savy and can for sure replace the BL2 as well if it's publicly available.
Sorry, but I'm a bit sceptical about updating such low level code. Bad things do happen.
Maybe hardkernel folks can even make the modified BL2 available on their website and the link added in the comment explaining the layout?
We would then require HardKernel to:
- Provide updated BL2.img
- Update their wiki to reflect the new BL2.
Also, it is an artificial constraint after all and can be easily modified. In fact I think we should push hardkernel to change that layout by default and use a BL2/SPL that has more sensible size for the u-boot binary even if they don't need it for their vendor u-boot which seems to be quite small.
I totally agree.
I'd like to propose a following plan:
- Accept Hyungwon's patches to have XU3 u-boot < 328 KiB (with
link to default BL2) to have XU3 support in place (and treat it as a starting point)
- If u-boot's size less than 328 KiB is _really_ a problem to
somebody then ask hardkernel to change BL2 or: - modify their sources to change the layout (I regard this as a "quick hack" solution) - with a lot of pain develop BL2/SPL (by whom?) which base on newest mainline (then for each test hardkernel must sign the binary).
My 2p worth...
The current Hardkernel BL1 looks broken to me - it is just too old.
+1
FWIW, the XU3 firmware is broken in other ways as well which have a major impact on power management.
First, with mainline kernels using MCPM, only 6 of 8 CPUs come online. However, even with that fixed[1], it turns out that the kernel can't properly manage CCI due to secure firmware[2], which means that MCPM (multi-cluster power management) can't work, and thus the low-power cluster-idle states can't work, the big.LITTLE switcher cannot work, and the ongoing work on energy-aware scheduling will not be useful on this platform.
Anyone know what are the chances of getting a non-secure version of the firmware for this platform. The Samsung Chromebook2 with basically the same SoC (5800 compared to the 5422 on the XU3) ships with non-secure firmware so all of the above mentioned features are working just fine.
I'm working on getting these same features working on the XU3, but this broken firmware as brought a halt to any real progress.
Kevin
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/305790.h... [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/306480.h...
Hi Kevin,
On 8 December 2014 at 10:58, Kevin Hilman khilman@kernel.org wrote:
Lukasz Majewski l.majewski@majess.pl writes:
[...]
On 28 November 2014 at 06:46, Lukasz Majewski l.majewski@majess.pl wrote:
Hello Javier,
Hello Lukasz,
On Fri, Nov 28, 2014 at 9:39 AM, Lukasz Majewski l.majewski@majess.pl wrote:
> I have yet to take him up on that offer though, but it sounds > like a good way forward. The current layout really isn't > practical. >
It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board.
Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the "normal" user do things.
He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel.
I agree with Sjoed that normal users don't replace the low-level components that are provided by the board vendor.
After all you can boot a mainline kernel using the vendor u-boot, just append the DTB and create a uImage. The practical reason why someone would want to replace the vendor u-boot is to have more features but is very hard to do if there is a constraint in the maximum u-boot image size (even harder if the maximum is such small like in the XU3).
I agree that 328 KiB size for u-boot is a constraint. I don't know HardKernel's justification for this.
For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB.
It is challenging but for sure doable.
It is doable but I don't see why the default BL2 _must_ be used.
For practical/pragmatic reasons:
- It is difficult to have signed BL2 - each time we need to ask
HardKernel for signing it. It is impractical and hampers usage of mainline SPL (BL2) with XU3.
- All the documentation on the HardKernel wiki site refers to the
default BL2.
- We will have "new" BL2, which source code is based on 2012.07
mainline u-boot.
- Two BL2 binaries - IMHO will hurt (i.e. brick) some device sooner
or latter.
A user that wants to replace the kernel or u-boot is already tech-savy and can for sure replace the BL2 as well if it's publicly available.
Sorry, but I'm a bit sceptical about updating such low level code. Bad things do happen.
Maybe hardkernel folks can even make the modified BL2 available on their website and the link added in the comment explaining the layout?
We would then require HardKernel to:
- Provide updated BL2.img
- Update their wiki to reflect the new BL2.
Also, it is an artificial constraint after all and can be easily modified. In fact I think we should push hardkernel to change that layout by default and use a BL2/SPL that has more sensible size for the u-boot binary even if they don't need it for their vendor u-boot which seems to be quite small.
I totally agree.
I'd like to propose a following plan:
- Accept Hyungwon's patches to have XU3 u-boot < 328 KiB (with
link to default BL2) to have XU3 support in place (and treat it as a starting point)
- If u-boot's size less than 328 KiB is _really_ a problem to
somebody then ask hardkernel to change BL2 or: - modify their sources to change the layout (I regard this as a "quick hack" solution) - with a lot of pain develop BL2/SPL (by whom?) which base on newest mainline (then for each test hardkernel must sign the binary).
My 2p worth...
The current Hardkernel BL1 looks broken to me - it is just too old.
+1
FWIW, the XU3 firmware is broken in other ways as well which have a major impact on power management.
First, with mainline kernels using MCPM, only 6 of 8 CPUs come online. However, even with that fixed[1], it turns out that the kernel can't properly manage CCI due to secure firmware[2], which means that MCPM (multi-cluster power management) can't work, and thus the low-power cluster-idle states can't work, the big.LITTLE switcher cannot work, and the ongoing work on energy-aware scheduling will not be useful on this platform.
Anyone know what are the chances of getting a non-secure version of the firmware for this platform. The Samsung Chromebook2 with basically the same SoC (5800 compared to the 5422 on the XU3) ships with non-secure firmware so all of the above mentioned features are working just fine.
I have pushed on this but apparently it is not possible - they need to sign every BL2. The only implementation I've seen sets up the chip in BL2 (U-Boot SPL) so I don't think we can work around it. It takes us back to the 1960s where we sent off our code at night to run it :-)
I think the best bet is the current effort to mainline the rest of the Chromebook code then try to build it for XU3.
I'm working on getting these same features working on the XU3, but this broken firmware as brought a halt to any real progress.
Agreed, but I think this is feasible once U-Boot on XU3 is sorted out.
Regards, Simon
Hi Simon,
Simon Glass sjg@chromium.org writes:
On 8 December 2014 at 10:58, Kevin Hilman khilman@kernel.org wrote:
[...]
FWIW, the XU3 firmware is broken in other ways as well which have a major impact on power management.
First, with mainline kernels using MCPM, only 6 of 8 CPUs come online. However, even with that fixed[1], it turns out that the kernel can't properly manage CCI due to secure firmware[2], which means that MCPM (multi-cluster power management) can't work, and thus the low-power cluster-idle states can't work, the big.LITTLE switcher cannot work, and the ongoing work on energy-aware scheduling will not be useful on this platform.
Anyone know what are the chances of getting a non-secure version of the firmware for this platform. The Samsung Chromebook2 with basically the same SoC (5800 compared to the 5422 on the XU3) ships with non-secure firmware so all of the above mentioned features are working just fine.
I have pushed on this but apparently it is not possible - they need to sign every BL2. The only implementation I've seen sets up the chip in BL2 (U-Boot SPL) so I don't think we can work around it.
Not quite sure I'm following...
So is secure-mode enabled before BL2 is started? Or do you mean BL2 is where secure-mode is enabled? If it's done in BL2, and if the hardkernel folks are willing to sign BL2 images (which I gathered from discussions elsewhere in this series) then it seems possible to turn off secure-mode.
So I went to look in the u-boot-samsung repo and didn't see the code for the SPL there. Is the BL2 source (which I understood to be u-boot SPL) in some other repo?
It takes us back to the 1960s where we sent off our code at night to run it :-)
I think the best bet is the current effort to mainline the rest of the Chromebook code then try to build it for XU3.
What's the status of that effort?
I'm working on getting these same features working on the XU3, but this broken firmware as brought a halt to any real progress.
Agreed, but I think this is feasible once U-Boot on XU3 is sorted out.
Let's hope so.
Kevin
Hi,
On 8 December 2014 at 18:27, Kevin Hilman khilman@kernel.org wrote:
Hi Simon,
Simon Glass sjg@chromium.org writes:
On 8 December 2014 at 10:58, Kevin Hilman khilman@kernel.org wrote:
[...]
FWIW, the XU3 firmware is broken in other ways as well which have a major impact on power management.
First, with mainline kernels using MCPM, only 6 of 8 CPUs come online. However, even with that fixed[1], it turns out that the kernel can't properly manage CCI due to secure firmware[2], which means that MCPM (multi-cluster power management) can't work, and thus the low-power cluster-idle states can't work, the big.LITTLE switcher cannot work, and the ongoing work on energy-aware scheduling will not be useful on this platform.
Anyone know what are the chances of getting a non-secure version of the firmware for this platform. The Samsung Chromebook2 with basically the same SoC (5800 compared to the 5422 on the XU3) ships with non-secure firmware so all of the above mentioned features are working just fine.
I have pushed on this but apparently it is not possible - they need to sign every BL2. The only implementation I've seen sets up the chip in BL2 (U-Boot SPL) so I don't think we can work around it.
Not quite sure I'm following...
So is secure-mode enabled before BL2 is started? Or do you mean BL2 is where secure-mode is enabled? If it's done in BL2, and if the hardkernel folks are willing to sign BL2 images (which I gathered from discussions elsewhere in this series) then it seems possible to turn off secure-mode.
Yes it is possible - and easy - to do in BL2 / U-Boot SPL. This is what the Chromebooks do.
So I went to look in the u-boot-samsung repo and didn't see the code for the SPL there. Is the BL2 source (which I understood to be u-boot SPL) in some other repo?
It's in mainline U-Boot so no particular need to go to the Samsung tree. See arch/arm/cpu/armv7/exynos/spl_boot.c and tzpc.c for the TrustZone stuff.
It takes us back to the 1960s where we sent off our code at night to run it :-)
I think the best bet is the current effort to mainline the rest of the Chromebook code then try to build it for XU3.
What's the status of that effort?
Coming along but the big/little support is still not there. The display works and most core peripherals. Needs more SPL work.
I'm working on getting these same features working on the XU3, but this broken firmware as brought a halt to any real progress.
Agreed, but I think this is feasible once U-Boot on XU3 is sorted out.
Let's hope so.
Kevin
Regards, Simon
Simon Glass sjg@chromium.org writes:
On 8 December 2014 at 18:27, Kevin Hilman khilman@kernel.org wrote:
[...]
So is secure-mode enabled before BL2 is started? Or do you mean BL2 is where secure-mode is enabled? If it's done in BL2, and if the hardkernel folks are willing to sign BL2 images (which I gathered from discussions elsewhere in this series) then it seems possible to turn off secure-mode.
Yes it is possible - and easy - to do in BL2 / U-Boot SPL. This is what the Chromebooks do.
OK, good.
So I went to look in the u-boot-samsung repo and didn't see the code for the SPL there. Is the BL2 source (which I understood to be u-boot SPL) in some other repo?
It's in mainline U-Boot so no particular need to go to the Samsung tree.
I went to the samsung tree since the cover letter for this series pointed me there. But I just tried the latest version of this series (v11) using mainlin u-boot. Thanks for the pointer.
See arch/arm/cpu/armv7/exynos/spl_boot.c and tzpc.c for the TrustZone stuff.
OK, thanks. Any pointers on how to get this building with mainline u-boot? Just adding CONFIG_SPL to odroid_xu3.h doesn't seem to work (compile errors.) I'm quite comfortable in the kernel, but I'm not very familiar with u-boot, especially SPL.
It takes us back to the 1960s where we sent off our code at night to run it :-)
I think the best bet is the current effort to mainline the rest of the Chromebook code then try to build it for XU3.
What's the status of that effort?
Coming along but the big/little support is still not there. The display works and most core peripherals. Needs more SPL work.
OK, I'll be glad to be a beta tester if/when you get to that point.
Thanks,
Kevin
Hi Kevin,
On 9 December 2014 at 17:03, Kevin Hilman khilman@kernel.org wrote:
Simon Glass sjg@chromium.org writes:
On 8 December 2014 at 18:27, Kevin Hilman khilman@kernel.org wrote:
[...]
So is secure-mode enabled before BL2 is started? Or do you mean BL2 is where secure-mode is enabled? If it's done in BL2, and if the hardkernel folks are willing to sign BL2 images (which I gathered from discussions elsewhere in this series) then it seems possible to turn off secure-mode.
Yes it is possible - and easy - to do in BL2 / U-Boot SPL. This is what the Chromebooks do.
OK, good.
So I went to look in the u-boot-samsung repo and didn't see the code for the SPL there. Is the BL2 source (which I understood to be u-boot SPL) in some other repo?
It's in mainline U-Boot so no particular need to go to the Samsung tree.
I went to the samsung tree since the cover letter for this series pointed me there. But I just tried the latest version of this series (v11) using mainlin u-boot. Thanks for the pointer.
See arch/arm/cpu/armv7/exynos/spl_boot.c and tzpc.c for the TrustZone stuff.
OK, thanks. Any pointers on how to get this building with mainline u-boot? Just adding CONFIG_SPL to odroid_xu3.h doesn't seem to work (compile errors.) I'm quite comfortable in the kernel, but I'm not very familiar with u-boot, especially SPL.
It's normally automatic unless some special disabling was done - see spl/u-boot-spl.bin in the output. You need to sign it though :-(
It takes us back to the 1960s where we sent off our code at night to run it :-)
I think the best bet is the current effort to mainline the rest of the Chromebook code then try to build it for XU3.
What's the status of that effort?
Coming along but the big/little support is still not there. The display works and most core peripherals. Needs more SPL work.
OK, I'll be glad to be a beta tester if/when you get to that point.
Thanks,
Kevin
Regards, Simon
Simon Glass sjg@chromium.org writes:
[...]
OK, thanks. Any pointers on how to get this building with mainline u-boot? Just adding CONFIG_SPL to odroid_xu3.h doesn't seem to work (compile errors.) I'm quite comfortable in the kernel, but I'm not very familiar with u-boot, especially SPL.
It's normally automatic unless some special disabling was done - see spl/u-boot-spl.bin in the output. You need to sign it though :-(
Right, I'm used to finding it there, but there's nothing there when buildling using odroid-xu3_config with $SUBJECT series.
Kevin
Dear Kevin,
On Wed, 10 Dec 2014 11:20:43 -0800 Kevin Hilman khilman@kernel.org wrote:
Simon Glass sjg@chromium.org writes:
[...]
OK, thanks. Any pointers on how to get this building with mainline u-boot? Just adding CONFIG_SPL to odroid_xu3.h doesn't seem to work (compile errors.) I'm quite comfortable in the kernel, but I'm not very familiar with u-boot, especially SPL.
It's normally automatic unless some special disabling was done - see spl/u-boot-spl.bin in the output. You need to sign it though :-(
Right, I'm used to finding it there, but there's nothing there when buildling using odroid-xu3_config with $SUBJECT series.
CONFIG_SPL_BUILD must be turn on for that(You can find the detailesin doc/README.SPL). But neither common exynos config files nor odroid xu3 specific config file contain the config option. Before I turned on that option, but not work at the moment. Some work should be done by someone. I am sorry to say, but I cannot assure I can do that immediately.
Kevin
Best regards, Hyungwon Hwang
Hi Kevin,
Lukasz Majewski l.majewski@majess.pl writes:
[...]
On 28 November 2014 at 06:46, Lukasz Majewski l.majewski@majess.pl wrote:
Hello Javier,
Hello Lukasz,
On Fri, Nov 28, 2014 at 9:39 AM, Lukasz Majewski l.majewski@majess.pl wrote:
> I have yet to take him up on that offer though, but it sounds > like a good way forward. The current layout really isn't > practical. >
It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board.
Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the "normal" user do things.
He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel.
I agree with Sjoed that normal users don't replace the low-level components that are provided by the board vendor.
After all you can boot a mainline kernel using the vendor u-boot, just append the DTB and create a uImage. The practical reason why someone would want to replace the vendor u-boot is to have more features but is very hard to do if there is a constraint in the maximum u-boot image size (even harder if the maximum is such small like in the XU3).
I agree that 328 KiB size for u-boot is a constraint. I don't know HardKernel's justification for this.
For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB.
It is challenging but for sure doable.
It is doable but I don't see why the default BL2 _must_ be used.
For practical/pragmatic reasons:
- It is difficult to have signed BL2 - each time we need to ask
HardKernel for signing it. It is impractical and hampers usage of mainline SPL (BL2) with XU3.
- All the documentation on the HardKernel wiki site refers to
the default BL2.
- We will have "new" BL2, which source code is based on 2012.07
mainline u-boot.
- Two BL2 binaries - IMHO will hurt (i.e. brick) some device
sooner or latter.
A user that wants to replace the kernel or u-boot is already tech-savy and can for sure replace the BL2 as well if it's publicly available.
Sorry, but I'm a bit sceptical about updating such low level code. Bad things do happen.
Maybe hardkernel folks can even make the modified BL2 available on their website and the link added in the comment explaining the layout?
We would then require HardKernel to:
- Provide updated BL2.img
- Update their wiki to reflect the new BL2.
Also, it is an artificial constraint after all and can be easily modified. In fact I think we should push hardkernel to change that layout by default and use a BL2/SPL that has more sensible size for the u-boot binary even if they don't need it for their vendor u-boot which seems to be quite small.
I totally agree.
I'd like to propose a following plan:
- Accept Hyungwon's patches to have XU3 u-boot < 328 KiB (with
link to default BL2) to have XU3 support in place (and treat it as a starting point)
- If u-boot's size less than 328 KiB is _really_ a problem to
somebody then ask hardkernel to change BL2 or: - modify their sources to change the layout (I regard this as a "quick hack" solution) - with a lot of pain develop BL2/SPL (by whom?) which base on newest mainline (then for each test hardkernel must sign the binary).
My 2p worth...
The current Hardkernel BL1 looks broken to me - it is just too old.
+1
FWIW, the XU3 firmware is broken in other ways as well which have a major impact on power management.
First, with mainline kernels using MCPM, only 6 of 8 CPUs come online. However, even with that fixed[1], it turns out that the kernel can't properly manage CCI due to secure firmware[2], which means that MCPM (multi-cluster power management) can't work, and thus the low-power cluster-idle states can't work, the big.LITTLE switcher cannot work, and the ongoing work on energy-aware scheduling will not be useful on this platform.
I've stumbled upon the "imprecise aborts" in Exynos5422. Moreover I've heard about problems with bringing up all 8 CPUs on that platform.
Anyone know what are the chances of getting a non-secure version of the firmware for this platform. The Samsung Chromebook2 with basically the same SoC (5800 compared to the 5422 on the XU3) ships with non-secure firmware so all of the above mentioned features are working just fine.
You can look into the HardKernle's u-boot from their github: https://github.com/hardkernel/u-boot
then tune it and send to hardkernel to be signed.
I guess that the described above problem might be with TZSW software - the one from Chromebook2 might be different from the one from Hard Kernel.
Correct me if I'm wrong, but isn't power management governed by TZSW - by calling smc instruction with proper parameter?
Regarding Hard Kernel - their u-boot/u-boot-spl(SPL/BL2) is from 2012. It is quite old. Problem here is that to update (SPL/BL2) one needs to send this binary to Hard Kernel for signing.
However, in my opinion working BL1 and BL2 for XU3 should be delivered by Hard Kernel. Period.
Therefore, please ask them on support/forum why do we experience such problems with cluster/power management on mainline Linux .
I'm working on getting these same features working on the XU3, but this broken firmware as brought a halt to any real progress.
Kevin
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/305790.h... [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/306480.h...
On 11/27/2014 10:21 PM, Hyungwon Hwang wrote:
This patch adds documentation for Odroid-XU3. This documentation is based on that of Odroid (doc/README-odroid) made by Przemyslaw Marczak. The documentation includes basic information about boot media layout, environment, partition layout, and the instruction to burn the u-boot image to boot media.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Tested-by: Lukasz Majewski l.majewski@samsung.com Acked-by: Lukasz Majewski l.majewski@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com
Changes for v6:
- Newly added
Changes for v7:
- Fix several errata in the documentation
Changes for v8:
- None
Changes for v9:
- Add the new contents to the documentation of Odroid X2/U2, instead of
making new document for Odorid XU3
doc/README.odroid | 46 ++++++++++++++++++++++++++++++---------------- 1 file changed, 30 insertions(+), 16 deletions(-)
diff --git a/doc/README.odroid b/doc/README.odroid index 25b962b..99693d4 100644 --- a/doc/README.odroid +++ b/doc/README.odroid @@ -1,28 +1,39 @@
- U-boot for Odroid X2/U3
- U-boot for Odroid X2/U3/XU3
========================
- Summary
========== -This is a quick instruction for setup Odroid boards based on Exynos4412.
s/Exynos4412/Exynos/ ?
Best Regards, Jaehoon Chung
-Board config: odroid_config +This is a quick instruction for setup Odroid boards. +Board config: odroid_config for X2/U3 +Board config: odroid-xu3_config for XU3
- Supported devices
==================== -This U-BOOT config can be used on two boards: +This U-BOOT config can be used on three boards:
- Odroid U3
- Odroid X2
with CPU Exynos 4412 rev 2.0 and 2GB of RAM +- Odroid XU3 +with CPU Exynos5422 and 2GB of RAM
- Boot sequence
================ iROM->BL1->(BL2 + TrustZone)->U-BOOT
-This version of U-BOOT doesn't implement SPL but it is required(BL2) -and can be found in "boot.tar.gz" from here: +This version of U-BOOT doesn't implement SPL. So, BL1, BL2, and TrustZone +binaries are needed to boot up.
+<< X2/U3 >> +It can be found in "boot.tar.gz" from here: http://dev.odroid.com/projects/4412boot/wiki/FrontPage?action=download&v... or here: http://odroid.in/guides/ubuntu-lfs/boot.tar.gz
+<< XU3 >> +It can be downloaded from: +https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardker...
- Boot media layout
==================== The table below shows SD/eMMC cards layout for U-boot. @@ -35,18 +46,20 @@ The block offset is starting from 0 and the block size is 512B. | Bl2 | 31 | 30 | 1 (boot) | | U-boot | 63 | 62 | 1 (boot) | | Tzsw | 2111 | 2110 | 1 (boot) | -| Uboot Env | 2500 | 2500 | 0 (user) |
+| Uboot Env | 2560 | 2560 | 0 (user) |
- Prepare the SD boot card - with SD card reader
================================================= To prepare bootable media you need boot binaries provided by hardkernel. -File "boot.tar.gz" (link in point 3.) contains: -- E4412_S.bl1.HardKernel.bin -- E4412_S.tzsw.signed.bin -- bl2.signed.bin +From the downloaded files, You can find: +- bl1.bin +- tzsw.bin +- bl2.bin
- sd_fusing.sh
- u-boot.bin
+(The file names can be slightly different, but you can distinguish what they are +without problem)
This is all you need to boot this board. But if you want to use your custom u-boot then you need to change u-boot.bin with your own u-boot binary* @@ -56,7 +69,7 @@ and run the script "sd_fusing.sh" - this script is valid only for SD card. The proper binary file of current U-boot is u-boot-dtb.bin.
quick steps for Linux: -- extract boot.tar.gz +- Download all files from the link at point 3 and extract it if needed.
- put any SD card into the SD reader
- check the device with "dmesg"
- run ./sd_fusing.sh /dev/sdX - where X is SD card device (but not a partition)
@@ -66,7 +79,7 @@ Check if Hardkernel U-boot is booting, and next do the same with your U-boot. with a eMMC card reader (boot from eMMC card slot) ===================================================== To boot the device from the eMMC slot you should use a special card reader -which supports eMMC partiion switch. All of the boot binaries are stored +which supports eMMC partition switch. All of the boot binaries are stored on the eMMC boot partition which is normally hidden.
The "sd_fusing.sh" script can be used after updating offsets of binaries @@ -81,8 +94,8 @@ But then the device can boot only from the SD card slot.
- Prepare the boot media using Hardkernel U-boot
================================================= -You can update the U-boot to the custom one if you have an working bootloader -delivered with the board on a eMMC/SD card. Then follow the steps: +You can update the U-boot to the custom one if you have a working bootloader +delivered with the board on the eMMC/SD card. Then follow the steps:
- install the android fastboot tool
- connect a micro usb cable to the board
- on the U-boot prompt, run command: fastboot (as a root)
@@ -91,7 +104,7 @@ delivered with the board on a eMMC/SD card. Then follow the steps:
- Partition layout
==================== -Default U-boot environment is setup for fixed partiion layout. +Default U-boot environment is setup for fixed partition layout.
Partition table: MSDOS. Disk layout and files as listed in the table below.
@@ -106,6 +119,7 @@ Partition table: MSDOS. Disk layout and files as listed in the table below. Supported fdt files are:
- exynos4412-odroidx2.dtb
- exynos4412-odroidu3.dtb
+- exynos5422-odroidxu3.dtb
Supported kernel files are:
- Image.itb
Hey Hyungwon,
The following are some of the patches i had locally on top of your v9 Odroid. Feel free to merge them into your patchset (or squash them into your existing patches) if they look good to you.
Sjoerd Simons (4): Odroid-XU3: Drop redundant fields Odroid-XU3: Add entry for DTS EHCI GPIO ODROID-XU3: Make odroid-xu3 an smdk5420 variant ODROID-XU3: drop overriding the boot environment
arch/arm/cpu/armv7/exynos/Kconfig | 1 - arch/arm/dts/exynos5422-odroidxu3.dts | 16 ++--- board/samsung/odroid-xu3/Kconfig | 12 ---- board/samsung/odroid-xu3/MAINTAINERS | 6 -- board/samsung/odroid-xu3/Makefile | 7 -- board/samsung/odroid-xu3/odroid-xu3.c | 122 ---------------------------------- board/samsung/odroid-xu3/setup.h | 95 -------------------------- board/samsung/smdk5420/Kconfig | 13 ++++ include/configs/odroid_xu3.h | 72 -------------------- 9 files changed, 17 insertions(+), 327 deletions(-) delete mode 100644 board/samsung/odroid-xu3/Kconfig delete mode 100644 board/samsung/odroid-xu3/MAINTAINERS delete mode 100644 board/samsung/odroid-xu3/Makefile delete mode 100644 board/samsung/odroid-xu3/odroid-xu3.c delete mode 100644 board/samsung/odroid-xu3/setup.h
Drop MMC related fields from the DTS that are already setup by exynos54xx.dtsi and correct the value of fifoth_val
Signed-off-by: Sjoerd Simons sjoerd.simons@collabora.co.uk --- arch/arm/dts/exynos5422-odroidxu3.dts | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts index 533d88e..bd88450 100644 --- a/arch/arm/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -36,22 +36,11 @@ };
mmc@12200000 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; - fifoth_val = <0x200f0020>; - }; - - mmc@12210000 { - status = "disabled"; + fifoth_val = <0x201f0020>; };
mmc@12220000 { - samsung,bus-width = <4>; - samsung,timing = <1 2 3>; - fifoth_val = <0x200f0020>; + fifoth_val = <0x201f0020>; };
- mmc@12230000 { - status = "disabled"; - }; };
Add samsung,vbus-gpio information for the XU3. This allows the usage of the EHCI controller on the XU3, which is connected to the SMSC LAN9514 chip (usb hub + network).
Note that this patch doesn't enable support for USB/USB networking in the default config as makes the u-boot binary too big for the current odroid setup.
Signed-off-by: Sjoerd Simons sjoerd.simons@collabora.co.uk --- arch/arm/dts/exynos5422-odroidxu3.dts | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts index bd88450..1cbb835 100644 --- a/arch/arm/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -43,4 +43,7 @@ fifoth_val = <0x201f0020>; };
+ ehci@12110000 { + samsung,vbus-gpio = <&gpio 0x316 0>; /* X26 */ + }; };
The odroid-xu3 board file sets up clocks that should have are setup by the SPL/BL2, so that code should be redundant. Drop it and make the XU3 an smdk5420 variant like e.g. Peach pit/pi, that way the only differences in the boards u-boot binary are purely due to configuration changes, not code differences.
Signed-off-by: Sjoerd Simons sjoerd.simons@collabora.co.uk --- arch/arm/cpu/armv7/exynos/Kconfig | 1 - board/samsung/odroid-xu3/Kconfig | 12 ---- board/samsung/odroid-xu3/MAINTAINERS | 6 -- board/samsung/odroid-xu3/Makefile | 7 -- board/samsung/odroid-xu3/odroid-xu3.c | 122 ---------------------------------- board/samsung/odroid-xu3/setup.h | 95 -------------------------- board/samsung/smdk5420/Kconfig | 13 ++++ 7 files changed, 13 insertions(+), 243 deletions(-) delete mode 100644 board/samsung/odroid-xu3/Kconfig delete mode 100644 board/samsung/odroid-xu3/MAINTAINERS delete mode 100644 board/samsung/odroid-xu3/Makefile delete mode 100644 board/samsung/odroid-xu3/odroid-xu3.c delete mode 100644 board/samsung/odroid-xu3/setup.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 16c9a0e..88017c7 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -69,7 +69,6 @@ source "board/samsung/universal_c210/Kconfig" source "board/samsung/origen/Kconfig" source "board/samsung/trats2/Kconfig" source "board/samsung/odroid/Kconfig" -source "board/samsung/odroid-xu3/Kconfig" source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig deleted file mode 100644 index 6159692..0000000 --- a/board/samsung/odroid-xu3/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ODROID_XU3 - -config SYS_BOARD - default "odroid-xu3" - -config SYS_VENDOR - default "samsung" - -config SYS_CONFIG_NAME - default "odroid_xu3" - -endif diff --git a/board/samsung/odroid-xu3/MAINTAINERS b/board/samsung/odroid-xu3/MAINTAINERS deleted file mode 100644 index 50cf928..0000000 --- a/board/samsung/odroid-xu3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ODROID-XU3 BOARD -M: Hyungwon Hwang human.hwang@samsung.com -S: Maintained -F: board/samsung/odroid-xu3/ -F: include/configs/odroid_xu3.h -F: configs/odroid-xu3_defconfig diff --git a/board/samsung/odroid-xu3/Makefile b/board/samsung/odroid-xu3/Makefile deleted file mode 100644 index 85ae5c5..0000000 --- a/board/samsung/odroid-xu3/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := odroid-xu3.o diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c deleted file mode 100644 index 8c54842..0000000 --- a/board/samsung/odroid-xu3/odroid-xu3.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (C) 2014 Samsung Electronics - * Hyungwon Hwang human.hwang@samsung.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/clock.h> -#include "setup.h" - -DECLARE_GLOBAL_DATA_PTR; - -unsigned int get_board_rev(void) -{ - return 0; -} - -int exynos_init(void) -{ - return 0; -} - -#ifdef CONFIG_BOARD_EARLY_INIT_F -static int board_clock_init(void) -{ - unsigned int set, clr, clr_src_cpu, clr_pll_con0; - struct exynos5420_clock *clk = (struct exynos5420_clock *) - samsung_get_base_clock(); - /* - * CMU_CPU clocks src to MPLL - * Bit values: 0 ; 1 - * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL - * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL - * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C - * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL - */ - - /* Set CMU_CPU clocks src to OSCCLK */ - clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1); - set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1); - - clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); - - while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu))) - continue; - - /* Set APLL to 1200MHz */ - clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | - PLL_ENABLE(1); - set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1); - - clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); - - while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) - continue; - - /* Set CMU_CPU clocks src to APLL */ - set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0); - clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); - - while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu))) - continue; - - clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) | - PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7); - set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) | - PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0); - - clrsetbits_le32(&clk->div_cpu0, clr, set); - - while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) - continue; - - /* Set MPLL to 800MHz */ - set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1); - - clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); - - while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) - continue; - - /* Set CLKMUX_UART src to MPLL */ - clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | UART3_SEL(7); - set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | UART3_SEL(3); - - clrsetbits_le32(&clk->src_peric0, clr, set); - - /* Set SCLK_UART to 400 MHz (MPLL / 2) */ - clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | - UART3_RATIO(15); - set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) | - UART3_RATIO(1); - - clrsetbits_le32(&clk->div_peric0, clr, set); - - while (readl(&clk->div_stat_peric0) & DIV_STAT_PERIC0_CHANGING) - continue; - - /* Set CLKMUX_MMC src to MPLL */ - clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7); - set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3); - - clrsetbits_le32(&clk->src_fsys, clr, set); - - clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | MMC2_RATIO(0x3ff); - set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0); - - clrsetbits_le32(&clk->div_fsys1, clr, set); - - /* Wait for divider ready status */ - while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) - continue; - - return 0; -} - -int exynos_early_init_f(void) -{ - return board_clock_init(); -} -#endif diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h deleted file mode 100644 index 143c189..0000000 --- a/board/samsung/odroid-xu3/setup.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2014 Samsung Electronics - * Hyungwon Hwang human.hwang@samsung.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ODROID_XU3_SETUP__ -#define __ODROID_XU3_SETUP__ - -#define SDIV(x) ((x) & 0x7) -#define PDIV(x) (((x) & 0x3f) << 8) -#define MDIV(x) (((x) & 0x3ff) << 16) -#define FSEL(x) (((x) & 0x1) << 27) -#define PLL_LOCKED_BIT (0x1 << 29) -#define PLL_ENABLE(x) (((x) & 0x1) << 31) - -/* CLK_SRC_CPU */ -#define MUX_APLL_SEL(x) ((x) & 0x1) -#define MUX_CORE_SEL(x) (((x) & 0x1) << 16) - -/* CLK_MUX_STAT_CPU */ -#define APLL_SEL(x) ((x) & 0x7) -#define CORE_SEL(x) (((x) & 0x7) << 16) -#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) || \ - (x) & APLL_SEL(1) || \ - (x) & CORE_SEL(0) || \ - (x) & CORE_SEL(1)) - -/* CLK_DIV_CPU0 */ -#define ARM_RATIO(x) ((x) & 0x7) -#define CPUD_RATIO(x) (((x) & 0x7) << 4) -#define ATB_RATIO(x) (((x) & 0x7) << 16) -#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) -#define APLL_RATIO(x) (((x) & 0x7) << 24) -#define ARM2_RATIO(x) (((x) & 0x7) << 28) - -/* CLK_DIV_STAT_CPU0 */ -#define DIV_CPUD(x) (((x) & 0x1) << 4) -#define DIV_ATB(x) (((x) & 0x1) << 16) -#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) -#define DIV_APLL(x) (((x) & 0x1) << 24) -#define DIV_ARM2(x) (((x) & 0x1) << 28) - -#define DIV_STAT_CHANGING 0x1 -#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \ - DIV_ATB(DIV_STAT_CHANGING) | \ - DIV_PCLK_DBG(DIV_STAT_CHANGING) | \ - DIV_APLL(DIV_STAT_CHANGING) | \ - DIV_ARM2(DIV_STAT_CHANGING)) - -/* Set CLK_SRC_PERIC0 */ -#define UART0_SEL(x) (((x) & 0xf) << 4) -#define UART1_SEL(x) (((x) & 0xf) << 8) -#define UART2_SEL(x) (((x) & 0xf) << 12) -#define UART3_SEL(x) (((x) & 0xf) << 16) - -/* Set CLK_DIV_PERIC0 */ -#define UART0_RATIO(x) (((x) & 0xf) << 8) -#define UART1_RATIO(x) (((x) & 0xf) << 12) -#define UART2_RATIO(x) (((x) & 0xf) << 16) -#define UART3_RATIO(x) (((x) & 0xf) << 20) - -/* Set CLK_DIV_STAT_PERIC0 */ -#define DIV_UART0(x) ((x) & 0x1) -#define DIV_UART1(x) (((x) & 0x1) << 4) -#define DIV_UART2(x) (((x) & 0x1) << 8) -#define DIV_UART3(x) (((x) & 0x1) << 12) -#define DIV_UART4(x) (((x) & 0x1) << 16) - -#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \ - DIV_UART3(DIV_STAT_CHANGING) | \ - DIV_UART2(DIV_STAT_CHANGING) | \ - DIV_UART1(DIV_STAT_CHANGING) | \ - DIV_UART0(DIV_STAT_CHANGING)) - -/* CLK_SRC_FSYS */ -#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8) -#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12) -#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16) - -/* CLK_DIV_FSYS1 */ -#define MMC0_RATIO(x) ((x) & 0x3ff) -#define MMC1_RATIO(x) (((x) & 0x3ff) << 10) -#define MMC2_RATIO(x) (((x) & 0x3ff) << 20) - -#define DIV_MMC0(x) (((x) & 1) << 20) -#define DIV_MMC1(x) (((x) & 1) << 24) -#define DIV_MMC2(x) (((x) & 1) << 28) - -#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \ - DIV_MMC1(DIV_STAT_CHANGING) | \ - DIV_MMC2(DIV_STAT_CHANGING)) - -#endif diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig index e7aafe5..ff28b1d 100644 --- a/board/samsung/smdk5420/Kconfig +++ b/board/samsung/smdk5420/Kconfig @@ -1,3 +1,16 @@ +if TARGET_ODROID_XU3 + +config SYS_BOARD + default "smdk5420" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "odroid_xu3" + +endif + if TARGET_PEACH_PI
config SYS_BOARD
Remove the override of the boot environment, this causes the board to use the distro_bootcmd setup for booting as included by exynos5-common.h.
Signed-off-by: Sjoerd Simons sjoerd.simons@collabora.co.uk --- include/configs/odroid_xu3.h | 72 -------------------------------------------- 1 file changed, 72 deletions(-)
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 1d53653..a60d4e5 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -45,80 +45,8 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
-#define CONFIG_BOOTCOMMAND "run autoboot" #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
-/* - * For details, refer the documentation: doc/README.odroid -*/ -#ifdef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_EXTRA_ENV_SETTINGS -#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ - "${kernelname}\0" \ - "loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ - "${initrdname}\0" \ - "loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \ - "${fdtfile}\0" \ - "check_ramdisk=" \ - "if run loadinitrd; then " \ - "setenv initrd_addr ${initrdaddr};" \ - "else " \ - "setenv initrd_addr -;" \ - "fi;\0" \ - "check_dtb=" \ - "if run loaddtb; then " \ - "setenv fdt_addr ${fdtaddr};" \ - "else " \ - "setenv fdt_addr;" \ - "fi;\0" \ - "kernel_args=" \ - "setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \ - " rootwait ${console} ${opts}\0" \ - "boot_fit=" \ - "setenv kerneladdr 0x42000000;" \ - "setenv kernelname Image.itb;" \ - "run loadkernel;" \ - "run kernel_args;" \ - "bootm ${kerneladdr}#${boardname}\0" \ - "boot_uimg=" \ - "setenv kerneladdr 0x40007FC0;" \ - "setenv kernelname uImage;" \ - "run check_dtb;" \ - "run check_ramdisk;" \ - "run loadkernel;" \ - "run kernel_args;" \ - "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ - "boot_zimg=" \ - "setenv kerneladdr 0x40007FC0;" \ - "setenv kernelname zImage;" \ - "run check_dtb;" \ - "run check_ramdisk;" \ - "run loadkernel;" \ - "run kernel_args;" \ - "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ - "autoboot=" \ - "if test -e mmc 0 Image.itb; then; " \ - "run boot_fit;" \ - "elif test -e mmc 0 zImage; then; " \ - "run boot_zimg;" \ - "elif test -e mmc 0 uImage; then; " \ - "run boot_uimg;" \ - "fi;\0" \ - "console=" CONFIG_DEFAULT_CONSOLE \ - "mmcbootdev=0\0" \ - "mmcbootpart=1\0" \ - "mmcrootdev=0\0" \ - "mmcrootpart=2\0" \ - "bootdelay=0\0" \ - "dfu_alt_info=Please reset the board\0" \ - "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ - "consoleoff=set console console=ram; save; reset\0" \ - "initrdname=uInitrd\0" \ - "initrdaddr=42000000\0" \ - "fdtaddr=40800000\0" - /* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ #undef CONFIG_EXYNOS_TMU #undef CONFIG_TMU_CMD_DTT
Dear Sjoerd,
Thanks for this work. I think it is better to squash patch #1, #3, #4 into my patchs, because these patches remove the code which needlessly being added by my patches. I will include patch #2 also from next version.
On Mon, 01 Dec 2014 13:34:16 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
Hey Hyungwon,
The following are some of the patches i had locally on top of your v9 Odroid. Feel free to merge them into your patchset (or squash them into your existing patches) if they look good to you.
Sjoerd Simons (4): Odroid-XU3: Drop redundant fields Odroid-XU3: Add entry for DTS EHCI GPIO ODROID-XU3: Make odroid-xu3 an smdk5420 variant ODROID-XU3: drop overriding the boot environment
arch/arm/cpu/armv7/exynos/Kconfig | 1 - arch/arm/dts/exynos5422-odroidxu3.dts | 16 ++--- board/samsung/odroid-xu3/Kconfig | 12 ---- board/samsung/odroid-xu3/MAINTAINERS | 6 -- board/samsung/odroid-xu3/Makefile | 7 -- board/samsung/odroid-xu3/odroid-xu3.c | 122
board/samsung/odroid-xu3/setup.h | 95 -------------------------- board/samsung/smdk5420/Kconfig | 13 ++++ include/configs/odroid_xu3.h | 72 -------------------- 9 files changed, 17 insertions(+), 327 deletions(-) delete mode 100644 board/samsung/odroid-xu3/Kconfig delete mode 100644 board/samsung/odroid-xu3/MAINTAINERS delete mode 100644 board/samsung/odroid-xu3/Makefile delete mode 100644 board/samsung/odroid-xu3/odroid-xu3.c delete mode 100644 board/samsung/odroid-xu3/setup.h
Best regards, Hyungwon Hwang
Hi,
On 12/02/2014 10:56 AM, Hyungwon Hwang wrote:
Dear Sjoerd,
Thanks for this work. I think it is better to squash patch #1, #3, #4 into my patchs, because these patches remove the code which needlessly being added by my patches. I will include patch #2 also from next version.
On Mon, 01 Dec 2014 13:34:16 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
Hey Hyungwon,
The following are some of the patches i had locally on top of your v9 Odroid. Feel free to merge them into your patchset (or squash them into your existing patches) if they look good to you.
Sjoerd Simons (4): Odroid-XU3: Drop redundant fields Odroid-XU3: Add entry for DTS EHCI GPIO ODROID-XU3: Make odroid-xu3 an smdk5420 variant
I need to support odroid xu3 specific gpio setting e.g. to reset emmc for reset command support. Also there are specific gpio setting codes for only smdk5420 board on board/samsung/smdk5420/smdk5420.c and they are not related with odroid xu3 board.
So, i think that need to split them.
First, split board file. It's easiest way to make separate board directory.
Second, we can make just board file for odroid xu3 in same directory and we should distinguish them from Makefile but i don't know this is general way.
Third, using same board file like now but we will need any way to distinguish boards on runtime.
Any ideas?
Thanks.
ODROID-XU3: drop overriding the boot environment
arch/arm/cpu/armv7/exynos/Kconfig | 1 - arch/arm/dts/exynos5422-odroidxu3.dts | 16 ++--- board/samsung/odroid-xu3/Kconfig | 12 ---- board/samsung/odroid-xu3/MAINTAINERS | 6 -- board/samsung/odroid-xu3/Makefile | 7 -- board/samsung/odroid-xu3/odroid-xu3.c | 122
board/samsung/odroid-xu3/setup.h | 95 -------------------------- board/samsung/smdk5420/Kconfig | 13 ++++ include/configs/odroid_xu3.h | 72 -------------------- 9 files changed, 17 insertions(+), 327 deletions(-) delete mode 100644 board/samsung/odroid-xu3/Kconfig delete mode 100644 board/samsung/odroid-xu3/MAINTAINERS delete mode 100644 board/samsung/odroid-xu3/Makefile delete mode 100644 board/samsung/odroid-xu3/odroid-xu3.c delete mode 100644 board/samsung/odroid-xu3/setup.h
Best regards, Hyungwon Hwang _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On Wed, 2015-01-07 at 17:31 +0900, Joonyoung Shim wrote:
Hi,
On 12/02/2014 10:56 AM, Hyungwon Hwang wrote:
Dear Sjoerd,
Thanks for this work. I think it is better to squash patch #1, #3, #4 into my patchs, because these patches remove the code which needlessly being added by my patches. I will include patch #2 also from next version.
On Mon, 01 Dec 2014 13:34:16 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
Hey Hyungwon,
The following are some of the patches i had locally on top of your v9 Odroid. Feel free to merge them into your patchset (or squash them into your existing patches) if they look good to you.
Sjoerd Simons (4): Odroid-XU3: Drop redundant fields Odroid-XU3: Add entry for DTS EHCI GPIO ODROID-XU3: Make odroid-xu3 an smdk5420 variant
I need to support odroid xu3 specific gpio setting e.g. to reset emmc for reset command support. Also there are specific gpio setting codes for only smdk5420 board on board/samsung/smdk5420/smdk5420.c and they are not related with odroid xu3 board.
So i think that need to split them.
For the gpio specific to the smdk5420 are you referring to the usb vbus gpio ? (For which i've dropped the code in a later, merged commit as it's handled by common code).
First, split board file. It's easiest way to make separate board directory.
Second, we can make just board file for odroid xu3 in same directory and we should distinguish them from Makefile but i don't know this is general way.
Third, using same board file like now but we will need any way to distinguish boards on runtime.
To distinguish boards at runtime you should use the information from the DT file of the board rather then hardcoding it in a board file.
Hi Sjoerd,
On 01/07/2015 06:25 PM, Sjoerd Simons wrote:
On Wed, 2015-01-07 at 17:31 +0900, Joonyoung Shim wrote:
Hi,
On 12/02/2014 10:56 AM, Hyungwon Hwang wrote:
Dear Sjoerd,
Thanks for this work. I think it is better to squash patch #1, #3, #4 into my patchs, because these patches remove the code which needlessly being added by my patches. I will include patch #2 also from next version.
On Mon, 01 Dec 2014 13:34:16 +0100 Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
Hey Hyungwon,
The following are some of the patches i had locally on top of your v9 Odroid. Feel free to merge them into your patchset (or squash them into your existing patches) if they look good to you.
Sjoerd Simons (4): Odroid-XU3: Drop redundant fields Odroid-XU3: Add entry for DTS EHCI GPIO ODROID-XU3: Make odroid-xu3 an smdk5420 variant
I need to support odroid xu3 specific gpio setting e.g. to reset emmc for reset command support. Also there are specific gpio setting codes for only smdk5420 board on board/samsung/smdk5420/smdk5420.c and they are not related with odroid xu3 board.
So i think that need to split them.
For the gpio specific to the smdk5420 are you referring to the usb vbus gpio ? (For which i've dropped the code in a later, merged commit as it's handled by common code).
I just mean current remaining - lcd and pwm codes, but maybe can move them to device tree.
First, split board file. It's easiest way to make separate board directory.
Second, we can make just board file for odroid xu3 in same directory and we should distinguish them from Makefile but i don't know this is general way.
Third, using same board file like now but we will need any way to distinguish boards on runtime.
To distinguish boards at runtime you should use the information from the DT file of the board rather then hardcoding it in a board file.
OK, let's try to use device tree.
Thanks for guide.
participants (10)
-
Hyungwon Hwang -
Jaehoon Chung -
Javier Martinez Canillas -
Joonyoung Shim -
Kevin Hilman -
Lukasz Majewski -
Lukasz Majewski -
Simon Glass -
Sjoerd Simons -
Suriyan Ramasami