This serials patches add mipi dsi support for rk3399. Except the basic mipi driver, we need also enable pmic rk808 for lcd power and enable i2c for rk808 communication. what's more, the needed clk and pwm for backlight is init in spl stage, make sure spl work first.
Eric Gao (5): rockchip: i2c: Enable i2c for rk3399 rockchip: pmic: Enable RK808 for rk3399 evb rockchip: video: Add mipi dsi driver for rk3399 rockchip: dts: Add mipi dsi support for rk3399 rockchip: configs: Enable mipi dsi for rk3399
arch/arm/dts/rk3399-evb.dts | 123 ++++++ arch/arm/dts/rk3399.dtsi | 88 +++++ arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 1 + arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 25 ++ arch/arm/include/asm/arch-rockchip/mipi_rk3399.h | 189 +++++++++ arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 1 + configs/evb-rk3399_defconfig | 12 + drivers/i2c/rk_i2c.c | 1 + drivers/video/Kconfig | 2 + drivers/video/rockchip/Kconfig | 47 +++ drivers/video/rockchip/Makefile | 6 +- drivers/video/rockchip/rk_mipi.c | 465 +++++++++++++++++++++++ drivers/video/rockchip/rk_vop.c | 39 +- 13 files changed, 992 insertions(+), 7 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/mipi_rk3399.h create mode 100644 drivers/video/rockchip/Kconfig create mode 100644 drivers/video/rockchip/rk_mipi.c
To enable mipi display, we need to enable pmic rk808 first for lcd3v3 power,which use i2c0 to communicate with soc. So enable i2c0.
Signed-off-by: Eric Gao eric.gao@rock-chips.com
---
arch/arm/dts/rk3399.dtsi | 16 ++++++++++++++++ configs/evb-rk3399_defconfig | 1 + drivers/i2c/rk_i2c.c | 1 + 3 files changed, 18 insertions(+)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 456fdb6..93e3bf4 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -26,6 +26,7 @@ serial4 = &uart4; mmc0 = &sdhci; mmc1 = &sdmmc; + i2c0 = &i2c0; };
cpus { @@ -651,6 +652,21 @@ status = "disabled"; };
+ i2c0: i2c@ff3c0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3c0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C0_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pinctrl: pinctrl { u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pinctrl"; diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index bedc1fd..2e2f9a8 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -58,3 +58,4 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y CONFIG_ERRNO_STR=y +CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index 7c701cb..a4c8c2ba 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -381,6 +381,7 @@ static const struct dm_i2c_ops rockchip_i2c_ops = {
static const struct udevice_id rockchip_i2c_ids[] = { { .compatible = "rockchip,rk3288-i2c" }, + { .compatible = "rockchip,rk3399-i2c" }, { } };
For using mipi display, we need to enable lcd3v3 which supplied by rk808,so enable rk808 first.
Signed-off-by: Eric Gao eric.gao@rock-chips.com ---
arch/arm/dts/rk3399-evb.dts | 39 +++++++++++++++++++++++++++++++++++++++ configs/evb-rk3399_defconfig | 5 +++++ 2 files changed, 44 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index a959989..7bf805a 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -30,6 +30,13 @@ status = "okay"; };
+ vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vccsys"; + regulator-boot-on; + regulator-always-on; + }; + vcc3v3_sys: vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; @@ -51,6 +58,7 @@ regulator-name = "vcc5v0_host"; gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; }; + };
&emmc_phy { @@ -110,6 +118,37 @@ status = "okay"; };
+&i2c0 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <100>; + u-boot,dm-pre-reloc; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + clock-output-names = "xin32k", "wifibt_32kin"; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + reg = <0x1b>; + rockchip,system-power-controller; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + status = "okay"; + + vcc12-supply = <&vcc3v3_sys>; + regulators { + vcc33_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc33_lcd"; + }; + }; + }; +}; + &pinctrl { pmic { pmic_int_l: pmic-int-l { diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 2e2f9a8..aac6d2d 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -59,3 +59,8 @@ CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y CONFIG_ERRNO_STR=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_CHILDREN=y +CONFIG_SPL_PMIC_CHILDREN=y +CONFIG_PMIC_RK808=y +CONFIG_REGULATOR_RK808=y
On 9 April 2017 at 20:41, Eric Gao eric.gao@rock-chips.com wrote:
For using mipi display, we need to enable lcd3v3 which supplied by rk808,so enable rk808 first.
Signed-off-by: Eric Gao eric.gao@rock-chips.com
arch/arm/dts/rk3399-evb.dts | 39 +++++++++++++++++++++++++++++++++++++++ configs/evb-rk3399_defconfig | 5 +++++ 2 files changed, 44 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On 11 April 2017 at 07:55, Simon Glass sjg@chromium.org wrote:
On 9 April 2017 at 20:41, Eric Gao eric.gao@rock-chips.com wrote:
For using mipi display, we need to enable lcd3v3 which supplied by rk808,so enable rk808 first.
Signed-off-by: Eric Gao eric.gao@rock-chips.com
arch/arm/dts/rk3399-evb.dts | 39 +++++++++++++++++++++++++++++++++++++++ configs/evb-rk3399_defconfig | 5 +++++ 2 files changed, 44 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
Add mipi dsi driver for rk chip, To enable this you need to enable DM, DM_VIDEO, DM_ROCKCHIP_VIDEO, DISPLAY_MIPI in menuconfig. And enable rk808,and it's corresponding i2c.
Signed-off-by: Eric Gao eric.gao@rock-chips.com ---
arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 1 + arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 25 ++ arch/arm/include/asm/arch-rockchip/mipi_rk3399.h | 189 +++++++++ arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 1 + drivers/video/Kconfig | 2 + drivers/video/rockchip/Kconfig | 47 +++ drivers/video/rockchip/Makefile | 6 +- drivers/video/rockchip/rk_mipi.c | 465 +++++++++++++++++++++++ drivers/video/rockchip/rk_vop.c | 39 +- 9 files changed, 768 insertions(+), 7 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/mipi_rk3399.h create mode 100644 drivers/video/rockchip/Kconfig create mode 100644 drivers/video/rockchip/rk_mipi.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index cf830d0..e9e5810 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -70,6 +70,7 @@ struct rk3399_cru { }; check_member(rk3399_cru, sdio1_con[1], 0x594); #define MHz 1000000 +#define MHZ 1000000 #define KHz 1000 #define OSC_HZ (24*MHz) #define APLL_HZ (600*MHz) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index 62d8496..2bf58da 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -399,6 +399,31 @@ enum { GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, GRF_UART_DBG_SEL_C = 2,
+ /* GRF_SOC_CON20 */ + GRF_DSI0_VOP_SEL_SHIFT = 0, + GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT, + GRF_DSI0_VOP_SEL_B = 0, + GRF_DSI0_VOP_SEL_L, + + /* GRF_SOC_CON22 */ + GRF_DPHY_TX0_RXMODE_SHIFT = 0, + GRF_DPHY_TX0_RXMODE_MASK = + 0xf << GRF_DPHY_TX0_RXMODE_SHIFT, + GRF_DPHY_TX0_RXMODE_EN = 0xb, + GRF_DPHY_TX0_RXMODE_DIS = 0, + + GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4, + GRF_DPHY_TX0_TXSTOPMODE_MASK = + 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT, + GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc, + GRF_DPHY_TX0_TXSTOPMODE_DIS = 0, + + GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12, + GRF_DPHY_TX0_TURNREQUEST_MASK = + 0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT, + GRF_DPHY_TX0_TURNREQUEST_EN = 0x1, + GRF_DPHY_TX0_TURNREQUEST_DIS = 0, + /* PMUGRF_GPIO0A_IOMUX */ PMUGRF_GPIO0A6_SEL_SHIFT = 12, PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT, diff --git a/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h new file mode 100644 index 0000000..9a1fffb --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2017-2025 Fuzhou Rockchip Electronics Co., Ltd + * author: eric.gao@rock-chips.com + * create date: 2017-03-31 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef RK33_MIPI_DSI_H +#define RK33_MIPI_DSI_H + +/* + * All these mipi controller register declaration provide + * reg address offset, bits width, bit offset for a + * specified register bits. With these message, we can + * set or clear every bits individually for a 32bit width + * register. We use DSI_HOST_BITS macro definition to + * combinat these message using the following format: + * val(32bit) = addr(16bit) | width(8bit) | offest(8bit) + * for example: + * #define SHUTDOWNZ DSI_HOST_BITS(0X004, 1, 0) + * means SHUTDOWNZ is a signal reg bit with bit offset + * qual 0,and it's reg addr offset is 0x004.The conbinat + * result = (0x004 << 16) | (1 << 8) | 0 + */ +#define DSI_HOST_BITS(addr, bits, bit_offset) \ + ((addr<<16) | (bits<<8) | (bit_offset)) + +/* DWC_DSI_VERSION_0X3133302A */ +#define VERSION DSI_HOST_BITS(0X000, 32, 0) +#define SHUTDOWNZ DSI_HOST_BITS(0X004, 1, 0) +#define TO_CLK_DIVISION DSI_HOST_BITS(0X008, 8, 8) +#define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0X008, 8, 0) +#define DPI_VCID DSI_HOST_BITS(0X00C, 2, 0) +#define EN18_LOOSELY DSI_HOST_BITS(0X010, 1, 8) +#define DPI_COLOR_CODING DSI_HOST_BITS(0X010, 4, 0) +#define COLORM_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 4) +#define SHUTD_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 3) +#define HSYNC_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 2) +#define VSYNC_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 1) +#define DATAEN_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 0) +#define OUTVACT_LPCMD_TIME DSI_HOST_BITS(0X018, 8, 16) +#define INVACT_LPCMD_TIME DSI_HOST_BITS(0X018, 8, 0) +#define CRC_RX_EN DSI_HOST_BITS(0X02C, 1, 4) +#define ECC_RX_EN DSI_HOST_BITS(0X02C, 1, 3) +#define BTA_EN DSI_HOST_BITS(0X02C, 1, 2) +#define EOTP_RX_EN DSI_HOST_BITS(0X02C, 1, 1) +#define EOTP_TX_EN DSI_HOST_BITS(0X02C, 1, 0) +#define GEN_VID_RX DSI_HOST_BITS(0X030, 2, 0) +#define CMD_VIDEO_MODE DSI_HOST_BITS(0X034, 1, 0) +#define VPG_ORIENTATION DSI_HOST_BITS(0X038, 1, 24) +#define VPG_MODE DSI_HOST_BITS(0X038, 1, 20) +#define VPG_EN DSI_HOST_BITS(0X038, 1, 16) +#define LP_CMD_EN DSI_HOST_BITS(0X038, 1, 15) +#define FRAME_BTA_ACK_EN DSI_HOST_BITS(0X038, 1, 14) +#define LP_HFP_EN DSI_HOST_BITS(0X038, 1, 13) +#define LP_HBP_EN DSI_HOST_BITS(0X038, 1, 12) +#define LP_VACT_EN DSI_HOST_BITS(0X038, 1, 11) +#define LP_VFP_EN DSI_HOST_BITS(0X038, 1, 10) +#define LP_VBP_EN DSI_HOST_BITS(0X038, 1, 9) +#define LP_VSA_EN DSI_HOST_BITS(0X038, 1, 8) +#define VID_MODE_TYPE DSI_HOST_BITS(0X038, 2, 0) +#define VID_PKT_SIZE DSI_HOST_BITS(0X03C, 14, 0) +#define NUM_CHUNKS DSI_HOST_BITS(0X040, 13, 0) +#define NULL_PKT_SIZE DSI_HOST_BITS(0X044, 13, 0) +#define VID_HSA_TIME DSI_HOST_BITS(0X048, 12, 0) +#define VID_HBP_TIME DSI_HOST_BITS(0X04C, 12, 0) +#define VID_HLINE_TIME DSI_HOST_BITS(0X050, 15, 0) +#define VID_VSA_LINES DSI_HOST_BITS(0X054, 10, 0) +#define VID_VBP_LINES DSI_HOST_BITS(0X058, 10, 0) +#define VID_VFP_LINES DSI_HOST_BITS(0X05C, 10, 0) +#define VID_ACTIVE_LINES DSI_HOST_BITS(0X060, 14, 0) +#define EDPI_CMD_SIZE DSI_HOST_BITS(0X064, 16, 0) +#define MAX_RD_PKT_SIZE DSI_HOST_BITS(0X068, 1, 24) +#define DCS_LW_TX DSI_HOST_BITS(0X068, 1, 19) +#define DCS_SR_0P_TX DSI_HOST_BITS(0X068, 1, 18) +#define DCS_SW_1P_TX DSI_HOST_BITS(0X068, 1, 17) +#define DCS_SW_0P_TX DSI_HOST_BITS(0X068, 1, 16) +#define GEN_LW_TX DSI_HOST_BITS(0X068, 1, 14) +#define GEN_SR_2P_TX DSI_HOST_BITS(0X068, 1, 13) +#define GEN_SR_1P_TX DSI_HOST_BITS(0X068, 1, 12) +#define GEN_SR_0P_TX DSI_HOST_BITS(0X068, 1, 11) +#define GEN_SW_2P_TX DSI_HOST_BITS(0X068, 1, 10) +#define GEN_SW_1P_TX DSI_HOST_BITS(0X068, 1, 9) +#define GEN_SW_0P_TX DSI_HOST_BITS(0X068, 1, 8) +#define ACK_RQST_EN DSI_HOST_BITS(0X068, 1, 1) +#define TEAR_FX_EN DSI_HOST_BITS(0X068, 1, 0) +#define GEN_WC_MSBYTE DSI_HOST_BITS(0X06C, 14, 16) +#define GEN_WC_LSBYTE DSI_HOST_BITS(0X06C, 8, 8) +#define GEN_VC DSI_HOST_BITS(0X06C, 2, 6) +#define GEN_DT DSI_HOST_BITS(0X06C, 6, 0) +#define GEN_PLD_DATA DSI_HOST_BITS(0X070, 32, 0) +#define GEN_RD_CMD_BUSY DSI_HOST_BITS(0X074, 1, 6) +#define GEN_PLD_R_FULL DSI_HOST_BITS(0X074, 1, 5) +#define GEN_PLD_R_EMPTY DSI_HOST_BITS(0X074, 1, 4) +#define GEN_PLD_W_FULL DSI_HOST_BITS(0X074, 1, 3) +#define GEN_PLD_W_EMPTY DSI_HOST_BITS(0X074, 1, 2) +#define GEN_CMD_FULL DSI_HOST_BITS(0X074, 1, 1) +#define GEN_CMD_EMPTY DSI_HOST_BITS(0X074, 1, 0) +#define HSTX_TO_CNT DSI_HOST_BITS(0X078, 16, 16) +#define LPRX_TO_CNT DSI_HOST_BITS(0X078, 16, 0) +#define HS_RD_TO_CNT DSI_HOST_BITS(0X07C, 16, 0) +#define LP_RD_TO_CNT DSI_HOST_BITS(0X080, 16, 0) +#define PRESP_TO_MODE DSI_HOST_BITS(0X084, 1, 24) +#define HS_WR_TO_CNT DSI_HOST_BITS(0X084, 16, 0) +#define LP_WR_TO_CNT DSI_HOST_BITS(0X088, 16, 0) +#define BTA_TO_CNT DSI_HOST_BITS(0X08C, 16, 0) +#define AUTO_CLKLANE_CTRL DSI_HOST_BITS(0X094, 1, 1) +#define PHY_TXREQUESTCLKHS DSI_HOST_BITS(0X094, 1, 0) +#define PHY_HS2LP_TIME_CLK_LANE DSI_HOST_BITS(0X098, 10, 16) +#define PHY_HS2HS_TIME_CLK_LANE DSI_HOST_BITS(0X098, 10, 0) +#define PHY_HS2LP_TIME DSI_HOST_BITS(0X09C, 8, 24) +#define PHY_LP2HS_TIME DSI_HOST_BITS(0X09C, 8, 16) +#define MAX_RD_TIME DSI_HOST_BITS(0X09C, 15, 0) +#define PHY_FORCEPLL DSI_HOST_BITS(0X0A0, 1, 3) +#define PHY_ENABLECLK DSI_HOST_BITS(0X0A0, 1, 2) +#define PHY_RSTZ DSI_HOST_BITS(0X0A0, 1, 1) +#define PHY_SHUTDOWNZ DSI_HOST_BITS(0X0A0, 1, 0) +#define PHY_STOP_WAIT_TIME DSI_HOST_BITS(0X0A4, 8, 8) +#define N_LANES DSI_HOST_BITS(0X0A4, 2, 0) +#define PHY_TXEXITULPSLAN DSI_HOST_BITS(0X0A8, 1, 3) +#define PHY_TXREQULPSLAN DSI_HOST_BITS(0X0A8, 1, 2) +#define PHY_TXEXITULPSCLK DSI_HOST_BITS(0X0A8, 1, 1) +#define PHY_TXREQULPSCLK DSI_HOST_BITS(0X0A8, 1, 0) +#define PHY_TX_TRIGGERS DSI_HOST_BITS(0X0AC, 4, 0) +#define PHYSTOPSTATECLKLANE DSI_HOST_BITS(0X0B0, 1, 2) +#define PHYLOCK DSI_HOST_BITS(0X0B0, 1, 0) +#define PHY_TESTCLK DSI_HOST_BITS(0X0B4, 1, 1) +#define PHY_TESTCLR DSI_HOST_BITS(0X0B4, 1, 0) +#define PHY_TESTEN DSI_HOST_BITS(0X0B8, 1, 16) +#define PHY_TESTDOUT DSI_HOST_BITS(0X0B8, 8, 8) +#define PHY_TESTDIN DSI_HOST_BITS(0X0B8, 8, 0) +#define PHY_TEST_CTRL1 DSI_HOST_BITS(0X0B8, 17, 0) +#define PHY_TEST_CTRL0 DSI_HOST_BITS(0X0B4, 2, 0) +#define INT_ST0 DSI_HOST_BITS(0X0BC, 21, 0) +#define INT_ST1 DSI_HOST_BITS(0X0C0, 18, 0) +#define INT_MKS0 DSI_HOST_BITS(0X0C4, 21, 0) +#define INT_MKS1 DSI_HOST_BITS(0X0C8, 18, 0) +#define INT_FORCE0 DSI_HOST_BITS(0X0D8, 21, 0) +#define INT_FORCE1 DSI_HOST_BITS(0X0DC, 18, 0) + +#define CODE_HS_RX_CLOCK 0X34 +#define CODE_HS_RX_LANE0 0X44 +#define CODE_HS_RX_LANE1 0X54 +#define CODE_HS_RX_LANE2 0X84 +#define CODE_HS_RX_LANE3 0X94 + +#define CODE_PLL_INPUT_DIV_RAT 0X17 +#define CODE_PLL_LOOP_DIV_RAT 0X18 +#define CODE_PLL_VCORANGE_VCOCAP 0X10 +#define CODE_PLL_INPUT_LOOP_DIV_RAT 0X19 +#define CODE_PLL_CPCTRL 0X11 + +#define CODE_HSTXDATALANEREQUSETSTATETIME 0X70 +#define CODE_HSTXDATALANEPREPARESTATETIME 0X71 +#define CODE_HSTXDATALANEHSZEROSTATETIME 0X72 + +enum vid_mode_type_t { + NON_BURST_SYNC_PLUSE = 0, + NON_BURST_SYNC_EVENT, + BURST_MODE, +}; + +enum cmd_video_mode { + VIDEO_MODE = 0, + CMD_MODE, +}; + +enum dpi_color_coding { + DPI_16BIT_CFG_1 = 0, + DPI_16BIT_CFG_2, + DPI_16BIT_CFG_3, + DPI_18BIT_CFG_1, + DPI_18BIT_CFG_2, + DPI_24BIT, + DPI_20BIT_YCBCR_422_LP, + DPI_24BIT_YCBCR_422, + DPI_16BIT_YCBCR_422, + DPI_30BIT, + DPI_36BIT, + DPI_12BIT_YCBCR_420, +}; + +enum vop_id { + VOP_B = 0, + VOP_L, +}; + +#endif /* end of RK33_MIPI_DSI_H */ diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h index 0ce3d67..d5599ec 100644 --- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h @@ -90,6 +90,7 @@ enum vop_modes { VOP_MODE_EDP = 0, VOP_MODE_HDMI, VOP_MODE_LVDS, + VOP_MODE_MIPI, VOP_MODE_NONE, VOP_MODE_AUTO_DETECT, VOP_MODE_UNKNOWN, diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2069576..4b03a9a 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -405,6 +405,8 @@ config VIDEO_ROCKCHIP (DSI). This driver supports the on-chip video output device, and targets the Rockchip RK3288.
+source "drivers/video/rockchip/Kconfig" + config VIDEO_SANDBOX_SDL bool "Enable sandbox video console using SDL" depends on SANDBOX diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig new file mode 100644 index 0000000..674034b --- /dev/null +++ b/drivers/video/rockchip/Kconfig @@ -0,0 +1,47 @@ +# +# video drivers selection for rockchip soc, these +# configs only impact the compile process. you can +# surely check all the options.In this case,all the +# display driver will be compiled, but which port +# finally be used is decided by dts configuration. +# + +menu "Video Display Port" + +config DISPLAY_MIPI + bool "MIPI Port" + depends on VIDEO_ROCKCHIP + help + Involve MIPI dsi for video port. + if you want to enable these function,you need + to turn on the DM_VIDEO,VDEIO_ROCKCHIP together + what is more,you shoud also enable the related + power,such as lcd3v3, lcd1v8,lcd1v0 and so on. +config DISPLAY_EDP + bool "EDP Port" + depends on VIDEO_ROCKCHIP + help + Involve EDP for video port. + if you want to enable these function,you need + to turn on the DM_VIDEO,VDEIO_ROCKCHIP together + what is more,you shoud also enable the related + power,such as lcd3v3, lcd1v8,lcd1v0 and so on. +config DISPLAY_LVDS + bool "LVDS Port" + depends on VIDEO_ROCKCHIP + help + Involve LVDS for video port. + if you want to enable these function,you need + to turn on the DM_VIDEO,VDEIO_ROCKCHIP together + what is more,you shoud also enable the related + power,such as lcd3v3, lcd1v8,lcd1v0 and so on. +config DISPLAY_HDMI + bool "HDMI port" + depends on VIDEO_ROCKCHIP + help + Involve HDMI for video port + if you want to enable these function,you need + to turn on the DM_VIDEO,VDEIO_ROCKCHIP together + what is more,you shoud also enable the related + power,such as lcd3v3, lcd1v8,lcd1v0 and so on. +endmenu diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index 7962f86..a14db04 100644 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -5,4 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o +obj-$(CONFIG_VIDEO_ROCKCHIP) += rk_vop.o +obj-$(CONFIG_DISPLAY_MIPI) += rk_mipi.o +obj-$(CONFIG_DISPLAY_EDP) += rk_edp.o +obj-$(CONFIG_DISPLAY_LVDS) += rk_lvds.o +obj-$(CONFIG_DISPLAY_HDMI) += rk_hdmi.o diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c new file mode 100644 index 0000000..a2c2a28 --- /dev/null +++ b/drivers/video/rockchip/rk_mipi.c @@ -0,0 +1,465 @@ +/* + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the SPDX General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#define DEBUG +#include <common.h> +#include <clk.h> +#include <display.h> +#include <dm.h> +#include <fdtdec.h> +#include <panel.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/hardware.h> +#include <asm/arch/mipi_rk3399.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3399.h> +#include <asm/arch/cru_rk3399.h> +#include <linux/kernel.h> +#include <dt-bindings/clock/rk3288-cru.h> +#include <dm/uclass-internal.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct mipi_dsi { + u32 ref_clk; + u32 sys_clk; + u32 pix_clk; + u32 phy_clk; + u32 txbyte_clk; + u32 txesc_clk; +}; + +struct rk_mipi_priv { + void __iomem *regs; + struct rk3399_grf_regs *grf; + struct udevice *panel; + struct mipi_dsi *dsi; +}; + +static int rk_mipi_read_timing(struct udevice *dev, + struct display_timing *timing) +{ + if (fdtdec_decode_display_timing + (gd->fdt_blob, dev_of_offset(dev), 0, timing)) { + debug("%s: Failed to decode display timing\n", __func__); + return -EINVAL; + } + + return 0; +} +/* + * register write function used only for mipi dsi controller. + * parameter: + * reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) + * you can use define in rk_mipi.h directly for this parameter + * val: value that will be write to specified bits of register + */ +static void rk_mipi_dsi_write(struct udevice *dev, u32 reg, u32 val) +{ + #define OFFSET (reg & 0xff) + #define BITS ((reg >> 8) & 0xff) + #define ADDR ((reg >> 16) + priv->regs) + + u32 dat; + u32 mask; + struct rk_mipi_priv *priv = dev_get_priv(dev); + + /* Mask for specifiled bits,the corresponding bits will be clear */ + mask = (~((0xffffffff << OFFSET) & + (0xffffffff >> (32 - OFFSET - BITS)))); + + /* Make sure val in the available range */ + val &= (~(0xffffffff << BITS)); + + /* Get register's original val */ + dat = readl(ADDR); + + /* Clear specified bits */ + dat &= mask; + + /* Fill specified bits */ + dat |= (val << OFFSET); + + writel(dat, ADDR); +} + +static int rk_mipi_dsi_enable(struct udevice *dev, + const struct display_timing *timing) +{ + int node, timing_node; + int val; + struct rk_mipi_priv *priv = dev_get_priv(dev); + struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); + u32 txbyte_clk = priv->dsi->txbyte_clk; + u32 txesc_clk = priv->dsi->txesc_clk; + + txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1); + + /* Select the video source */ + switch (disp_uc_plat->source_id) { + case VOP_B: + rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, + GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT); + break; + case VOP_L: + rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, + GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT); + break; + default: + return -EINVAL; + } + + /* Set Controller as TX mode */ + val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT; + rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val); + + /* Exit tx stop mode */ + val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT; + rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val); + + /* Disable turnequest */ + val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT; + rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val); + + /* Set Display timing parameter */ + rk_mipi_dsi_write(dev, VID_HSA_TIME, timing->hsync_len.typ); + rk_mipi_dsi_write(dev, VID_HBP_TIME, timing->hback_porch.typ); + rk_mipi_dsi_write(dev, VID_HLINE_TIME, + (timing->hsync_len.typ + + timing->hback_porch.typ + + timing->hactive.typ + + timing->hfront_porch.typ)); + rk_mipi_dsi_write(dev, VID_VSA_LINES, timing->vsync_len.typ); + rk_mipi_dsi_write(dev, VID_VBP_LINES, timing->vback_porch.typ); + rk_mipi_dsi_write(dev, VID_VFP_LINES, timing->vfront_porch.typ); + rk_mipi_dsi_write(dev, VID_ACTIVE_LINES, timing->vactive.typ); + + /* Set Signal Polarity */ + val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0; + rk_mipi_dsi_write(dev, HSYNC_ACTIVE_LOW, val); + + val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0; + rk_mipi_dsi_write(dev, VSYNC_ACTIVE_LOW, val); + + val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0; + rk_mipi_dsi_write(dev, DISPLAY_FLAGS_DE_LOW, val); + + val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0; + rk_mipi_dsi_write(dev, COLORM_ACTIVE_LOW, val); + + /* Set video mode */ + rk_mipi_dsi_write(dev, CMD_VIDEO_MODE, VIDEO_MODE); + + /* Set video mode transmission type as burst mode */ + rk_mipi_dsi_write(dev, VID_MODE_TYPE, BURST_MODE); + + /* Set pix num in a video package */ + rk_mipi_dsi_write(dev, VID_PKT_SIZE, 0x4b0); + + /* Set dpi color coding depth 24 bit */ + timing_node = fdt_subnode_offset(gd->fdt_blob, + dev_of_offset(dev), "display-timings"); + node = fdt_first_subnode(gd->fdt_blob, timing_node); + val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1); + switch (val) { + case 16: + rk_mipi_dsi_write(dev, DPI_COLOR_CODING, DPI_16BIT_CFG_1); + break; + case 24: + rk_mipi_dsi_write(dev, DPI_COLOR_CODING, DPI_24BIT); + break; + case 30: + rk_mipi_dsi_write(dev, DPI_COLOR_CODING, DPI_30BIT); + break; + default: + rk_mipi_dsi_write(dev, DPI_COLOR_CODING, DPI_24BIT); + } + /* Enable low power mode */ + rk_mipi_dsi_write(dev, LP_CMD_EN, 1); + rk_mipi_dsi_write(dev, LP_HFP_EN, 1); + rk_mipi_dsi_write(dev, LP_VACT_EN, 1); + rk_mipi_dsi_write(dev, LP_VFP_EN, 1); + rk_mipi_dsi_write(dev, LP_VBP_EN, 1); + rk_mipi_dsi_write(dev, LP_VSA_EN, 1); + + /* Division for timeout counter clk */ + rk_mipi_dsi_write(dev, TO_CLK_DIVISION, 0x0a); + + /* Tx esc clk division from txbyte clk */ + rk_mipi_dsi_write(dev, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk); + + /* + * Timeout count for hs<->lp + * transation between Line period + */ + rk_mipi_dsi_write(dev, HSTX_TO_CNT, 0x3e8); + + /* Phy State transfer timing */ + rk_mipi_dsi_write(dev, PHY_STOP_WAIT_TIME, 32); + rk_mipi_dsi_write(dev, PHY_TXREQUESTCLKHS, 1); + rk_mipi_dsi_write(dev, PHY_HS2LP_TIME, 0x14); + rk_mipi_dsi_write(dev, PHY_LP2HS_TIME, 0x10); + rk_mipi_dsi_write(dev, MAX_RD_TIME, 0x2710); + + /* Power on */ + rk_mipi_dsi_write(dev, SHUTDOWNZ, 1); + + return 0; +} + +/* + * rk mipi dphy write function + */ +static void rk_mipi_phy_write(struct udevice *dev, unsigned char test_code, + unsigned char *test_data, unsigned char size) +{ + int i = 0; + /* Write Test code */ + rk_mipi_dsi_write(dev, PHY_TESTCLK, 1); + rk_mipi_dsi_write(dev, PHY_TESTDIN, test_code); + rk_mipi_dsi_write(dev, PHY_TESTEN, 1); + rk_mipi_dsi_write(dev, PHY_TESTCLK, 0); + rk_mipi_dsi_write(dev, PHY_TESTEN, 0); + + /* Write Test data */ + for (i = 0; i < size; i++) { + rk_mipi_dsi_write(dev, PHY_TESTCLK, 0); + rk_mipi_dsi_write(dev, PHY_TESTDIN, test_data[i]); + rk_mipi_dsi_write(dev, PHY_TESTCLK, 1); + } +} + +/* + * mipi dphy config function. calculate the suitable prediv, + * feedback div,fsfreqrang value ,cap ,lpf and so on + * according to the given pix clk ratthe.and then enable phy + */ +static int rk_mipi_phy_enable(struct udevice *dev) +{ + int i; + struct rk_mipi_priv *priv = dev_get_priv(dev); + u64 fbdiv; + u64 prediv = 1; + u64 ddr_clk = priv->dsi->phy_clk; + u32 refclk = priv->dsi->ref_clk; + u32 remain = refclk; + unsigned char test_data[2] = {0}; + + /* + * dphy fsfreqrang + * different dphy config is needed for diffenect freq rang + * here list the config-freq relation + */ + int freq_rang[][2] = { + {90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01}, + {140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12}, + {200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23}, + {270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15}, + {400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07}, + {600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09}, + {800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a}, + {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, + {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, + {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} + }; + + /* Shutdown mode */ + rk_mipi_dsi_write(dev, PHY_SHUTDOWNZ, 0); + rk_mipi_dsi_write(dev, PHY_RSTZ, 0); + rk_mipi_dsi_write(dev, PHY_TESTCLR, 1); + + /* Pll locking */ + rk_mipi_dsi_write(dev, PHY_TESTCLR, 0); + + /* config cp and lfp */ + test_data[0] = 0x80 | (ddr_clk / (200*MHZ)) << 3 | 0x3; + rk_mipi_phy_write(dev, 0x10, test_data, 1); + + test_data[0] = 0x8; + rk_mipi_phy_write(dev, 0x11, test_data, 1); + + test_data[0] = 0x80 | 0x40; + rk_mipi_phy_write(dev, 0x12, test_data, 1); + + /* select the suitable value for fsfreqrang reg */ + for (i = 0; i < ARRAY_SIZE(freq_rang); i++) { + if (ddr_clk / (MHZ) >= freq_rang[i][0]) + break; + } + test_data[0] = freq_rang[i][1] << 1; + rk_mipi_phy_write(dev, CODE_HS_RX_LANE0, test_data, 1); + + /* + * Calculate the best ddrclk and it's + * corresponding div value, If the given + * pixelclock is great than 250M, the ddr + * clk will be fix 1500M.otherwise , it's + * equal to ddr_clk= pixclk*6. + * 40MHZ>=refclk/prediv>=5MHZ according to spec + */ + #define MAX_FBDIV 512 + #define MAX_PREDIV (refclk/(5*MHZ)) + #define MIN_PREDIV ((refclk/(40*MHZ)) ? (refclk/(40*MHZ) + 1) : 1) + + debug("DEBUG: MAX_PREDIV=%u, MIN_PREDIV=%u\n", MAX_PREDIV, MIN_PREDIV); + + if (MAX_PREDIV < MIN_PREDIV) { + debug("Err: Invalid refclk value@%s\n", __func__); + return -EINVAL; + } + + for (i = MIN_PREDIV; i < MAX_PREDIV; i++) { + if ((ddr_clk * i % refclk < remain) && + (ddr_clk * i / refclk) < MAX_FBDIV) { + prediv = i; + remain = ddr_clk * i % refclk; + } + } + fbdiv = ddr_clk * prediv / refclk; + ddr_clk = refclk * fbdiv / prediv; + priv->dsi->phy_clk = ddr_clk; + + debug("DEBUG:refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n", + refclk, prediv, fbdiv, ddr_clk); + + /* config prediv and feedback reg */ + test_data[0] = prediv - 1; + rk_mipi_phy_write(dev, CODE_PLL_INPUT_DIV_RAT, test_data, 1); + test_data[0] = (fbdiv - 1) & 0x1f; + rk_mipi_phy_write(dev, CODE_PLL_LOOP_DIV_RAT, test_data, 1); + test_data[0] = (fbdiv - 1) >> 5 | 0x80; + rk_mipi_phy_write(dev, CODE_PLL_LOOP_DIV_RAT, test_data, 1); + test_data[0] = 0x30; + rk_mipi_phy_write(dev, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1); + + /* rest config */ + test_data[0] = 0x4d; + rk_mipi_phy_write(dev, 0x20, test_data, 1); + + test_data[0] = 0x3d; + rk_mipi_phy_write(dev, 0x21, test_data, 1); + + test_data[0] = 0xdf; + rk_mipi_phy_write(dev, 0x21, test_data, 1); + + test_data[0] = 0x7; + rk_mipi_phy_write(dev, 0x22, test_data, 1); + + test_data[0] = 0x80 | 0x7; + rk_mipi_phy_write(dev, 0x22, test_data, 1); + + test_data[0] = 0x80 | 15; + rk_mipi_phy_write(dev, CODE_HSTXDATALANEREQUSETSTATETIME, + test_data, 1); + test_data[0] = 0x80 | 85; + rk_mipi_phy_write(dev, CODE_HSTXDATALANEPREPARESTATETIME, + test_data, 1); + test_data[0] = 0x40 | 10; + rk_mipi_phy_write(dev, CODE_HSTXDATALANEHSZEROSTATETIME, + test_data, 1); + + /* enter into stop mode */ + rk_mipi_dsi_write(dev, N_LANES, 0x03); + rk_mipi_dsi_write(dev, PHY_ENABLECLK, 1); + rk_mipi_dsi_write(dev, PHY_FORCEPLL, 1); + rk_mipi_dsi_write(dev, PHY_SHUTDOWNZ, 1); + rk_mipi_dsi_write(dev, PHY_RSTZ, 1); + + return 0; +} + +static int rk_mipi_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *timing) +{ + return 0; +} + +static int rk_mipi_ofdata_to_platdata(struct udevice *dev) +{ + struct rk_mipi_priv *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->regs = (void *)dev_get_addr(dev); + + return 0; +} + +/* + * probe function: check panel existence and reading + * it's timing. then config mipi dsi controller and + * enable it according to the timing parameter + */ +static int rk_mipi_probe(struct udevice *dev) +{ + struct rk_mipi_priv *priv = dev_get_priv(dev); + struct display_timing timing; + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel", + &priv->panel); + if (ret) { + debug("Err:Can't find panel@%s, ret = %d\n", __func__, ret); + return -ENODEV; + } + /* Read panel timing,and save to struct timing */ + rk_mipi_read_timing(dev, &timing); + + /* fill the mipi controller parameter */ + priv->dsi->ref_clk = 24*MHZ; + priv->dsi->sys_clk = priv->dsi->ref_clk; + priv->dsi->pix_clk = timing.pixelclock.typ; + priv->dsi->phy_clk = priv->dsi->pix_clk * 6; + priv->dsi->txbyte_clk = priv->dsi->phy_clk / 8; + priv->dsi->txesc_clk = 20*MHZ; + + /* config mipi dsi according to timing and enable it */ + ret = rk_mipi_dsi_enable(dev, &timing); + if (ret) { + debug("Err: mipi dsi enable fail@%s,ret=%d\n", __func__, ret); + return ret; + } + + /* init mipi dsi phy */ + ret = rk_mipi_phy_enable(dev); + if (ret) { + debug("Err: mipi phy enable fail@%s,ret=%d\n", __func__, ret); + return ret; + } + + /* enable backlight */ + ret = panel_enable_backlight(priv->panel); + if (ret) { + debug("Err: fail to enable bg@%s,ret=%d\n", __func__, ret); + return ret; + } + + return 0; +} + +static const struct dm_display_ops rk_mipi_dsi_ops = { + .read_timing = rk_mipi_read_timing, + .enable = rk_mipi_enable, +}; + +static const struct udevice_id rk_mipi_dsi_ids[] = { + { .compatible = "rockchip,rk3399_mipi_dsi" }, + { } +}; + +U_BOOT_DRIVER(rk_mipi_dsi) = { + .name = "rk_mipi_dsi", + .id = UCLASS_DISPLAY, + .of_match = rk_mipi_dsi_ids, + .ofdata_to_platdata = rk_mipi_ofdata_to_platdata, + .probe = rk_mipi_probe, + .ops = &rk_mipi_dsi_ops, + .priv_auto_alloc_size = sizeof(struct rk_mipi_priv), +}; diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index aeecb58..e833eb5 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -109,6 +109,10 @@ void rkvop_mode_set(struct rk3288_vop *regs, clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); break; + case VOP_MODE_MIPI: + clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, + V_MIPI_OUT_EN(1)); + break; case VOP_MODE_EDP: default: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, @@ -178,13 +182,11 @@ void rkvop_mode_set(struct rk3288_vop *regs, * * @dev: VOP device that we want to connect to the display * @fbbase: Frame buffer address - * @l2bpp Log2 of bits-per-pixels for the display * @ep_node: Device tree node to process - this is the offset of an endpoint * node within the VOP's 'port' list. * @return 0 if OK, -ve if something went wrong */ -int rk_display_init(struct udevice *dev, ulong fbbase, - enum video_log2_bpp l2bpp, int ep_node) +int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node) { struct video_priv *uc_priv = dev_get_uclass_priv(dev); const void *blob = gd->fdt_blob; @@ -196,6 +198,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase, int ret, remote, i, offset; struct display_plat *disp_uc_plat; struct clk clk; + enum video_log2_bpp l2bpp;
vop_id = fdtdec_get_int(blob, ep_node, "reg", -1); debug("vop_id=%d\n", vop_id); @@ -245,11 +248,26 @@ int rk_display_init(struct udevice *dev, ulong fbbase, ret = clk_get_by_index(dev, 1, &clk); if (!ret) ret = clk_set_rate(&clk, timing.pixelclock.typ); - if (ret) { + /* clk_set_rate return clk rate,normally it is a none zero value */ + if (!ret) { debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret); return ret; }
+ /* Set bitwidth for vop display according to vop mode */ + switch (vop_id) { + case VOP_MODE_EDP: + case VOP_MODE_HDMI: + case VOP_MODE_LVDS: + l2bpp = VIDEO_BPP16; + break; + case VOP_MODE_MIPI: + l2bpp = VIDEO_BPP32; + break; + default: + l2bpp = VIDEO_BPP16; + } + rkvop_mode_set(regs, &timing, vop_id);
rkvop_enable(regs, fbbase, 1 << l2bpp, &timing); @@ -327,7 +345,7 @@ static int rk_vop_probe(struct udevice *dev) for (node = fdt_first_subnode(blob, port); node > 0; node = fdt_next_subnode(blob, node)) { - ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node); + ret = rk_display_init(dev, plat->base, node); if (ret) debug("Device failed: ret=%d\n", ret); if (!ret) @@ -342,7 +360,14 @@ static int rk_vop_bind(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
- plat->size = 1920 * 1080 * 2; + /* + * plat->size is only used for reserve fb space in memory befor + * relocation. So we just need to make sure it's big enough for + * all condition. And actually, we now know nothing about the + * display port type, color depth and it's resolution ratio. + * So, we can't calculat fb size accurately. + */ + plat->size = 1920 * 1200 * 4;
return 0; } @@ -351,6 +376,8 @@ static const struct video_ops rk_vop_ops = { };
static const struct udevice_id rk_vop_ids[] = { + { .compatible = "rockchip,rk3399-vop-big" }, + { .compatible = "rockchip,rk3399-vop-lit" }, { .compatible = "rockchip,rk3288-vop" }, { } };
Hi Eric,
On 9 April 2017 at 20:41, Eric Gao eric.gao@rock-chips.com wrote:
Add mipi dsi driver for rk chip, To enable this you need to enable DM, DM_VIDEO, DM_ROCKCHIP_VIDEO, DISPLAY_MIPI in menuconfig. And enable rk808,and it's corresponding i2c.
General comment:
Can you please format your commit message, comments and code to use up more of the 80 columns?
Git commit messages should be word-wrapped to <=75 columns I think (so that git log looks right in 80 columns). Comments, etc. should be <=80 cols.
Kconfig also should use more of the width.
Set your editor to show a line at 80cols!
Signed-off-by: Eric Gao eric.gao@rock-chips.com
arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 1 + arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 25 ++ arch/arm/include/asm/arch-rockchip/mipi_rk3399.h | 189 +++++++++ arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 1 + drivers/video/Kconfig | 2 + drivers/video/rockchip/Kconfig | 47 +++ drivers/video/rockchip/Makefile | 6 +- drivers/video/rockchip/rk_mipi.c | 465 +++++++++++++++++++++++ drivers/video/rockchip/rk_vop.c | 39 +- 9 files changed, 768 insertions(+), 7 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/mipi_rk3399.h create mode 100644 drivers/video/rockchip/Kconfig create mode 100644 drivers/video/rockchip/rk_mipi.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index cf830d0..e9e5810 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -70,6 +70,7 @@ struct rk3399_cru { }; check_member(rk3399_cru, sdio1_con[1], 0x594); #define MHz 1000000 +#define MHZ 1000000 #define KHz 1000 #define OSC_HZ (24*MHz) #define APLL_HZ (600*MHz) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index 62d8496..2bf58da 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -399,6 +399,31 @@ enum { GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, GRF_UART_DBG_SEL_C = 2,
/* GRF_SOC_CON20 */GRF_DSI0_VOP_SEL_SHIFT = 0,GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT,GRF_DSI0_VOP_SEL_B = 0,GRF_DSI0_VOP_SEL_L,/* GRF_SOC_CON22 */GRF_DPHY_TX0_RXMODE_SHIFT = 0,GRF_DPHY_TX0_RXMODE_MASK =0xf << GRF_DPHY_TX0_RXMODE_SHIFT,GRF_DPHY_TX0_RXMODE_EN = 0xb,GRF_DPHY_TX0_RXMODE_DIS = 0,GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,GRF_DPHY_TX0_TXSTOPMODE_MASK =0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc,GRF_DPHY_TX0_TXSTOPMODE_DIS = 0,GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,GRF_DPHY_TX0_TURNREQUEST_MASK =0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,GRF_DPHY_TX0_TURNREQUEST_EN = 0x1,GRF_DPHY_TX0_TURNREQUEST_DIS = 0,/* PMUGRF_GPIO0A_IOMUX */ PMUGRF_GPIO0A6_SEL_SHIFT = 12, PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,diff --git a/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h new file mode 100644 index 0000000..9a1fffb --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h @@ -0,0 +1,189 @@ +/*
- Copyright (C) 2017-2025 Fuzhou Rockchip Electronics Co., Ltd
- author: eric.gao@rock-chips.com
- create date: 2017-03-31
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef RK33_MIPI_DSI_H +#define RK33_MIPI_DSI_H
+/*
- All these mipi controller register declaration provide
- reg address offset, bits width, bit offset for a
- specified register bits. With these message, we can
- set or clear every bits individually for a 32bit width
- register. We use DSI_HOST_BITS macro definition to
- combinat these message using the following format:
- val(32bit) = addr(16bit) | width(8bit) | offest(8bit)
- for example:
#define SHUTDOWNZ DSI_HOST_BITS(0X004, 1, 0)
- means SHUTDOWNZ is a signal reg bit with bit offset
- qual 0,and it's reg addr offset is 0x004.The conbinat
- result = (0x004 << 16) | (1 << 8) | 0
A more conventional idea might be:
struct dsi_host_reg { u16 addr; u8 bits; u8 bit_offset; };
enum dsi_host_reg_t { VERSION, SHUTDOWNZ, ... DSI_HOST_REG_COUNT, };
#define DSI_HOST_REG(addr, bits, bit_offset) { .addr = _addr; bits = _bits; bit_offset = _bit_offset }
static const struct dsi_host_reg dsi_host_reg[DSI_HOST_REG_COUNT] = { DSI_HOST_BITS(0x000, 32, 0) DSI_HOST_BITS(0x004, 1, 0) };
However, having written the above, I don't see a good reason why it is better than what you have. Both produce a similar size rodata I expect. So let's stick with what you have.
- */
+#define DSI_HOST_BITS(addr, bits, bit_offset) \
((addr<<16) | (bits<<8) | (bit_offset))
Please add enums for the shifts and masks here and use them here and in your decode functions.
+/* DWC_DSI_VERSION_0X3133302A */ +#define VERSION DSI_HOST_BITS(0X000, 32, 0)
0x000
+#define SHUTDOWNZ DSI_HOST_BITS(0X004, 1, 0) +#define TO_CLK_DIVISION DSI_HOST_BITS(0X008, 8, 8) +#define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0X008, 8, 0) +#define DPI_VCID DSI_HOST_BITS(0X00C, 2, 0)
Please can you use lower-case hex?
+#define EN18_LOOSELY DSI_HOST_BITS(0X010, 1, 8) +#define DPI_COLOR_CODING DSI_HOST_BITS(0X010, 4, 0) +#define COLORM_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 4) +#define SHUTD_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 3) +#define HSYNC_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 2) +#define VSYNC_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 1) +#define DATAEN_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 0) +#define OUTVACT_LPCMD_TIME DSI_HOST_BITS(0X018, 8, 16) +#define INVACT_LPCMD_TIME DSI_HOST_BITS(0X018, 8, 0) +#define CRC_RX_EN DSI_HOST_BITS(0X02C, 1, 4) +#define ECC_RX_EN DSI_HOST_BITS(0X02C, 1, 3) +#define BTA_EN DSI_HOST_BITS(0X02C, 1, 2) +#define EOTP_RX_EN DSI_HOST_BITS(0X02C, 1, 1) +#define EOTP_TX_EN DSI_HOST_BITS(0X02C, 1, 0) +#define GEN_VID_RX DSI_HOST_BITS(0X030, 2, 0) +#define CMD_VIDEO_MODE DSI_HOST_BITS(0X034, 1, 0) +#define VPG_ORIENTATION DSI_HOST_BITS(0X038, 1, 24) +#define VPG_MODE DSI_HOST_BITS(0X038, 1, 20) +#define VPG_EN DSI_HOST_BITS(0X038, 1, 16) +#define LP_CMD_EN DSI_HOST_BITS(0X038, 1, 15) +#define FRAME_BTA_ACK_EN DSI_HOST_BITS(0X038, 1, 14) +#define LP_HFP_EN DSI_HOST_BITS(0X038, 1, 13) +#define LP_HBP_EN DSI_HOST_BITS(0X038, 1, 12) +#define LP_VACT_EN DSI_HOST_BITS(0X038, 1, 11) +#define LP_VFP_EN DSI_HOST_BITS(0X038, 1, 10) +#define LP_VBP_EN DSI_HOST_BITS(0X038, 1, 9) +#define LP_VSA_EN DSI_HOST_BITS(0X038, 1, 8) +#define VID_MODE_TYPE DSI_HOST_BITS(0X038, 2, 0) +#define VID_PKT_SIZE DSI_HOST_BITS(0X03C, 14, 0) +#define NUM_CHUNKS DSI_HOST_BITS(0X040, 13, 0) +#define NULL_PKT_SIZE DSI_HOST_BITS(0X044, 13, 0) +#define VID_HSA_TIME DSI_HOST_BITS(0X048, 12, 0) +#define VID_HBP_TIME DSI_HOST_BITS(0X04C, 12, 0) +#define VID_HLINE_TIME DSI_HOST_BITS(0X050, 15, 0) +#define VID_VSA_LINES DSI_HOST_BITS(0X054, 10, 0) +#define VID_VBP_LINES DSI_HOST_BITS(0X058, 10, 0) +#define VID_VFP_LINES DSI_HOST_BITS(0X05C, 10, 0) +#define VID_ACTIVE_LINES DSI_HOST_BITS(0X060, 14, 0) +#define EDPI_CMD_SIZE DSI_HOST_BITS(0X064, 16, 0) +#define MAX_RD_PKT_SIZE DSI_HOST_BITS(0X068, 1, 24) +#define DCS_LW_TX DSI_HOST_BITS(0X068, 1, 19) +#define DCS_SR_0P_TX DSI_HOST_BITS(0X068, 1, 18) +#define DCS_SW_1P_TX DSI_HOST_BITS(0X068, 1, 17) +#define DCS_SW_0P_TX DSI_HOST_BITS(0X068, 1, 16) +#define GEN_LW_TX DSI_HOST_BITS(0X068, 1, 14) +#define GEN_SR_2P_TX DSI_HOST_BITS(0X068, 1, 13) +#define GEN_SR_1P_TX DSI_HOST_BITS(0X068, 1, 12) +#define GEN_SR_0P_TX DSI_HOST_BITS(0X068, 1, 11) +#define GEN_SW_2P_TX DSI_HOST_BITS(0X068, 1, 10) +#define GEN_SW_1P_TX DSI_HOST_BITS(0X068, 1, 9) +#define GEN_SW_0P_TX DSI_HOST_BITS(0X068, 1, 8) +#define ACK_RQST_EN DSI_HOST_BITS(0X068, 1, 1) +#define TEAR_FX_EN DSI_HOST_BITS(0X068, 1, 0) +#define GEN_WC_MSBYTE DSI_HOST_BITS(0X06C, 14, 16) +#define GEN_WC_LSBYTE DSI_HOST_BITS(0X06C, 8, 8) +#define GEN_VC DSI_HOST_BITS(0X06C, 2, 6) +#define GEN_DT DSI_HOST_BITS(0X06C, 6, 0) +#define GEN_PLD_DATA DSI_HOST_BITS(0X070, 32, 0) +#define GEN_RD_CMD_BUSY DSI_HOST_BITS(0X074, 1, 6) +#define GEN_PLD_R_FULL DSI_HOST_BITS(0X074, 1, 5) +#define GEN_PLD_R_EMPTY DSI_HOST_BITS(0X074, 1, 4) +#define GEN_PLD_W_FULL DSI_HOST_BITS(0X074, 1, 3) +#define GEN_PLD_W_EMPTY DSI_HOST_BITS(0X074, 1, 2) +#define GEN_CMD_FULL DSI_HOST_BITS(0X074, 1, 1) +#define GEN_CMD_EMPTY DSI_HOST_BITS(0X074, 1, 0) +#define HSTX_TO_CNT DSI_HOST_BITS(0X078, 16, 16) +#define LPRX_TO_CNT DSI_HOST_BITS(0X078, 16, 0) +#define HS_RD_TO_CNT DSI_HOST_BITS(0X07C, 16, 0) +#define LP_RD_TO_CNT DSI_HOST_BITS(0X080, 16, 0) +#define PRESP_TO_MODE DSI_HOST_BITS(0X084, 1, 24) +#define HS_WR_TO_CNT DSI_HOST_BITS(0X084, 16, 0) +#define LP_WR_TO_CNT DSI_HOST_BITS(0X088, 16, 0) +#define BTA_TO_CNT DSI_HOST_BITS(0X08C, 16, 0) +#define AUTO_CLKLANE_CTRL DSI_HOST_BITS(0X094, 1, 1) +#define PHY_TXREQUESTCLKHS DSI_HOST_BITS(0X094, 1, 0) +#define PHY_HS2LP_TIME_CLK_LANE DSI_HOST_BITS(0X098, 10, 16) +#define PHY_HS2HS_TIME_CLK_LANE DSI_HOST_BITS(0X098, 10, 0) +#define PHY_HS2LP_TIME DSI_HOST_BITS(0X09C, 8, 24) +#define PHY_LP2HS_TIME DSI_HOST_BITS(0X09C, 8, 16) +#define MAX_RD_TIME DSI_HOST_BITS(0X09C, 15, 0) +#define PHY_FORCEPLL DSI_HOST_BITS(0X0A0, 1, 3) +#define PHY_ENABLECLK DSI_HOST_BITS(0X0A0, 1, 2) +#define PHY_RSTZ DSI_HOST_BITS(0X0A0, 1, 1) +#define PHY_SHUTDOWNZ DSI_HOST_BITS(0X0A0, 1, 0) +#define PHY_STOP_WAIT_TIME DSI_HOST_BITS(0X0A4, 8, 8) +#define N_LANES DSI_HOST_BITS(0X0A4, 2, 0) +#define PHY_TXEXITULPSLAN DSI_HOST_BITS(0X0A8, 1, 3) +#define PHY_TXREQULPSLAN DSI_HOST_BITS(0X0A8, 1, 2) +#define PHY_TXEXITULPSCLK DSI_HOST_BITS(0X0A8, 1, 1) +#define PHY_TXREQULPSCLK DSI_HOST_BITS(0X0A8, 1, 0) +#define PHY_TX_TRIGGERS DSI_HOST_BITS(0X0AC, 4, 0) +#define PHYSTOPSTATECLKLANE DSI_HOST_BITS(0X0B0, 1, 2) +#define PHYLOCK DSI_HOST_BITS(0X0B0, 1, 0) +#define PHY_TESTCLK DSI_HOST_BITS(0X0B4, 1, 1) +#define PHY_TESTCLR DSI_HOST_BITS(0X0B4, 1, 0) +#define PHY_TESTEN DSI_HOST_BITS(0X0B8, 1, 16) +#define PHY_TESTDOUT DSI_HOST_BITS(0X0B8, 8, 8) +#define PHY_TESTDIN DSI_HOST_BITS(0X0B8, 8, 0) +#define PHY_TEST_CTRL1 DSI_HOST_BITS(0X0B8, 17, 0) +#define PHY_TEST_CTRL0 DSI_HOST_BITS(0X0B4, 2, 0) +#define INT_ST0 DSI_HOST_BITS(0X0BC, 21, 0) +#define INT_ST1 DSI_HOST_BITS(0X0C0, 18, 0) +#define INT_MKS0 DSI_HOST_BITS(0X0C4, 21, 0) +#define INT_MKS1 DSI_HOST_BITS(0X0C8, 18, 0) +#define INT_FORCE0 DSI_HOST_BITS(0X0D8, 21, 0) +#define INT_FORCE1 DSI_HOST_BITS(0X0DC, 18, 0)
+#define CODE_HS_RX_CLOCK 0X34 +#define CODE_HS_RX_LANE0 0X44 +#define CODE_HS_RX_LANE1 0X54 +#define CODE_HS_RX_LANE2 0X84 +#define CODE_HS_RX_LANE3 0X94
+#define CODE_PLL_INPUT_DIV_RAT 0X17 +#define CODE_PLL_LOOP_DIV_RAT 0X18 +#define CODE_PLL_VCORANGE_VCOCAP 0X10 +#define CODE_PLL_INPUT_LOOP_DIV_RAT 0X19 +#define CODE_PLL_CPCTRL 0X11
+#define CODE_HSTXDATALANEREQUSETSTATETIME 0X70 +#define CODE_HSTXDATALANEPREPARESTATETIME 0X71 +#define CODE_HSTXDATALANEHSZEROSTATETIME 0X72
+enum vid_mode_type_t {
NON_BURST_SYNC_PLUSE = 0,NON_BURST_SYNC_EVENT,BURST_MODE,+};
+enum cmd_video_mode {
VIDEO_MODE = 0,CMD_MODE,+};
+enum dpi_color_coding {
DPI_16BIT_CFG_1 = 0,DPI_16BIT_CFG_2,DPI_16BIT_CFG_3,DPI_18BIT_CFG_1,DPI_18BIT_CFG_2,DPI_24BIT,DPI_20BIT_YCBCR_422_LP,DPI_24BIT_YCBCR_422,DPI_16BIT_YCBCR_422,DPI_30BIT,DPI_36BIT,DPI_12BIT_YCBCR_420,+};
Comment this next one please
+enum vop_id {
VOP_B = 0,VOP_L,+};
+#endif /* end of RK33_MIPI_DSI_H */ diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h index 0ce3d67..d5599ec 100644 --- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h @@ -90,6 +90,7 @@ enum vop_modes { VOP_MODE_EDP = 0, VOP_MODE_HDMI, VOP_MODE_LVDS,
VOP_MODE_MIPI, VOP_MODE_NONE, VOP_MODE_AUTO_DETECT, VOP_MODE_UNKNOWN,diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2069576..4b03a9a 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -405,6 +405,8 @@ config VIDEO_ROCKCHIP (DSI). This driver supports the on-chip video output device, and targets the Rockchip RK3288.
+source "drivers/video/rockchip/Kconfig"
config VIDEO_SANDBOX_SDL bool "Enable sandbox video console using SDL" depends on SANDBOX diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig new file mode 100644 index 0000000..674034b --- /dev/null +++ b/drivers/video/rockchip/Kconfig @@ -0,0 +1,47 @@ +# +# video drivers selection for rockchip soc, these
soc. These
+# configs only impact the compile process. you can
You
+# surely check all the options.In this case,all the
Space after punctuation: options. In this case, all the
(please fix that in the Kconfig below)
+# display driver will be compiled, but which port
drivers
+# finally be used is decided by dts configuration.
finally will be used
s/dts/device tree/
+#
+menu "Video Display Port"
+config DISPLAY_MIPI
bool "MIPI Port"depends on VIDEO_ROCKCHIPhelpInvolve MIPI dsi for video port.if you want to enable these function,you needto turn on the DM_VIDEO,VDEIO_ROCKCHIP together
VIDEO
The dependency is already specified in your 'depends on' line so I don't think you need it here. Instead you could talk about what MIPI is (write out the meaning in full) and what MIPI version or features are supported by the driver. Same with other options below.
what is more,you shoud also enable the related
should
power,such as lcd3v3, lcd1v8,lcd1v0 and so on.
blank line between options
Also, how do I enable the power? Doesn't that happen for me in the drivers?
+config DISPLAY_EDP
bool "EDP Port"depends on VIDEO_ROCKCHIPhelpInvolve EDP for video port.if you want to enable these function,you needto turn on the DM_VIDEO,VDEIO_ROCKCHIP togetherwhat is more,you shoud also enable the relatedpower,such as lcd3v3, lcd1v8,lcd1v0 and so on.+config DISPLAY_LVDS
bool "LVDS Port"depends on VIDEO_ROCKCHIPhelpInvolve LVDS for video port.if you want to enable these function,you needto turn on the DM_VIDEO,VDEIO_ROCKCHIP togetherwhat is more,you shoud also enable the relatedpower,such as lcd3v3, lcd1v8,lcd1v0 and so on.+config DISPLAY_HDMI
bool "HDMI port"depends on VIDEO_ROCKCHIPhelpInvolve HDMI for video portif you want to enable these function,you needto turn on the DM_VIDEO,VDEIO_ROCKCHIP togetherwhat is more,you shoud also enable the relatedpower,such as lcd3v3, lcd1v8,lcd1v0 and so on.+endmenu diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index 7962f86..a14db04 100644 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -5,4 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o +obj-$(CONFIG_VIDEO_ROCKCHIP) += rk_vop.o +obj-$(CONFIG_DISPLAY_MIPI) += rk_mipi.o +obj-$(CONFIG_DISPLAY_EDP) += rk_edp.o +obj-$(CONFIG_DISPLAY_LVDS) += rk_lvds.o +obj-$(CONFIG_DISPLAY_HDMI) += rk_hdmi.o diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c new file mode 100644 index 0000000..a2c2a28 --- /dev/null +++ b/drivers/video/rockchip/rk_mipi.c @@ -0,0 +1,465 @@ +/*
- Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- This program is free software; you can redistribute it and/or modify
- it under the terms of the SPDX General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
I think you want this instead:
* SPDX-License-Identifier: GPL-2.0+
- */
+#define DEBUG
Can you drop that?
+#include <common.h> +#include <clk.h> +#include <display.h> +#include <dm.h> +#include <fdtdec.h> +#include <panel.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/hardware.h> +#include <asm/arch/mipi_rk3399.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3399.h> +#include <asm/arch/cru_rk3399.h> +#include <linux/kernel.h>
goes at the end, after dm/
+#include <dt-bindings/clock/rk3288-cru.h> +#include <dm/uclass-internal.h>
+DECLARE_GLOBAL_DATA_PTR;
+struct mipi_dsi {
u32 ref_clk;u32 sys_clk;u32 pix_clk;u32 phy_clk;u32 txbyte_clk;u32 txesc_clk;+};
+struct rk_mipi_priv {
void __iomem *regs;struct rk3399_grf_regs *grf;struct udevice *panel;struct mipi_dsi *dsi;+};
+static int rk_mipi_read_timing(struct udevice *dev,
struct display_timing *timing)+{
if (fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), 0, timing)) {debug("%s: Failed to decode display timing\n", __func__);return -EINVAL;}return 0;+} +/*
- register write function used only for mipi dsi controller.
- parameter:
- reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit)
you can use define in rk_mipi.h directly for this parameter
- val: value that will be write to specified bits of register
- */
+static void rk_mipi_dsi_write(struct udevice *dev, u32 reg, u32 val)
Can you pass regs to this function instead of dev, to avoid the conversion each time?
+{
#define OFFSET (reg & 0xff)#define BITS ((reg >> 8) & 0xff)#define ADDR ((reg >> 16) + priv->regs)
These can just be local variables
int offset = (reg & DSI_BIT_OFFSET_MASK) >> DSI_BIT_OFFSET_SHIFT;
u32 dat;u32 mask;struct rk_mipi_priv *priv = dev_get_priv(dev);/* Mask for specifiled bits,the corresponding bits will be clear */mask = (~((0xffffffff << OFFSET) &(0xffffffff >> (32 - OFFSET - BITS))));/* Make sure val in the available range */val &= (~(0xffffffff << BITS));/* Get register's original val */dat = readl(ADDR);/* Clear specified bits */dat &= mask;/* Fill specified bits */dat |= (val << OFFSET);writel(dat, ADDR);+}
+static int rk_mipi_dsi_enable(struct udevice *dev,
const struct display_timing *timing)+{
int node, timing_node;int val;struct rk_mipi_priv *priv = dev_get_priv(dev);struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);u32 txbyte_clk = priv->dsi->txbyte_clk;u32 txesc_clk = priv->dsi->txesc_clk;txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);/* Select the video source */switch (disp_uc_plat->source_id) {case VOP_B:rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);break;case VOP_L:rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);break;default:return -EINVAL;}/* Set Controller as TX mode */val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);/* Exit tx stop mode */val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT;rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val);/* Disable turnequest */val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);/* Set Display timing parameter */rk_mipi_dsi_write(dev, VID_HSA_TIME, timing->hsync_len.typ);rk_mipi_dsi_write(dev, VID_HBP_TIME, timing->hback_porch.typ);rk_mipi_dsi_write(dev, VID_HLINE_TIME,(timing->hsync_len.typ +timing->hback_porch.typ +timing->hactive.typ +timing->hfront_porch.typ));rk_mipi_dsi_write(dev, VID_VSA_LINES, timing->vsync_len.typ);rk_mipi_dsi_write(dev, VID_VBP_LINES, timing->vback_porch.typ);rk_mipi_dsi_write(dev, VID_VFP_LINES, timing->vfront_porch.typ);rk_mipi_dsi_write(dev, VID_ACTIVE_LINES, timing->vactive.typ);/* Set Signal Polarity */val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;rk_mipi_dsi_write(dev, HSYNC_ACTIVE_LOW, val);val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;rk_mipi_dsi_write(dev, VSYNC_ACTIVE_LOW, val);val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;rk_mipi_dsi_write(dev, DISPLAY_FLAGS_DE_LOW, val);val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;rk_mipi_dsi_write(dev, COLORM_ACTIVE_LOW, val);/* Set video mode */rk_mipi_dsi_write(dev, CMD_VIDEO_MODE, VIDEO_MODE);/* Set video mode transmission type as burst mode */rk_mipi_dsi_write(dev, VID_MODE_TYPE, BURST_MODE);/* Set pix num in a video package */rk_mipi_dsi_write(dev, VID_PKT_SIZE, 0x4b0);/* Set dpi color coding depth 24 bit */timing_node = fdt_subnode_offset(gd->fdt_blob,dev_of_offset(dev), "display-timings");node = fdt_first_subnode(gd->fdt_blob, timing_node);val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);switch (val) {case 16:rk_mipi_dsi_write(dev, DPI_COLOR_CODING, DPI_16BIT_CFG_1);break;case 24:rk_mipi_dsi_write(dev, DPI_COLOR_CODING, DPI_24BIT);break;case 30:rk_mipi_dsi_write(dev, DPI_COLOR_CODING, DPI_30BIT);break;default:rk_mipi_dsi_write(dev, DPI_COLOR_CODING, DPI_24BIT);}/* Enable low power mode */rk_mipi_dsi_write(dev, LP_CMD_EN, 1);rk_mipi_dsi_write(dev, LP_HFP_EN, 1);rk_mipi_dsi_write(dev, LP_VACT_EN, 1);rk_mipi_dsi_write(dev, LP_VFP_EN, 1);rk_mipi_dsi_write(dev, LP_VBP_EN, 1);rk_mipi_dsi_write(dev, LP_VSA_EN, 1);/* Division for timeout counter clk */rk_mipi_dsi_write(dev, TO_CLK_DIVISION, 0x0a);/* Tx esc clk division from txbyte clk */rk_mipi_dsi_write(dev, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk);/** Timeout count for hs<->lp* transation between Line period*/rk_mipi_dsi_write(dev, HSTX_TO_CNT, 0x3e8);/* Phy State transfer timing */rk_mipi_dsi_write(dev, PHY_STOP_WAIT_TIME, 32);rk_mipi_dsi_write(dev, PHY_TXREQUESTCLKHS, 1);rk_mipi_dsi_write(dev, PHY_HS2LP_TIME, 0x14);rk_mipi_dsi_write(dev, PHY_LP2HS_TIME, 0x10);rk_mipi_dsi_write(dev, MAX_RD_TIME, 0x2710);/* Power on */rk_mipi_dsi_write(dev, SHUTDOWNZ, 1);return 0;+}
+/*
- rk mipi dphy write function
Please use the standard format for function comments. See for example dm/device.h
- */
+static void rk_mipi_phy_write(struct udevice *dev, unsigned char test_code,
unsigned char *test_data, unsigned char size)+{
int i = 0;/* Write Test code */rk_mipi_dsi_write(dev, PHY_TESTCLK, 1);rk_mipi_dsi_write(dev, PHY_TESTDIN, test_code);rk_mipi_dsi_write(dev, PHY_TESTEN, 1);rk_mipi_dsi_write(dev, PHY_TESTCLK, 0);rk_mipi_dsi_write(dev, PHY_TESTEN, 0);/* Write Test data */for (i = 0; i < size; i++) {rk_mipi_dsi_write(dev, PHY_TESTCLK, 0);rk_mipi_dsi_write(dev, PHY_TESTDIN, test_data[i]);rk_mipi_dsi_write(dev, PHY_TESTCLK, 1);}+}
+/*
- mipi dphy config function. calculate the suitable prediv,
- feedback div,fsfreqrang value ,cap ,lpf and so on
- according to the given pix clk ratthe.and then enable phy
- */
+static int rk_mipi_phy_enable(struct udevice *dev) +{
int i;struct rk_mipi_priv *priv = dev_get_priv(dev);u64 fbdiv;u64 prediv = 1;u64 ddr_clk = priv->dsi->phy_clk;u32 refclk = priv->dsi->ref_clk;u32 remain = refclk;unsigned char test_data[2] = {0};/** dphy fsfreqrang* different dphy config is needed for diffenect freq rang* here list the config-freq relation
Can you please check this comment? It seems to have spelling mistakes or doesn't make sense
*/int freq_rang[][2] = {{90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01},{140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12},{200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23},{270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15},{400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07},{600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09},{800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a},{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}};/* Shutdown mode */rk_mipi_dsi_write(dev, PHY_SHUTDOWNZ, 0);rk_mipi_dsi_write(dev, PHY_RSTZ, 0);rk_mipi_dsi_write(dev, PHY_TESTCLR, 1);/* Pll locking */rk_mipi_dsi_write(dev, PHY_TESTCLR, 0);/* config cp and lfp */test_data[0] = 0x80 | (ddr_clk / (200*MHZ)) << 3 | 0x3;
Spaces around *
rk_mipi_phy_write(dev, 0x10, test_data, 1);
Do you have register enums for 0x10, 0x11, etc.?
test_data[0] = 0x8;rk_mipi_phy_write(dev, 0x11, test_data, 1);test_data[0] = 0x80 | 0x40;rk_mipi_phy_write(dev, 0x12, test_data, 1);/* select the suitable value for fsfreqrang reg */for (i = 0; i < ARRAY_SIZE(freq_rang); i++) {if (ddr_clk / (MHZ) >= freq_rang[i][0])break;}
What happens if you didn't find the range? Then i will be out of range. Do you need a check?
test_data[0] = freq_rang[i][1] << 1;rk_mipi_phy_write(dev, CODE_HS_RX_LANE0, test_data, 1);/** Calculate the best ddrclk and it's* corresponding div value, If the given* pixelclock is great than 250M, the ddr* clk will be fix 1500M.otherwise , it's* equal to ddr_clk= pixclk*6.* 40MHZ>=refclk/prediv>=5MHZ according to spec
Spaces around >=
*/#define MAX_FBDIV 512#define MAX_PREDIV (refclk/(5*MHZ))#define MIN_PREDIV ((refclk/(40*MHZ)) ? (refclk/(40*MHZ) + 1) : 1)
Can you just use local variables here instead of #define ?
debug("DEBUG: MAX_PREDIV=%u, MIN_PREDIV=%u\n", MAX_PREDIV, MIN_PREDIV);
debug("%s: MAX_PREDIV=%u, MIN_PREDIV=%u\n", __func__, MAX_PREDIV, MIN_PREDIV);
Please fix the rest also. The function name helps us know which module is generating the debugging.
if (MAX_PREDIV < MIN_PREDIV) {debug("Err: Invalid refclk value@%s\n", __func__);return -EINVAL;}
Please and a comment as to what you are doing here
for (i = MIN_PREDIV; i < MAX_PREDIV; i++) {if ((ddr_clk * i % refclk < remain) &&(ddr_clk * i / refclk) < MAX_FBDIV) {prediv = i;remain = ddr_clk * i % refclk;}}fbdiv = ddr_clk * prediv / refclk;ddr_clk = refclk * fbdiv / prediv;priv->dsi->phy_clk = ddr_clk;debug("DEBUG:refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n",refclk, prediv, fbdiv, ddr_clk);/* config prediv and feedback reg */test_data[0] = prediv - 1;rk_mipi_phy_write(dev, CODE_PLL_INPUT_DIV_RAT, test_data, 1);test_data[0] = (fbdiv - 1) & 0x1f;rk_mipi_phy_write(dev, CODE_PLL_LOOP_DIV_RAT, test_data, 1);test_data[0] = (fbdiv - 1) >> 5 | 0x80;rk_mipi_phy_write(dev, CODE_PLL_LOOP_DIV_RAT, test_data, 1);test_data[0] = 0x30;rk_mipi_phy_write(dev, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1);/* rest config */test_data[0] = 0x4d;rk_mipi_phy_write(dev, 0x20, test_data, 1);test_data[0] = 0x3d;rk_mipi_phy_write(dev, 0x21, test_data, 1);test_data[0] = 0xdf;rk_mipi_phy_write(dev, 0x21, test_data, 1);test_data[0] = 0x7;rk_mipi_phy_write(dev, 0x22, test_data, 1);test_data[0] = 0x80 | 0x7;rk_mipi_phy_write(dev, 0x22, test_data, 1);test_data[0] = 0x80 | 15;rk_mipi_phy_write(dev, CODE_HSTXDATALANEREQUSETSTATETIME,test_data, 1);test_data[0] = 0x80 | 85;rk_mipi_phy_write(dev, CODE_HSTXDATALANEPREPARESTATETIME,test_data, 1);test_data[0] = 0x40 | 10;rk_mipi_phy_write(dev, CODE_HSTXDATALANEHSZEROSTATETIME,test_data, 1);/* enter into stop mode */rk_mipi_dsi_write(dev, N_LANES, 0x03);rk_mipi_dsi_write(dev, PHY_ENABLECLK, 1);rk_mipi_dsi_write(dev, PHY_FORCEPLL, 1);rk_mipi_dsi_write(dev, PHY_SHUTDOWNZ, 1);rk_mipi_dsi_write(dev, PHY_RSTZ, 1);return 0;+}
+static int rk_mipi_enable(struct udevice *dev, int panel_bpp,
const struct display_timing *timing)+{
return 0;+}
+static int rk_mipi_ofdata_to_platdata(struct udevice *dev) +{
struct rk_mipi_priv *priv = dev_get_priv(dev);priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
Check for error here?
priv->regs = (void *)dev_get_addr(dev);
and here?
return 0;+}
+/*
- probe function: check panel existence and reading
- it's timing. then config mipi dsi controller and
- enable it according to the timing parameter
- */
+static int rk_mipi_probe(struct udevice *dev) +{
struct rk_mipi_priv *priv = dev_get_priv(dev);struct display_timing timing;int ret;ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",&priv->panel);if (ret) {debug("Err:Can't find panel@%s, ret = %d\n", __func__, ret);return -ENODEV;
return ret (I think). The device still exists, it just can't be probed.
}/* Read panel timing,and save to struct timing */rk_mipi_read_timing(dev, &timing);/* fill the mipi controller parameter */priv->dsi->ref_clk = 24*MHZ;priv->dsi->sys_clk = priv->dsi->ref_clk;priv->dsi->pix_clk = timing.pixelclock.typ;priv->dsi->phy_clk = priv->dsi->pix_clk * 6;priv->dsi->txbyte_clk = priv->dsi->phy_clk / 8;priv->dsi->txesc_clk = 20*MHZ;/* config mipi dsi according to timing and enable it */ret = rk_mipi_dsi_enable(dev, &timing);if (ret) {debug("Err: mipi dsi enable fail@%s,ret=%d\n", __func__, ret);return ret;}/* init mipi dsi phy */ret = rk_mipi_phy_enable(dev);if (ret) {debug("Err: mipi phy enable fail@%s,ret=%d\n", __func__, ret);return ret;}/* enable backlight */ret = panel_enable_backlight(priv->panel);if (ret) {debug("Err: fail to enable bg@%s,ret=%d\n", __func__, ret);return ret;}return 0;+}
+static const struct dm_display_ops rk_mipi_dsi_ops = {
.read_timing = rk_mipi_read_timing,.enable = rk_mipi_enable,+};
+static const struct udevice_id rk_mipi_dsi_ids[] = {
{ .compatible = "rockchip,rk3399_mipi_dsi" },{ }+};
+U_BOOT_DRIVER(rk_mipi_dsi) = {
.name = "rk_mipi_dsi",.id = UCLASS_DISPLAY,.of_match = rk_mipi_dsi_ids,.ofdata_to_platdata = rk_mipi_ofdata_to_platdata,.probe = rk_mipi_probe,.ops = &rk_mipi_dsi_ops,.priv_auto_alloc_size = sizeof(struct rk_mipi_priv),+}; diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index aeecb58..e833eb5 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -109,6 +109,10 @@ void rkvop_mode_set(struct rk3288_vop *regs, clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); break;
case VOP_MODE_MIPI:clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,V_MIPI_OUT_EN(1));break; case VOP_MODE_EDP: default: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,@@ -178,13 +182,11 @@ void rkvop_mode_set(struct rk3288_vop *regs,
- @dev: VOP device that we want to connect to the display
- @fbbase: Frame buffer address
*/
- @l2bpp Log2 of bits-per-pixels for the display
- @ep_node: Device tree node to process - this is the offset of an endpoint
node within the VOP's 'port' list.- @return 0 if OK, -ve if something went wrong
-int rk_display_init(struct udevice *dev, ulong fbbase,
enum video_log2_bpp l2bpp, int ep_node)+int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node) { struct video_priv *uc_priv = dev_get_uclass_priv(dev); const void *blob = gd->fdt_blob; @@ -196,6 +198,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase, int ret, remote, i, offset; struct display_plat *disp_uc_plat; struct clk clk;
enum video_log2_bpp l2bpp; vop_id = fdtdec_get_int(blob, ep_node, "reg", -1); debug("vop_id=%d\n", vop_id);@@ -245,11 +248,26 @@ int rk_display_init(struct udevice *dev, ulong fbbase, ret = clk_get_by_index(dev, 1, &clk); if (!ret) ret = clk_set_rate(&clk, timing.pixelclock.typ);
if (ret) {
/* clk_set_rate return clk rate,normally it is a none zero value */if (!ret) { debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret); return ret; }/* Set bitwidth for vop display according to vop mode */switch (vop_id) {case VOP_MODE_EDP:case VOP_MODE_HDMI:case VOP_MODE_LVDS:l2bpp = VIDEO_BPP16;break;case VOP_MODE_MIPI:l2bpp = VIDEO_BPP32;break;default:l2bpp = VIDEO_BPP16;}rkvop_mode_set(regs, &timing, vop_id); rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);@@ -327,7 +345,7 @@ static int rk_vop_probe(struct udevice *dev) for (node = fdt_first_subnode(blob, port); node > 0; node = fdt_next_subnode(blob, node)) {
ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
ret = rk_display_init(dev, plat->base, node); if (ret) debug("Device failed: ret=%d\n", ret); if (!ret)@@ -342,7 +360,14 @@ static int rk_vop_bind(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
plat->size = 1920 * 1080 * 2;
/** plat->size is only used for reserve fb space in memory befor* relocation. So we just need to make sure it's big enough for* all condition. And actually, we now know nothing about the* display port type, color depth and it's resolution ratio.* So, we can't calculat fb size accurately.
calculate
*/plat->size = 1920 * 1200 * 4; return 0;} @@ -351,6 +376,8 @@ static const struct video_ops rk_vop_ops = { };
static const struct udevice_id rk_vop_ids[] = {
{ .compatible = "rockchip,rk3399-vop-big" },{ .compatible = "rockchip,rk3399-vop-lit" }, { .compatible = "rockchip,rk3288-vop" }, { }};
1.9.1
Regards, Simon
Add dts config for mipi display, include vop, mipi controller, panel, backlight.And Enable rk808 for lcd_3v3 in another patch.
Signed-off-by: Eric Gao eric.gao@rock-chips.com ---
arch/arm/dts/rk3399-evb.dts | 84 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/rk3399.dtsi | 72 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 156 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 7bf805a..709d66d 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -59,6 +59,15 @@ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; };
+ backlight: backlight { + compatible = "pwm-backlight"; + status = "disabled"; + }; + + panel:panel { + compatible = "simple-panel"; + status = "disabled"; + }; };
&emmc_phy { @@ -139,6 +148,7 @@ status = "okay";
vcc12-supply = <&vcc3v3_sys>; + regulators { vcc33_lcd: SWITCH_REG2 { regulator-always-on; @@ -149,6 +159,80 @@ }; };
+&backlight { + power-supply = <&vccsys>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + pwms = <&pwm0 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + pwm-delay-us = <10000>; + status = "okay"; + }; + +&panel { + power-supply = <&vcc33_lcd>; + backlight = <&backlight>; + /*enable-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;*/ + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + rockchip,panel = <&panel>; + display-timings { + timing0 { + bits-per-pixel = <24>; + clock-frequency = <160000000>; + hfront-porch = <120>; + hsync-len = <20>; + hback-porch = <21>; + hactive = <1200>; + vfront-porch = <21>; + vsync-len = <3>; + vback-porch = <18>; + vactive = <1920>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; +}; + &pinctrl { pmic { pmic_int_l: pmic-int-l { diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 93e3bf4..c82e674 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -667,6 +667,78 @@ status = "disabled"; };
+ vopl: vop@ff8f0000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-vop-lit"; + reg = <0x0 0xff8f0000 0x0 0x3efc>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; + reset-names = "axi", "ahb", "dclk"; + status = "okay"; + vopl_out: port { + #address-cells = <1>; + #size-cells = <0>; + vopl_out_mipi: endpoint@0 { + reg = <3>; + remote-endpoint = <&mipi_in_vopl>; + }; + }; + }; + + vopb: vop@ff900000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-vop-big"; + reg = <0x0 0xff900000 0x0 0x3efc>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; + #clock-cells = <0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; + reset-names = "axi", "ahb", "dclk"; + /*power-domains = <&power RK3399_PD_VOPB>;*/ + status = "okay"; + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + vopb_out_mipi: endpoint@0 { + reg = <3>; + remote-endpoint = <&mipi_in_vopb>; + }; + }; + }; + + mipi_dsi: mipi@ff960000 { + compatible = "rockchip,rk3399_mipi_dsi"; + reg = <0x0 0xff960000 0x0 0x8000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, + <&cru SCLK_DPHY_TX0_CFG>; + clock-names = "ref", "pclk", "phy_cfg"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; + mipi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi>; + }; + }; + }; + }; + pinctrl: pinctrl { u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pinctrl";
On 9 April 2017 at 20:41, Eric Gao eric.gao@rock-chips.com wrote:
Add dts config for mipi display, include vop,mipi controller, panel, backlight.And Enable rk808 for lcd_3v3 in another patch.
Signed-off-by: Eric Gao eric.gao@rock-chips.com
arch/arm/dts/rk3399-evb.dts | 84 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/rk3399.dtsi | 72 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 156 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Enable mipi dsi by default for rk3399-evb board
Signed-off-by: Eric Gao eric.gao@rock-chips.com ---
configs/evb-rk3399_defconfig | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index aac6d2d..f41cbf9 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -64,3 +64,9 @@ CONFIG_PMIC_CHILDREN=y CONFIG_SPL_PMIC_CHILDREN=y CONFIG_PMIC_RK808=y CONFIG_REGULATOR_RK808=y +CONFIG_DM_VIDEO=y +CONFIG_DM_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_MIPI=y
participants (2)
-
Eric Gao -
Simon Glass