[PATCH v3 00/11] Add MTK AHCI driver, BPI-R64 dts and USB-Nodes for mt7622>
From: Frank Wunderlich frank-w@public-files.de
This series adds Mediatek AHCI driver, makes neccessary phy modifications creates new dts for bananapi-r64 (because it's a bit different to rfb) and adds all DTS nodes to get SATA and USB working on mt7622 and mt7623
they are based on top of this:
Add PCIe and its clock support for mt7622 https://patchwork.ozlabs.org/project/uboot/list/?series=194888
and to get USB working (no hard depency, ports get enumerated without it): usb: xhci: add a member hci_version in xhci_ctrl struct https://patchwork.ozlabs.org/project/uboot/list/?series=195331
v2->v3: - fixed code style suggested by sam v1->v2: - made register of phy optional for tphy v1 and remove it in dts
Frank Wunderlich (11): arm: dts: mt7622: add SATA reset constants phy: mtk-tphy: add PHY_TYPE_SATA phy: mtk-tphy: make shared reg optional for v1 reset: add basic reset controller for pciesys ahci: mediatek: add ahci driver clk: mt7622: add needed clocks for ssusb-node arm: dts: add watchdog-reboot node for mt7622 arm: dts: add dts for Bananapi-R64 arm: dts: mt7622: add sata- and asm_sel nodes arm: dts: mt7622: add USB nodes arm: dts: mt7623: add USB nodes
arch/arm/dts/Makefile | 1 + arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 223 +++++++++++++++++++++++ arch/arm/dts/mt7622-rfb.dts | 8 + arch/arm/dts/mt7622.dtsi | 92 ++++++++++ arch/arm/dts/mt7623.dtsi | 46 +++++ arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 ++ drivers/ata/Kconfig | 8 + drivers/ata/Makefile | 1 + drivers/ata/mtk_ahci.c | 128 +++++++++++++ drivers/clk/mediatek/clk-mt7622.c | 56 ++++++ drivers/phy/phy-mtk-tphy.c | 110 ++++++++++- include/dt-bindings/reset/mt7629-reset.h | 5 +- 12 files changed, 690 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/mt7622-bananapi-bpi-r64.dts create mode 100644 drivers/ata/mtk_ahci.c
From: Frank Wunderlich frank-w@public-files.de
add reset constants used for SATA to header file
Signed-off-by: Frank Wunderlich frank-w@public-files.de --- include/dt-bindings/reset/mt7629-reset.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h index 8f1634f7a6..311a5cb3d0 100644 --- a/include/dt-bindings/reset/mt7629-reset.h +++ b/include/dt-bindings/reset/mt7629-reset.h @@ -6,7 +6,10 @@ #ifndef _DT_BINDINGS_MTK_RESET_H_ #define _DT_BINDINGS_MTK_RESET_H_
-/* PCIe Subsystem resets */ +/* PCIe/SATA Subsystem resets */ +#define MT7622_SATA_PHY_REG_RST 12 +#define MT7622_SATA_PHY_SW_RST 13 +#define MT7622_SATA_AXI_BUS_RST 15 #define PCIE1_CORE_RST 19 #define PCIE1_MMIO_RST 20 #define PCIE1_HRST 21
From: Frank Wunderlich frank-w@public-files.de
add support for PHY_TYPE_SATA to Mediateks TPHY driver
Signed-off-by: Frank Wunderlich frank-w@public-files.de Reviewed-by: Chunfeng Yun chunfeng.yun@mediatek.com --- drivers/phy/phy-mtk-tphy.c | 105 +++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+)
diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c index 1e65c24356..326227a30d 100644 --- a/drivers/phy/phy-mtk-tphy.c +++ b/drivers/phy/phy-mtk-tphy.c @@ -175,6 +175,65 @@ #define XC3_RG_U3_XTAL_RX_PWD BIT(9) #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
+/* SATA register setting */ +#define PHYD_CTRL_SIGNAL_MODE4 0x1c +/* CDR Charge Pump P-path current adjustment */ +#define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) +#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20) +#define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) +#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8) + +#define PHYD_DESIGN_OPTION2 0x24 +/* Symbol lock count selection */ +#define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) +#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4) + +#define PHYD_DESIGN_OPTION9 0x40 +/* COMWAK GAP width window */ +#define RG_TG_MAX_MSK GENMASK(20, 16) +#define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16) +/* COMINIT GAP width window */ +#define RG_T2_MAX_MSK GENMASK(13, 8) +#define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8) +/* COMWAK GAP width window */ +#define RG_TG_MIN_MSK GENMASK(7, 5) +#define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5) +/* COMINIT GAP width window */ +#define RG_T2_MIN_MSK GENMASK(4, 0) +#define RG_T2_MIN_VAL(x) (0x1f & (x)) + +#define ANA_RG_CTRL_SIGNAL1 0x4c +/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ +#define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) +#define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8) + +#define ANA_RG_CTRL_SIGNAL4 0x58 +#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) +#define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20) +/* Loop filter R1 resistance adjustment for Gen1 speed */ +#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) +#define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8) + +#define ANA_RG_CTRL_SIGNAL6 0x60 +/* I-path capacitance adjustment for Gen1 */ +#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) +#define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24) +#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) +#define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x)) + +#define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c +/* RX Gen1 LEQ tuning step */ +#define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) +#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8) + +#define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 +#define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) +#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16) + +#define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc +#define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) +#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) + enum mtk_phy_version { MTK_TPHY_V1 = 1, MTK_TPHY_V2, @@ -372,6 +431,45 @@ static void pcie_phy_instance_init(struct mtk_tphy *tphy, udelay(3000); }
+static void sata_phy_instance_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + + clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL6, + RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK, + RG_CDR_BIRLTR_GEN1_VAL(0x6) | + RG_CDR_BC_GEN1_VAL(0x1a)); + clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL4, + RG_CDR_BIRLTD0_GEN1_MSK, + RG_CDR_BIRLTD0_GEN1_VAL(0x18)); + clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL5, + RG_CDR_BIRLTD0_GEN3_MSK, + RG_CDR_BIRLTD0_GEN3_VAL(0x06)); + clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL4, + RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK, + RG_CDR_BICLTR_GEN1_VAL(0x0c) | + RG_CDR_BR_GEN2_VAL(0x07)); + clrsetbits_le32(u3_banks->phyd + PHYD_CTRL_SIGNAL_MODE4, + RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK, + RG_CDR_BICLTD0_GEN1_VAL(0x08) | + RG_CDR_BICLTD1_GEN1_VAL(0x02)); + clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION2, + RG_LOCK_CNT_SEL_MSK, + RG_LOCK_CNT_SEL_VAL(0x02)); + clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION9, + RG_T2_MIN_MSK | RG_TG_MIN_MSK | + RG_T2_MAX_MSK | RG_TG_MAX_MSK, + RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) | + RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e)); + clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL1, + RG_IDRV_0DB_GEN1_MSK, + RG_IDRV_0DB_GEN1_VAL(0x20)); + clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL1, + RG_EQ_DLEQ_LFI_GEN1_MSK, + RG_EQ_DLEQ_LFI_GEN1_VAL(0x03)); +} + static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { @@ -414,6 +512,9 @@ static void phy_v1_banks_init(struct mtk_tphy *tphy, u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; break; + case PHY_TYPE_SATA: + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; + break; default: dev_err(tphy->dev, "incompatible PHY type\n"); return; @@ -474,6 +575,9 @@ static int mtk_phy_init(struct phy *phy) case PHY_TYPE_PCIE: pcie_phy_instance_init(tphy, instance); break; + case PHY_TYPE_SATA: + sata_phy_instance_init(tphy, instance); + break; default: dev_err(tphy->dev, "incompatible PHY type\n"); return -EINVAL; @@ -552,6 +656,7 @@ static int mtk_phy_xlate(struct phy *phy, instance->type = args->args[1]; if (!(instance->type == PHY_TYPE_USB2 || instance->type == PHY_TYPE_USB3 || + instance->type == PHY_TYPE_SATA || instance->type == PHY_TYPE_PCIE)) { dev_err(phy->dev, "unsupported device type\n"); return -EINVAL;
From: Frank Wunderlich frank-w@public-files.de
make the shared reg optional when version is v1 for sata
Suggested-by: Chunfeng Yun chunfeng.yun@mediatek.com Signed-off-by: Frank Wunderlich frank-w@public-files.de Reviewed-by: Chunfeng Yun chunfeng.yun@mediatek.com --- drivers/phy/phy-mtk-tphy.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c index 326227a30d..3d7b9cd2b1 100644 --- a/drivers/phy/phy-mtk-tphy.c +++ b/drivers/phy/phy-mtk-tphy.c @@ -698,11 +698,10 @@ static int mtk_tphy_probe(struct udevice *dev) tphy->dev = dev; tphy->version = dev_get_driver_data(dev);
- /* v1 has shared banks */ + /* v1 has shared banks for usb/pcie mode, */ + /* but not for sata mode */ if (tphy->version == MTK_TPHY_V1) { tphy->sif_base = dev_read_addr_ptr(dev); - if (!tphy->sif_base) - return -ENOENT; }
dev_for_each_subnode(subnode, dev) {
From: Frank Wunderlich frank-w@public-files.de
bind reset controller to pciesys
Signed-off-by: Frank Wunderlich frank-w@public-files.de --- drivers/clk/mediatek/clk-mt7622.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index bd86b5b974..d53ed69189 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -594,6 +594,20 @@ static int mt7622_pciesys_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs); }
+static int mt7622_pciesys_bind(struct udevice *dev) +{ + int ret = 0; + + if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) { +// PCIESYS uses in linux also 0x34 = ETHSYS reset controller + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); + if (ret) + debug("Warning: failed to bind reset controller\n"); + } + + return ret; +} + static int mt7622_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs); @@ -710,6 +724,7 @@ U_BOOT_DRIVER(mtk_clk_pciesys) = { .id = UCLASS_CLK, .of_match = mt7622_pciesys_compat, .probe = mt7622_pciesys_probe, + .bind = mt7622_pciesys_bind, .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, };
Gesendet: Donnerstag, 20. August 2020 um 11:55 Uhr Von: "Frank Wunderlich" linux@fw-web.de +static int mt7622_pciesys_bind(struct udevice *dev) +{
- int ret = 0;
- if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
+// PCIESYS uses in linux also 0x34 = ETHSYS reset controller
sorry, squashed change to wrong commit...will fix it soon
- ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
- if (ret)
debug("Warning: failed to bind reset controller\n");- }
- return ret;
+}
From: Frank Wunderlich frank-w@public-files.de
add AHCI driver ported from linux
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/driv...
Signed-off-by: Frank Wunderlich frank-w@public-files.de --- drivers/ata/Kconfig | 8 +++ drivers/ata/Makefile | 1 + drivers/ata/mtk_ahci.c | 128 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 137 insertions(+) create mode 100644 drivers/ata/mtk_ahci.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index d8c9756c2a..f2f8275aec 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -130,4 +130,12 @@ config AHCI_MVEBU onboard AHCI SATA.
If unsure, say N. + +config MTK_AHCI + bool "Enable Mediatek AHCI driver support" + depends on AHCI + help + Enable this driver to support Sata devices through + Mediatek AHCI controller (e.g. MT7622). + endmenu diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index a69edb10f7..98fb480700 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -19,3 +19,4 @@ obj-$(CONFIG_SATA_SIL) += sata_sil.o obj-$(CONFIG_SANDBOX) += sata_sandbox.o obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o +obj-$(CONFIG_MTK_AHCI) += mtk_ahci.o diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c new file mode 100644 index 0000000000..4ad260a5bb --- /dev/null +++ b/drivers/ata/mtk_ahci.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MTK SATA platform driver + * + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Ryder Lee ryder.lee@mediatek.com + * Author: Frank Wunderlich frank-w@public-files.de + */ + +#include <common.h> +#include <ahci.h> +#include <asm/io.h> +#include <dm.h> +#include <dm/of_access.h> +#include <generic-phy.h> +#include <linux/err.h> +#include <regmap.h> +#include <reset.h> +#include <sata.h> +#include <scsi.h> +#include <syscon.h> + +#define SYS_CFG 0x14 +#define SYS_CFG_SATA_MSK GENMASK(31, 30) +#define SYS_CFG_SATA_EN BIT(31) + +struct mtk_ahci_priv { + void *base; + + struct ahci_uc_priv ahci_priv; + struct regmap *mode; + struct reset_ctl_bulk rst_bulk; +}; + +static int mtk_ahci_bind(struct udevice *dev) +{ + struct udevice *scsi_dev; + + return ahci_bind_scsi(dev, &scsi_dev); +} + +static int mtk_ahci_ofdata_to_platdata(struct udevice *dev) +{ + struct mtk_ahci_priv *priv = dev_get_priv(dev); + + priv->base = devfdt_remap_addr_index(dev, 0); + + return 0; +} + +static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv, + struct udevice *dev) +{ + struct mtk_ahci_priv *plat = dev_get_priv(dev); + const void *fdt = gd->fdt_blob; + + /* enable SATA function if needed */ + if (fdt_get_property(fdt, dev_of_offset(dev), + "mediatek,phy-mode", NULL)) { + plat->mode = syscon_regmap_lookup_by_phandle(dev, + "mediatek,phy-mode"); + if (IS_ERR(plat->mode)) { + dev_err(dev, "missing phy-mode phandle\n"); + return PTR_ERR(plat->mode); + } + regmap_update_bits(plat->mode, SYS_CFG, + SYS_CFG_SATA_MSK, SYS_CFG_SATA_EN); + } + + ofnode_read_u32(dev->node, "ports-implemented", &hpriv->port_map); + return 0; +} + +static int mtk_ahci_probe(struct udevice *dev) +{ + struct mtk_ahci_priv *priv = dev_get_priv(dev); + int ret; + struct phy phy; + + ret = mtk_ahci_parse_property(&priv->ahci_priv, dev); + if (ret) + return ret; + + ret = reset_get_bulk(dev, &priv->rst_bulk); + if (!ret) { + reset_assert_bulk(&priv->rst_bulk); + reset_deassert_bulk(&priv->rst_bulk); + } else { + dev_err(dev, "Failed to get reset: %d\n", ret); + } + + ret = generic_phy_get_by_name(dev, "sata-phy", &phy); + if (ret) { + pr_err("can't get the phy from DT\n"); + return ret; + } + + ret = generic_phy_init(&phy); + if (ret) { + pr_err("unable to initialize the sata phy\n"); + return ret; + } + + ret = generic_phy_power_on(&phy); + if (ret) { + pr_err("unable to power on the sata phy\n"); + return ret; + } + + return ahci_probe_scsi(dev, (ulong)priv->base); +} + +static const struct udevice_id mtk_ahci_ids[] = { + { .compatible = "mediatek,mtk-ahci" }, + { } +}; + +U_BOOT_DRIVER(mtk_ahci) = { + .name = "mtk_ahci", + .id = UCLASS_AHCI, + .of_match = mtk_ahci_ids, + .bind = mtk_ahci_bind, + .ofdata_to_platdata = mtk_ahci_ofdata_to_platdata, + .ops = &scsi_ops, + .probe = mtk_ahci_probe, + .priv_auto_alloc_size = sizeof(struct mtk_ahci_priv), +};
From: Frank Wunderlich frank-w@public-files.de
MT7622 needs additional clock definitions to work properly
Signed-off-by: Frank Wunderlich frank-w@public-files.de --- drivers/clk/mediatek/clk-mt7622.c | 43 ++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index d53ed69189..0246149107 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -521,6 +521,20 @@ static const struct mtk_gate_regs sgmii_cg_regs = { .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ }
+static const struct mtk_gate_regs ssusb_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_SSUSB(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &ssusb_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ +} + static const struct mtk_gate sgmii_cgs[] = { GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2), GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3), @@ -528,6 +542,15 @@ static const struct mtk_gate sgmii_cgs[] = { GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), };
+static const struct mtk_gate ssusb_cgs[] = { + GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0), + GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1), + GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5), + GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6), + GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7), + GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8), +}; + static const struct mtk_clk_tree mt7622_clk_tree = { .xtal_rate = 25 * MHZ, .xtal2_rate = 25 * MHZ, @@ -599,7 +622,6 @@ static int mt7622_pciesys_bind(struct udevice *dev) int ret = 0;
if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) { -// PCIESYS uses in linux also 0x34 = ETHSYS reset controller ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); if (ret) debug("Warning: failed to bind reset controller\n"); @@ -631,6 +653,11 @@ static int mt7622_sgmiisys_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs); }
+static int mt7622_ssusbsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs); +} + static const struct udevice_id mt7622_apmixed_compat[] = { { .compatible = "mediatek,mt7622-apmixedsys" }, { } @@ -671,6 +698,11 @@ static const struct udevice_id mt7622_mcucfg_compat[] = { { } };
+static const struct udevice_id mt7622_ssusbsys_compat[] = { + { .compatible = "mediatek,mt7622-ssusbsys" }, + { } +}; + U_BOOT_DRIVER(mtk_mcucfg) = { .name = "mt7622-mcucfg", .id = UCLASS_SYSCON, @@ -747,3 +779,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = { .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, }; + +U_BOOT_DRIVER(mtk_clk_ssusbsys) = { + .name = "mt7622-clock-ssusbsys", + .id = UCLASS_CLK, + .of_match = mt7622_ssusbsys_compat, + .probe = mt7622_ssusbsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +};
From: Frank Wunderlich frank-w@public-files.de
adding a wdt-reboot node to mt7622 dtsi
Signed-off-by: Frank Wunderlich frank-w@public-files.de --- arch/arm/dts/mt7622.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index d0783bc9ff..fec071643e 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -142,6 +142,11 @@ reg = <0x10212000 0x800>; };
+ wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&watchdog>; + }; + gic: interrupt-controller@10300000 { compatible = "arm,gic-400"; interrupt-controller;
From: Frank Wunderlich frank-w@public-files.de
add a separate DTS for BananaPi R64 because it has 1GB RAM and SATA-Support
Signed-off-by: Frank Wunderlich frank-w@public-files.de --- v1->v2: - changed name --- arch/arm/dts/Makefile | 1 + arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 206 +++++++++++++++++++++++ 2 files changed, 207 insertions(+) create mode 100644 arch/arm/dts/mt7622-bananapi-bpi-r64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8ecf63e988..ff0e76f808 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -959,6 +959,7 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ + mt7622-bananapi-bpi-r64.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb \ diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts new file mode 100644 index 0000000000..768f15bc2c --- /dev/null +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Sam Shih sam.shih@mediatek.com + */ + +/dts-v1/; +#include "mt7622.dtsi" +#include "mt7622-u-boot.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "mt7622-bpi-r64"; + compatible = "mediatek,mt7622", "mediatek,mt7622-rfb"; + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + aliases { + spi0 = &snfi; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + + +&pinctrl { + snfi_pins: snfi-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + snor_pins: snor-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + uart0_pins: uart0 { + mux { + function = "uart"; + groups = "uart0_0_tx_rx" ; + }; + }; + + pwm_pins: pwm1 { + mux { + function = "pwm"; + groups = "pwm_ch1_0" ; + }; + }; + + watchdog_pins: watchdog-default { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "emmc"; + groups = "emmc"; + }; + + /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", + * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, + * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively + */ + conf-cmd-dat { + pins = "NDL0", "NDL1", "NDL2", + "NDL3", "NDL4", "NDL5", + "NDL6", "NDL7", "NRB"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "NCLE"; + bias-pull-down; + }; + + }; + + mmc1_pins_default: mmc1default { + mux { + function = "sd"; + groups = "sd_0"; + }; + /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", + * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, + * DAT2, DAT3, CMD, CLK for SD respectively. + */ + conf-cmd-data { + pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", + "I2S2_IN","I2S4_OUT"; + input-enable; + drive-strength = <8>; + bias-pull-up; + }; + conf-clk { + pins = "I2S3_OUT"; + drive-strength = <12>; + bias-pull-down; + }; + conf-cd { + pins = "TXD3"; + bias-pull-up; + }; + + }; +}; + +&snfi { + pinctrl-names = "default", "snfi"; + pinctrl-0 = <&snor_pins>; + pinctrl-1 = <&snfi_pins>; + status = "okay"; + + spi-flash@0{ + compatible = "jedec,spi-nor"; + reg = <0>; + u-boot,dm-pre-reloc; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + r_smpl = <1>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +};
From: Frank Wunderlich frank-w@public-files.de
asm_sel is for switching between sata and pcie mode on r64 there is GPIO90 connected to ASM1480 which switches RX/TX pairs to PCIe/SATA connector output-low means sata-controller is active
Signed-off-by: Frank Wunderlich frank-w@public-files.de Reviewed-by: Chunfeng Yun chunfeng.yun@mediatek.com --- arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 9 +++++++ arch/arm/dts/mt7622.dtsi | 31 ++++++++++++++++++++++++ 2 files changed, 40 insertions(+)
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts index 768f15bc2c..c36ec8f8d0 100644 --- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts @@ -204,3 +204,12 @@ full-duplex; }; }; + +&gpio { + /*gpio 90 for setting mode to sata*/ + asm_sel { + gpio-hog; + gpios = <90 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index fec071643e..6b4260407e 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/power/mt7629-power.h> #include <dt-bindings/reset/mt7629-reset.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h>
/ { compatible = "mediatek,mt7622"; @@ -270,6 +271,36 @@ }; };
+ sata: sata@1a200000 { + compatible = "mediatek,mtk-ahci"; + reg = <0x1a200000 0x1100>; + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, + <&pciesys MT7622_SATA_PHY_SW_RST>, + <&pciesys MT7622_SATA_PHY_REG_RST>; + reset-names = "axi", "sw", "reg"; + mediatek,phy-mode = <&pciesys>; + ports-implemented = <0x1>; + phys = <&sata_port PHY_TYPE_SATA>; + phy-names = "sata-phy"; + status = "okay"; + }; + + sata_phy: sata-phy@1a243000 { + compatible = "mediatek,generic-tphy-v1"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "okay"; + + sata_port: sata-phy@1a243000 { + reg = <0x1a243000 0x0100>; + clocks = <&topckgen CLK_TOP_ETH_500M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7622-ethsys", "syscon"; reg = <0x1b000000 0x1000>;
From: Frank Wunderlich frank-w@public-files.de
Add DTS nodes for MT7622/BPI-R64
Signed-off-by: Frank Wunderlich frank-w@public-files.de Reviewed-by: Chunfeng Yun chunfeng.yun@mediatek.com --- v1->v2: - remove clk25m as it's not needed --- arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 8 ++++ arch/arm/dts/mt7622-rfb.dts | 8 ++++ arch/arm/dts/mt7622.dtsi | 56 ++++++++++++++++++++++++ 3 files changed, 72 insertions(+)
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts index c36ec8f8d0..7cd581cf7d 100644 --- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts @@ -213,3 +213,11 @@ output-low; }; }; + +&ssusb { + status = "okay"; +}; + +&u3phy { + status = "okay"; +}; diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts index 317fc78abd..ef7d0f0270 100644 --- a/arch/arm/dts/mt7622-rfb.dts +++ b/arch/arm/dts/mt7622-rfb.dts @@ -222,3 +222,11 @@ full-duplex; }; }; + +&ssusb { + status = "okay"; +}; + +&u3phy { + status = "okay"; +}; diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 6b4260407e..5a4dab185f 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -192,6 +192,14 @@ status = "disabled"; };
+ ssusbsys: ssusbsys@1a000000 { + compatible = "mediatek,mt7622-ssusbsys", + "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pciesys: pciesys@1a100800 { compatible = "mediatek,mt7622-pciesys", "syscon"; reg = <0x1a100800 0x1000>; @@ -301,6 +309,54 @@ }; };
+ ssusb: usb@1a0c0000 { + compatible = "mediatek,mt7622-xhci", + "mediatek,mtk-xhci"; + reg = <0x1a0c0000 0x01000>, + <0x1a0c4700 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>; + clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, + <&ssusbsys CLK_SSUSB_REF_EN>, + <&ssusbsys CLK_SSUSB_MCU_EN>, + <&ssusbsys CLK_SSUSB_DMA_EN>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>, + <&u2port1 PHY_TYPE_USB2>; + status = "disabled"; + }; + + u3phy: usb-phy@1a0c4000 { + compatible = "mediatek,mt7622-u3phy", + "mediatek,generic-tphy-v1"; + reg = <0x1a0c4000 0x700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port0: usb-phy@1a0c4800 { + reg = <0x1a0c4800 0x0100>; + #phy-cells = <1>; + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; + clock-names = "ref"; + }; + + u3port0: usb-phy@1a0c4900 { + reg = <0x1a0c4900 0x0700>; + #phy-cells = <1>; + }; + + u2port1: usb-phy@1a0c5000 { + reg = <0x1a0c5000 0x0100>; + #phy-cells = <1>; + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>; + clock-names = "ref"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7622-ethsys", "syscon"; reg = <0x1b000000 0x1000>;
From: Frank Wunderlich frank-w@public-files.de
This adds USB nodes for MT7623/BPI-R2
Signed-off-by: Frank Wunderlich frank-w@public-files.de Reviewed-by: Chunfeng Yun chunfeng.yun@mediatek.com --- arch/arm/dts/mt7623.dtsi | 46 ++++++++++++++++++++++++ arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 +++++++++ 2 files changed, 62 insertions(+)
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 0452889ef8..b5a802552b 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -352,6 +352,52 @@ }; };
+ usb1: usb@1a1c0000 { + compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci"; + reg = <0x1a1c0000 0x1000>, <0x1a1c4700 0x0100>; + reg-names = "mac", "ippc"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "ref_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy1: usb-phy@1a1c4000 { + compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1"; + + reg = <0x1a1c4000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port0: usb-phy@1a1c4800 { + reg = <0x1a1c4800 0x0100>; + #phy-cells = <1>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + }; + + u3port0: usb-phy@1a1c4900 { + reg = <0x1a1c4900 0x0700>; + #phy-cells = <1>; + clocks = <&clk26m>; + clock-names = "ref"; + }; + }; + + usb2: usb@1a240000 { + compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci"; + reg = <0x1a240000 0x1000>, <0x1a244700 0x0100>; + reg-names = "mac", "ippc"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "ref_ck"; + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + status = "disabled"; + }; + u3phy2: usb-phy@1a244000 { compatible = "mediatek,generic-tphy-v1"; reg = <0x1a244000 0x0700>; diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts index bcedcf20f1..ef07369627 100644 --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts @@ -248,3 +248,19 @@ pinctrl-0 = <&uart2_pins_a>; status = "okay"; }; + +&usb1 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +};
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Frank Wunderlich