[U-Boot] [PATCH 1/4] mx6: clock: Allow enable_ipu_clock() to be built for SPL code
Allow enable_ipu_clock() to be built for SPL code. This is done in preparation for configuring the NoC registers on i.MX6QP in SPL.
Signed-off-by: Fabio Estevam festevam@gmail.com --- arch/arm/mach-imx/mx6/clock.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 366a4e3c6b..5af1ae7cf3 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1275,6 +1275,22 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return 0; }
+#ifndef CONFIG_MX6SX +void enable_ipu_clock(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; + writel(reg, &mxc_ccm->CCGR3); + + if (is_mx6dqp()) { + setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); + } +} +#endif + #ifndef CONFIG_SPL_BUILD /* * Dump some core clockes. @@ -1311,22 +1327,6 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; }
-#ifndef CONFIG_MX6SX -void enable_ipu_clock(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; - writel(reg, &mxc_ccm->CCGR3); - - if (is_mx6dqp()) { - setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); - setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); - } -} -#endif - #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \ defined(CONFIG_MX6S) static void disable_ldb_di_clock_sources(void)
The code can be made simpler by using setbits_le32(), so switch to it.
Signed-off-by: Fabio Estevam festevam@gmail.com --- arch/arm/mach-imx/mx6/clock.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 5af1ae7cf3..9951f79106 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1279,10 +1279,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) void enable_ipu_clock(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; - writel(reg, &mxc_ccm->CCGR3); + + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
if (is_mx6dqp()) { setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
Subject: [PATCH 2/4] mx6: clock: Use setbits_le32()
The code can be made simpler by using setbits_le32(), so switch to it.
Signed-off-by: Fabio Estevam festevam@gmail.com
arch/arm/mach-imx/mx6/clock.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 5af1ae7cf3..9951f79106 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1279,10 +1279,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) void enable_ipu_clock(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
- reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
- writel(reg, &mxc_ccm->CCGR3);
setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
if (is_mx6dqp()) { setbits_le32(&mxc_ccm->CCGR6,
MXC_CCM_CCGR6_PRG_CLK0_MASK);
Reviewed-by: Peng Fan peng.fan@nxp.com
-- 2.17.1
Introduce disable_ipu_clock(). This is done in preparation for configuring the NoC registers on i.MX6QP in SPL.
Afer the NoC registers are set the IPU clocks can be disabled.
Signed-off-by: Fabio Estevam festevam@gmail.com --- arch/arm/include/asm/arch-mx6/clock.h | 1 + arch/arm/mach-imx/mx6/clock.c | 12 ++++++++++++ 2 files changed, 13 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index a9481a5fea..f7760541a4 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -71,6 +71,7 @@ int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); +void disable_ipu_clock(void); int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); void enable_enet_clk(unsigned char enable); int enable_lcdif_clock(u32 base_addr, bool enable); diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 9951f79106..e1e21e37a8 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1287,6 +1287,18 @@ void enable_ipu_clock(void) setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); } } + +void disable_ipu_clock(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK); + + if (is_mx6dqp()) { + clrbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); + clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); + } +} #endif
#ifndef CONFIG_SPL_BUILD
Subject: [PATCH 3/4] mx6: clock: Introduce disable_ipu_clock()
Introduce disable_ipu_clock(). This is done in preparation for configuring the NoC registers on i.MX6QP in SPL.
Afer the NoC registers are set the IPU clocks can be disabled.
Signed-off-by: Fabio Estevam festevam@gmail.com
arch/arm/include/asm/arch-mx6/clock.h | 1 + arch/arm/mach-imx/mx6/clock.c | 12 ++++++++++++ 2 files changed, 13 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index a9481a5fea..f7760541a4 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -71,6 +71,7 @@ int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); +void disable_ipu_clock(void); int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); void enable_enet_clk(unsigned char enable); int enable_lcdif_clock(u32 base_addr, bool enable); diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 9951f79106..e1e21e37a8 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1287,6 +1287,18 @@ void enable_ipu_clock(void) setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); } }
+void disable_ipu_clock(void) +{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg
*)CCM_BASE_ADDR;
- clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
- if (is_mx6dqp()) {
clrbits_le32(&mxc_ccm->CCGR6,MXC_CCM_CCGR6_PRG_CLK0_MASK);
clrbits_le32(&mxc_ccm->CCGR3,MXC_CCM_CCGR3_IPU2_IPU_MASK);
- }
+} #endif
Reviewed-by: Peng Fan peng.fan@nxp.com
#ifndef CONFIG_SPL_BUILD
2.17.1
The NoC registers on i.MX6QP needs to be configured, otherwise some usecases in the kernel behave incorrectly, such as rotation and resize.
Currently the NoC registers are not configured in the kernel, so configure them in U-Boot like it is done in the NXP U-Boot tree.
Signed-off-by: Fabio Estevam festevam@gmail.com --- arch/arm/mach-imx/mx6/soc.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e80f1d484b..8de42408c7 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -365,6 +365,35 @@ static void init_bandgap(void) } }
+static void noc_setup(void) +{ + enable_ipu_clock(); + + writel(0x80000201, 0xbb0608); + /* Bypass IPU1 QoS generator */ + writel(0x00000002, 0x00bb048c); + /* Bypass IPU2 QoS generator */ + writel(0x00000002, 0x00bb050c); + /* Bandwidth THR for of PRE0 */ + writel(0x00000200, 0x00bb0690); + /* Bandwidth THR for of PRE1 */ + writel(0x00000200, 0x00bb0710); + /* Bandwidth THR for of PRE2 */ + writel(0x00000200, 0x00bb0790); + /* Bandwidth THR for of PRE3 */ + writel(0x00000200, 0x00bb0810); + /* Saturation THR for of PRE0 */ + writel(0x00000010, 0x00bb0694); + /* Saturation THR for of PRE1 */ + writel(0x00000010, 0x00bb0714); + /* Saturation THR for of PRE2 */ + writel(0x00000010, 0x00bb0794); + /* Saturation THR for of PRE */ + writel(0x00000010, 0x00bb0814); + + disable_ipu_clock(); +} + int arch_cpu_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -442,6 +471,9 @@ int arch_cpu_init(void)
init_src();
+ if (is_mx6dqp()) + noc_setup(); + return 0; }
Hi Fabio,
Subject: [PATCH 4/4] mx6: Allow configuring the NoC registers on i.MX6QP
The NoC registers on i.MX6QP needs to be configured, otherwise some usecases in the kernel behave incorrectly, such as rotation and resize.
Currently the NoC registers are not configured in the kernel, so configure them in U-Boot like it is done in the NXP U-Boot tree.
Signed-off-by: Fabio Estevam festevam@gmail.com
arch/arm/mach-imx/mx6/soc.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e80f1d484b..8de42408c7 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -365,6 +365,35 @@ static void init_bandgap(void) } }
+static void noc_setup(void) +{
- enable_ipu_clock();
- writel(0x80000201, 0xbb0608);
- /* Bypass IPU1 QoS generator */
- writel(0x00000002, 0x00bb048c);
- /* Bypass IPU2 QoS generator */
- writel(0x00000002, 0x00bb050c);
- /* Bandwidth THR for of PRE0 */
- writel(0x00000200, 0x00bb0690);
- /* Bandwidth THR for of PRE1 */
- writel(0x00000200, 0x00bb0710);
- /* Bandwidth THR for of PRE2 */
- writel(0x00000200, 0x00bb0790);
- /* Bandwidth THR for of PRE3 */
- writel(0x00000200, 0x00bb0810);
- /* Saturation THR for of PRE0 */
- writel(0x00000010, 0x00bb0694);
- /* Saturation THR for of PRE1 */
- writel(0x00000010, 0x00bb0714);
- /* Saturation THR for of PRE2 */
- writel(0x00000010, 0x00bb0794);
- /* Saturation THR for of PRE */
- writel(0x00000010, 0x00bb0814);
- disable_ipu_clock();
Why disable ipu clock?
Regards, Peng.
+}
int arch_cpu_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -442,6 +471,9 @@ int arch_cpu_init(void)
init_src();
- if (is_mx6dqp())
noc_setup();- return 0;
}
-- 2.17.1
Hi Peng,
On Sun, Jul 14, 2019 at 10:55 PM Peng Fan peng.fan@nxp.com wrote:
Why disable ipu clock?
Once the NoC registers are configured we no longer need to keep the IPU clocks turned on.
Thanks,
Fabio Estevam
Subject: [PATCH 4/4] mx6: Allow configuring the NoC registers on i.MX6QP
The NoC registers on i.MX6QP needs to be configured, otherwise some usecases in the kernel behave incorrectly, such as rotation and resize.
Currently the NoC registers are not configured in the kernel, so configure them in U-Boot like it is done in the NXP U-Boot tree.
Signed-off-by: Fabio Estevam festevam@gmail.com
arch/arm/mach-imx/mx6/soc.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e80f1d484b..8de42408c7 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -365,6 +365,35 @@ static void init_bandgap(void) } }
+static void noc_setup(void) +{
- enable_ipu_clock();
- writel(0x80000201, 0xbb0608);
- /* Bypass IPU1 QoS generator */
- writel(0x00000002, 0x00bb048c);
- /* Bypass IPU2 QoS generator */
- writel(0x00000002, 0x00bb050c);
- /* Bandwidth THR for of PRE0 */
- writel(0x00000200, 0x00bb0690);
- /* Bandwidth THR for of PRE1 */
- writel(0x00000200, 0x00bb0710);
- /* Bandwidth THR for of PRE2 */
- writel(0x00000200, 0x00bb0790);
- /* Bandwidth THR for of PRE3 */
- writel(0x00000200, 0x00bb0810);
- /* Saturation THR for of PRE0 */
- writel(0x00000010, 0x00bb0694);
- /* Saturation THR for of PRE1 */
- writel(0x00000010, 0x00bb0714);
- /* Saturation THR for of PRE2 */
- writel(0x00000010, 0x00bb0794);
- /* Saturation THR for of PRE */
- writel(0x00000010, 0x00bb0814);
- disable_ipu_clock();
+}
int arch_cpu_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -442,6 +471,9 @@ int arch_cpu_init(void)
init_src();
- if (is_mx6dqp())
noc_setup();- return 0;
}
Reviewed-by: Peng Fan peng.fan@nxp.com
-- 2.17.1
Hi Stefano,
On Fri, Jul 12, 2019 at 9:33 AM Fabio Estevam festevam@gmail.com wrote:
The NoC registers on i.MX6QP needs to be configured, otherwise some usecases in the kernel behave incorrectly, such as rotation and resize.
Currently the NoC registers are not configured in the kernel, so configure them in U-Boot like it is done in the NXP U-Boot tree.
Signed-off-by: Fabio Estevam festevam@gmail.com
It seems that only the first patch of this series got applied.
Could you please consider applying patches 2-4 too?
Thanks
On 24/10/19 15:47, Fabio Estevam wrote:
Hi Stefano,
On Fri, Jul 12, 2019 at 9:33 AM Fabio Estevam festevam@gmail.com wrote:
The NoC registers on i.MX6QP needs to be configured, otherwise some usecases in the kernel behave incorrectly, such as rotation and resize.
Currently the NoC registers are not configured in the kernel, so configure them in U-Boot like it is done in the NXP U-Boot tree.
Signed-off-by: Fabio Estevam festevam@gmail.com
It seems that only the first patch of this series got applied.
Could you please consider applying patches 2-4 too?
Something went wrong, patches were already set to "Accepted" in patchwork. I have picked up the rest of series, thanks for remind.
Regards, Stefano
Hi Fabio,
On 03/11/19 13:17, Stefano Babic wrote:
On 24/10/19 15:47, Fabio Estevam wrote:
Hi Stefano,
On Fri, Jul 12, 2019 at 9:33 AM Fabio Estevam festevam@gmail.com wrote:
The NoC registers on i.MX6QP needs to be configured, otherwise some usecases in the kernel behave incorrectly, such as rotation and resize.
Currently the NoC registers are not configured in the kernel, so configure them in U-Boot like it is done in the NXP U-Boot tree.
Signed-off-by: Fabio Estevam festevam@gmail.com
It seems that only the first patch of this series got applied.
Could you please consider applying patches 2-4 too?
Something went wrong, patches were already set to "Accepted" in patchwork. I have picked up the rest of series, thanks for remind.
I found a good reason why they were out. Patch 4 breaks the build for mx6sxsabresd because enable_[disable]ipu is called (of course, it should not be).
Could you take a look and repost ? Thanks !
Best regards, Stefano
Hi Stefano,
On Sun, Nov 3, 2019 at 1:06 PM Stefano Babic sbabic@denx.de wrote:
I found a good reason why they were out. Patch 4 breaks the build for mx6sxsabresd because enable_[disable]ipu is called (of course, it should not be).
Could you take a look and repost ? Thanks !
Thanks for the feedback.
I have fixed it and submitted a v2.
Thanks
Subject: [PATCH 1/4] mx6: clock: Allow enable_ipu_clock() to be built for SPL code
Allow enable_ipu_clock() to be built for SPL code. This is done in preparation for configuring the NoC registers on i.MX6QP in SPL.
Signed-off-by: Fabio Estevam festevam@gmail.com
arch/arm/mach-imx/mx6/clock.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 366a4e3c6b..5af1ae7cf3 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1275,6 +1275,22 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return 0; }
+#ifndef CONFIG_MX6SX +void enable_ipu_clock(void) +{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg
*)CCM_BASE_ADDR;
- int reg;
- reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
- writel(reg, &mxc_ccm->CCGR3);
- if (is_mx6dqp()) {
setbits_le32(&mxc_ccm->CCGR6,MXC_CCM_CCGR6_PRG_CLK0_MASK);
setbits_le32(&mxc_ccm->CCGR3,MXC_CCM_CCGR3_IPU2_IPU_MASK);
- }
+} +#endif
#ifndef CONFIG_SPL_BUILD /*
- Dump some core clockes.
@@ -1311,22 +1327,6 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; }
-#ifndef CONFIG_MX6SX -void enable_ipu_clock(void) -{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg
*)CCM_BASE_ADDR;
- int reg;
- reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
- writel(reg, &mxc_ccm->CCGR3);
- if (is_mx6dqp()) {
setbits_le32(&mxc_ccm->CCGR6,MXC_CCM_CCGR6_PRG_CLK0_MASK);
setbits_le32(&mxc_ccm->CCGR3,MXC_CCM_CCGR3_IPU2_IPU_MASK);
- }
-} -#endif
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \ defined(CONFIG_MX6S) static void disable_ldb_di_clock_sources(void)
Reviewed-by: Peng Fan peng.fan@nxp.com
-- 2.17.1
Hi Stefano,
Could this series be applied, please?
On Fri, Jul 12, 2019 at 9:32 AM Fabio Estevam festevam@gmail.com wrote:
Allow enable_ipu_clock() to be built for SPL code. This is done in preparation for configuring the NoC registers on i.MX6QP in SPL.
Signed-off-by: Fabio Estevam festevam@gmail.com
arch/arm/mach-imx/mx6/clock.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 366a4e3c6b..5af1ae7cf3 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1275,6 +1275,22 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return 0; }
+#ifndef CONFIG_MX6SX +void enable_ipu_clock(void) +{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;int reg;reg = readl(&mxc_ccm->CCGR3);reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;writel(reg, &mxc_ccm->CCGR3);if (is_mx6dqp()) {setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);}+} +#endif
#ifndef CONFIG_SPL_BUILD /*
- Dump some core clockes.
@@ -1311,22 +1327,6 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; }
-#ifndef CONFIG_MX6SX -void enable_ipu_clock(void) -{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;int reg;reg = readl(&mxc_ccm->CCGR3);reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;writel(reg, &mxc_ccm->CCGR3);if (is_mx6dqp()) {setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);}-} -#endif
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \ defined(CONFIG_MX6S) static void disable_ldb_di_clock_sources(void) -- 2.17.1
participants (3)
-
Fabio Estevam -
Peng Fan -
Stefano Babic