For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded to higher address to support large space.

Signed-off-by: York Sun yorksun@freescale.com CC: Prabhakar Kushwaha prabhakar@freescale.com --- drivers/misc/fsl_ifc.c | 7 +++++++ include/fsl_ifc.h | 1 + 2 files changed, 8 insertions(+)

diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index be61973..3902e9f 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -162,3 +162,10 @@ void init_early_memctl_regs(void) set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); #endif } + +void init_final_memctl_regs(void) +{ +#ifdef CONFIG_SYS_CSPR0_FINAL + set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL); +#endif +} diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 58a6efd..630e4b4 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -784,6 +784,7 @@ enum ifc_nand_fir_opcodes {

extern void print_ifc_regs(void); extern void init_early_memctl_regs(void); +void init_final_memctl_regs(void);

#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)