If we attempt to compile serial_sh.c for a system which lacks HSCIF support (e.g. R8A7740), we see the following compilation error:

In file included from drivers/serial/serial_sh.c:20: drivers/serial/serial_sh.c: In function ‘sh_serial_init_generic’: drivers/serial/serial_sh.h:429:35: warning: implicit declaration of function ‘sci_HSSRR_out’; did you mean ‘sci_SCSCR_out’? [-Wimplicit-function-declaration] 429 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | ^~~~ drivers/serial/serial_sh.c:62:17: note: in expansion of macro ‘sci_out’ 62 | sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8); | ^~~~~~~

To fix this, only try to support access to the HSSRR register for SoCs where it actually exists.

Fixes: bbe36e29ca2c ('serial: sh: Add HSCIF support for R-Car SoC') Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Cc: Hai Pham hai.pham.ud@renesas.com Cc: Marek Vasut marek.vasut+renesas@mailbox.org Cc: Simon Glass sjg@chromium.org --- drivers/serial/serial_sh.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 20cda5dbe272..5e543dbf3d58 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -58,8 +58,10 @@ static void sh_serial_init_generic(struct uart_port *port) sci_out(port, SCSPTR, 0x0003); #endif

+#if IS_ENABLED(CONFIG_RCAR_GEN2) || IS_ENABLED(CONFIG_RCAR_GEN3) || IS_ENABLED(CONFIG_RCAR_GEN4) if (port->type == PORT_HSCIF) sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8); +#endif }

static void

Import bindings for the Clock Pulse Generator (CPG) module in the Renesas RZ/G2L SoC family.

This patch is based on the dt-bindings in Linux v6.5.

Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- include/dt-bindings/clock/r9a07g044-cpg.h | 220 ++++++++++++++++++++++ 1 file changed, 220 insertions(+) create mode 100644 include/dt-bindings/clock/r9a07g044-cpg.h

diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h new file mode 100644 index 000000000000..0bb17ff1a01a --- /dev/null +++ b/include/dt-bindings/clock/r9a07g044-cpg.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* R9A07G044 CPG Core Clocks */ +#define R9A07G044_CLK_I 0 +#define R9A07G044_CLK_I2 1 +#define R9A07G044_CLK_G 2 +#define R9A07G044_CLK_S0 3 +#define R9A07G044_CLK_S1 4 +#define R9A07G044_CLK_SPI0 5 +#define R9A07G044_CLK_SPI1 6 +#define R9A07G044_CLK_SD0 7 +#define R9A07G044_CLK_SD1 8 +#define R9A07G044_CLK_M0 9 +#define R9A07G044_CLK_M1 10 +#define R9A07G044_CLK_M2 11 +#define R9A07G044_CLK_M3 12 +#define R9A07G044_CLK_M4 13 +#define R9A07G044_CLK_HP 14 +#define R9A07G044_CLK_TSU 15 +#define R9A07G044_CLK_ZT 16 +#define R9A07G044_CLK_P0 17 +#define R9A07G044_CLK_P1 18 +#define R9A07G044_CLK_P2 19 +#define R9A07G044_CLK_AT 20 +#define R9A07G044_OSCCLK 21 +#define R9A07G044_CLK_P0_DIV2 22 + +/* R9A07G044 Module Clocks */ +#define R9A07G044_CA55_SCLK 0 +#define R9A07G044_CA55_PCLK 1 +#define R9A07G044_CA55_ATCLK 2 +#define R9A07G044_CA55_GICCLK 3 +#define R9A07G044_CA55_PERICLK 4 +#define R9A07G044_CA55_ACLK 5 +#define R9A07G044_CA55_TSCLK 6 +#define R9A07G044_GIC600_GICCLK 7 +#define R9A07G044_IA55_CLK 8 +#define R9A07G044_IA55_PCLK 9 +#define R9A07G044_MHU_PCLK 10 +#define R9A07G044_SYC_CNT_CLK 11 +#define R9A07G044_DMAC_ACLK 12 +#define R9A07G044_DMAC_PCLK 13 +#define R9A07G044_OSTM0_PCLK 14 +#define R9A07G044_OSTM1_PCLK 15 +#define R9A07G044_OSTM2_PCLK 16 +#define R9A07G044_MTU_X_MCK_MTU3 17 +#define R9A07G044_POE3_CLKM_POE 18 +#define R9A07G044_GPT_PCLK 19 +#define R9A07G044_POEG_A_CLKP 20 +#define R9A07G044_POEG_B_CLKP 21 +#define R9A07G044_POEG_C_CLKP 22 +#define R9A07G044_POEG_D_CLKP 23 +#define R9A07G044_WDT0_PCLK 24 +#define R9A07G044_WDT0_CLK 25 +#define R9A07G044_WDT1_PCLK 26 +#define R9A07G044_WDT1_CLK 27 +#define R9A07G044_WDT2_PCLK 28 +#define R9A07G044_WDT2_CLK 29 +#define R9A07G044_SPI_CLK2 30 +#define R9A07G044_SPI_CLK 31 +#define R9A07G044_SDHI0_IMCLK 32 +#define R9A07G044_SDHI0_IMCLK2 33 +#define R9A07G044_SDHI0_CLK_HS 34 +#define R9A07G044_SDHI0_ACLK 35 +#define R9A07G044_SDHI1_IMCLK 36 +#define R9A07G044_SDHI1_IMCLK2 37 +#define R9A07G044_SDHI1_CLK_HS 38 +#define R9A07G044_SDHI1_ACLK 39 +#define R9A07G044_GPU_CLK 40 +#define R9A07G044_GPU_AXI_CLK 41 +#define R9A07G044_GPU_ACE_CLK 42 +#define R9A07G044_ISU_ACLK 43 +#define R9A07G044_ISU_PCLK 44 +#define R9A07G044_H264_CLK_A 45 +#define R9A07G044_H264_CLK_P 46 +#define R9A07G044_CRU_SYSCLK 47 +#define R9A07G044_CRU_VCLK 48 +#define R9A07G044_CRU_PCLK 49 +#define R9A07G044_CRU_ACLK 50 +#define R9A07G044_MIPI_DSI_PLLCLK 51 +#define R9A07G044_MIPI_DSI_SYSCLK 52 +#define R9A07G044_MIPI_DSI_ACLK 53 +#define R9A07G044_MIPI_DSI_PCLK 54 +#define R9A07G044_MIPI_DSI_VCLK 55 +#define R9A07G044_MIPI_DSI_LPCLK 56 +#define R9A07G044_LCDC_CLK_A 57 +#define R9A07G044_LCDC_CLK_P 58 +#define R9A07G044_LCDC_CLK_D 59 +#define R9A07G044_SSI0_PCLK2 60 +#define R9A07G044_SSI0_PCLK_SFR 61 +#define R9A07G044_SSI1_PCLK2 62 +#define R9A07G044_SSI1_PCLK_SFR 63 +#define R9A07G044_SSI2_PCLK2 64 +#define R9A07G044_SSI2_PCLK_SFR 65 +#define R9A07G044_SSI3_PCLK2 66 +#define R9A07G044_SSI3_PCLK_SFR 67 +#define R9A07G044_SRC_CLKP 68 +#define R9A07G044_USB_U2H0_HCLK 69 +#define R9A07G044_USB_U2H1_HCLK 70 +#define R9A07G044_USB_U2P_EXR_CPUCLK 71 +#define R9A07G044_USB_PCLK 72 +#define R9A07G044_ETH0_CLK_AXI 73 +#define R9A07G044_ETH0_CLK_CHI 74 +#define R9A07G044_ETH1_CLK_AXI 75 +#define R9A07G044_ETH1_CLK_CHI 76 +#define R9A07G044_I2C0_PCLK 77 +#define R9A07G044_I2C1_PCLK 78 +#define R9A07G044_I2C2_PCLK 79 +#define R9A07G044_I2C3_PCLK 80 +#define R9A07G044_SCIF0_CLK_PCK 81 +#define R9A07G044_SCIF1_CLK_PCK 82 +#define R9A07G044_SCIF2_CLK_PCK 83 +#define R9A07G044_SCIF3_CLK_PCK 84 +#define R9A07G044_SCIF4_CLK_PCK 85 +#define R9A07G044_SCI0_CLKP 86 +#define R9A07G044_SCI1_CLKP 87 +#define R9A07G044_IRDA_CLKP 88 +#define R9A07G044_RSPI0_CLKB 89 +#define R9A07G044_RSPI1_CLKB 90 +#define R9A07G044_RSPI2_CLKB 91 +#define R9A07G044_CANFD_PCLK 92 +#define R9A07G044_GPIO_HCLK 93 +#define R9A07G044_ADC_ADCLK 94 +#define R9A07G044_ADC_PCLK 95 +#define R9A07G044_TSU_PCLK 96 + +/* R9A07G044 Resets */ +#define R9A07G044_CA55_RST_1_0 0 +#define R9A07G044_CA55_RST_1_1 1 +#define R9A07G044_CA55_RST_3_0 2 +#define R9A07G044_CA55_RST_3_1 3 +#define R9A07G044_CA55_RST_4 4 +#define R9A07G044_CA55_RST_5 5 +#define R9A07G044_CA55_RST_6 6 +#define R9A07G044_CA55_RST_7 7 +#define R9A07G044_CA55_RST_8 8 +#define R9A07G044_CA55_RST_9 9 +#define R9A07G044_CA55_RST_10 10 +#define R9A07G044_CA55_RST_11 11 +#define R9A07G044_CA55_RST_12 12 +#define R9A07G044_GIC600_GICRESET_N 13 +#define R9A07G044_GIC600_DBG_GICRESET_N 14 +#define R9A07G044_IA55_RESETN 15 +#define R9A07G044_MHU_RESETN 16 +#define R9A07G044_DMAC_ARESETN 17 +#define R9A07G044_DMAC_RST_ASYNC 18 +#define R9A07G044_SYC_RESETN 19 +#define R9A07G044_OSTM0_PRESETZ 20 +#define R9A07G044_OSTM1_PRESETZ 21 +#define R9A07G044_OSTM2_PRESETZ 22 +#define R9A07G044_MTU_X_PRESET_MTU3 23 +#define R9A07G044_POE3_RST_M_REG 24 +#define R9A07G044_GPT_RST_C 25 +#define R9A07G044_POEG_A_RST 26 +#define R9A07G044_POEG_B_RST 27 +#define R9A07G044_POEG_C_RST 28 +#define R9A07G044_POEG_D_RST 29 +#define R9A07G044_WDT0_PRESETN 30 +#define R9A07G044_WDT1_PRESETN 31 +#define R9A07G044_WDT2_PRESETN 32 +#define R9A07G044_SPI_RST 33 +#define R9A07G044_SDHI0_IXRST 34 +#define R9A07G044_SDHI1_IXRST 35 +#define R9A07G044_GPU_RESETN 36 +#define R9A07G044_GPU_AXI_RESETN 37 +#define R9A07G044_GPU_ACE_RESETN 38 +#define R9A07G044_ISU_ARESETN 39 +#define R9A07G044_ISU_PRESETN 40 +#define R9A07G044_H264_X_RESET_VCP 41 +#define R9A07G044_H264_CP_PRESET_P 42 +#define R9A07G044_CRU_CMN_RSTB 43 +#define R9A07G044_CRU_PRESETN 44 +#define R9A07G044_CRU_ARESETN 45 +#define R9A07G044_MIPI_DSI_CMN_RSTB 46 +#define R9A07G044_MIPI_DSI_ARESET_N 47 +#define R9A07G044_MIPI_DSI_PRESET_N 48 +#define R9A07G044_LCDC_RESET_N 49 +#define R9A07G044_SSI0_RST_M2_REG 50 +#define R9A07G044_SSI1_RST_M2_REG 51 +#define R9A07G044_SSI2_RST_M2_REG 52 +#define R9A07G044_SSI3_RST_M2_REG 53 +#define R9A07G044_SRC_RST 54 +#define R9A07G044_USB_U2H0_HRESETN 55 +#define R9A07G044_USB_U2H1_HRESETN 56 +#define R9A07G044_USB_U2P_EXL_SYSRST 57 +#define R9A07G044_USB_PRESETN 58 +#define R9A07G044_ETH0_RST_HW_N 59 +#define R9A07G044_ETH1_RST_HW_N 60 +#define R9A07G044_I2C0_MRST 61 +#define R9A07G044_I2C1_MRST 62 +#define R9A07G044_I2C2_MRST 63 +#define R9A07G044_I2C3_MRST 64 +#define R9A07G044_SCIF0_RST_SYSTEM_N 65 +#define R9A07G044_SCIF1_RST_SYSTEM_N 66 +#define R9A07G044_SCIF2_RST_SYSTEM_N 67 +#define R9A07G044_SCIF3_RST_SYSTEM_N 68 +#define R9A07G044_SCIF4_RST_SYSTEM_N 69 +#define R9A07G044_SCI0_RST 70 +#define R9A07G044_SCI1_RST 71 +#define R9A07G044_IRDA_RST 72 +#define R9A07G044_RSPI0_RST 73 +#define R9A07G044_RSPI1_RST 74 +#define R9A07G044_RSPI2_RST 75 +#define R9A07G044_CANFD_RSTP_N 76 +#define R9A07G044_CANFD_RSTC_N 77 +#define R9A07G044_GPIO_RSTN 78 +#define R9A07G044_GPIO_PORT_RESETN 79 +#define R9A07G044_GPIO_SPARE_RESETN 80 +#define R9A07G044_ADC_PRESETN 81 +#define R9A07G044_ADC_ADRST_N 82 +#define R9A07G044_TSU_PRESETN 83 + +#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */

Import bindings for the Port Function Control (PFC) module in the Renesas RZ/G2L SoC family.

This patch is based on the dt-bindings in Linux v6.5.

Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- include/dt-bindings/pinctrl/rzg2l-pinctrl.h | 23 +++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 include/dt-bindings/pinctrl/rzg2l-pinctrl.h

diff --git a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h new file mode 100644 index 000000000000..c78ed5e5efb7 --- /dev/null +++ b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G2L family pinctrl bindings. + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_RZG2L_PINCTRL_H +#define __DT_BINDINGS_RZG2L_PINCTRL_H + +#define RZG2L_PINS_PER_PORT 8 + +/* + * Create the pin index from its bank and position numbers and store in + * the upper 16 bits the alternate function identifier + */ +#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16)) + +/* Convert a port and pin label to its global pin index */ +#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin)) + +#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */

Import bindings for the Interrupt Controller (IRQC) module in the Renesas RZ/G2L SoC family.

This patch is based on the dt-bindings in Linux v6.5.

Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- .../interrupt-controller/irqc-rzg2l.h | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/irqc-rzg2l.h

diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h new file mode 100644 index 000000000000..34ce778885a1 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G2L family IRQC bindings. + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_IRQC_RZG2L_H +#define __DT_BINDINGS_IRQC_RZG2L_H + +/* NMI maps to SPI0 */ +#define RZG2L_NMI 0 + +/* IRQ0-7 map to SPI1-8 */ +#define RZG2L_IRQ0 1 +#define RZG2L_IRQ1 2 +#define RZG2L_IRQ2 3 +#define RZG2L_IRQ3 4 +#define RZG2L_IRQ4 5 +#define RZG2L_IRQ5 6 +#define RZG2L_IRQ6 7 +#define RZG2L_IRQ7 8 + +#endif /* __DT_BINDINGS_IRQC_RZG2L_H */

The Renesas RZ/G2L family includes the following ARM SoCs:

* RZ/G2L (r9a07g044l) * RZ/G2LC (r9a07g044c) * RZ/G2UL (r9a07g043u) * RZ/V2L (r9a07g054l)

Support for individual SoCs and evaluation boards will be added in separate patches.

Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- arch/arm/mach-rmobile/Kconfig | 13 +++++++++++++ arch/arm/mach-rmobile/Kconfig.rzg2l | 12 ++++++++++++ arch/arm/mach-rmobile/include/mach/rmobile.h | 2 ++ arch/arm/mach-rmobile/include/mach/rzg2l.h | 13 +++++++++++++ 4 files changed, 40 insertions(+) create mode 100644 arch/arm/mach-rmobile/Kconfig.rzg2l create mode 100644 arch/arm/mach-rmobile/include/mach/rzg2l.h

diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 3061ccd34c8b..fd240832d83d 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -66,6 +66,18 @@ config RZN1 select SYSRESET_SYSCON imply CMD_DM

+config RZG2L + prompt "Renesas RZ/G2L Family ARM SoCs" + select RCAR_64 + select GICV3 + imply MULTI_DTB_FIT + imply MULTI_DTB_FIT_USER_DEFINED_AREA + imply SYS_MALLOC_F + imply RENESAS_SDHI + help + Enable support for the Renesas RZ/G2L family of SoCs, including the + the RZ/G2L itself (based on the R9A07G044 SoC). + endchoice

config SYS_SOC @@ -75,5 +87,6 @@ source "arch/arm/mach-rmobile/Kconfig.32" source "arch/arm/mach-rmobile/Kconfig.64" source "arch/arm/mach-rmobile/Kconfig.rza1" source "arch/arm/mach-rmobile/Kconfig.rzn1" +source "arch/arm/mach-rmobile/Kconfig.rzg2l"

endif diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l b/arch/arm/mach-rmobile/Kconfig.rzg2l new file mode 100644 index 000000000000..37ff6cd34160 --- /dev/null +++ b/arch/arm/mach-rmobile/Kconfig.rzg2l @@ -0,0 +1,12 @@ +# Copyright (C) 2023 Renesas Electronics Corporation +# SPDX-License-Identifier: GPL-2.0+ + +if RZG2L + +config MULTI_DTB_FIT_UNCOMPRESS_SZ + default 0x80000 if TARGET_RZG2L_SMARC_EVK + +config MULTI_DTB_FIT_USER_DEF_ADDR + default 0x49000000 if TARGET_RZG2L_SMARC_EVK + +endif diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index a14c2aad0a68..d326d5545a6f 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -19,6 +19,8 @@ #elif defined(CONFIG_RCAR_GEN4) #include <asm/arch/rcar-gen4-base.h> #elif defined(CONFIG_R7S72100) +#elif defined(CONFIG_RZG2L) +#include <asm/arch/rzg2l.h> #else #error "SOC Name not defined" #endif diff --git a/arch/arm/mach-rmobile/include/mach/rzg2l.h b/arch/arm/mach-rmobile/include/mach/rzg2l.h new file mode 100644 index 000000000000..057df5cb9d46 --- /dev/null +++ b/arch/arm/mach-rmobile/include/mach/rzg2l.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RZ/G2L SoC Family support. + * Copyright (C) 2023 Renesas Electronics Corporation + */ + +#ifndef __ASM_ARCH_RZG2L_H +#define __ASM_ARCH_RZG2L_H + +#define GICD_BASE 0x11900000 +#define GICR_BASE 0x11960000 + +#endif /* __ASM_ARCH_RZG2L_H */

Add a config option for the R9A07G044L SoC used in the RZ/G2L so that we can make use of this in the subsequent driver patches.

Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- arch/arm/mach-rmobile/Kconfig.rzg2l | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l b/arch/arm/mach-rmobile/Kconfig.rzg2l index 37ff6cd34160..266f82c18085 100644 --- a/arch/arm/mach-rmobile/Kconfig.rzg2l +++ b/arch/arm/mach-rmobile/Kconfig.rzg2l @@ -3,6 +3,11 @@

if RZG2L

+config R9A07G044L + bool "Renesas R9A07G044L SoC" + help + Enable support for the R9A07G044L SoC used in the RZ/G2L. + config MULTI_DTB_FIT_UNCOMPRESS_SZ default 0x80000 if TARGET_RZG2L_SMARC_EVK

This driver provides clock and reset control for the Renesas RZ/G2L (R9A07G044) SoC. It consists of two parts:

* driver code which is applicable to all SoCs in the RZ/G2L family

* static data describing the clocks and resets which are specific to the R9A07G044 SoC.

clk_set_rate() and clk_get_rate() are implemented only for the clocks that are actually used in u-boot.

The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind function is called before the SCIF (serial port) driver is probed. This is required so that we can de-assert the relevant reset signal during the serial driver probe function.

This patch is based on the corresponding Linux v6.5 driver.

Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- arch/arm/mach-rmobile/Kconfig | 1 + arch/arm/mach-rmobile/Kconfig.rzg2l | 1 + drivers/clk/renesas/Kconfig | 9 + drivers/clk/renesas/Makefile | 2 + drivers/clk/renesas/r9a07g044-cpg.c | 384 +++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.c | 502 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 318 ++++++++++++++++++ 7 files changed, 1217 insertions(+) create mode 100644 drivers/clk/renesas/r9a07g044-cpg.c create mode 100644 drivers/clk/renesas/rzg2l-cpg.c create mode 100644 drivers/clk/renesas/rzg2l-cpg.h

diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index fd240832d83d..fc37f6c79e50 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -74,6 +74,7 @@ config RZG2L imply MULTI_DTB_FIT_USER_DEFINED_AREA imply SYS_MALLOC_F imply RENESAS_SDHI + imply CLK_RZG2L help Enable support for the Renesas RZ/G2L family of SoCs, including the the RZ/G2L itself (based on the R9A07G044 SoC). diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l b/arch/arm/mach-rmobile/Kconfig.rzg2l index 266f82c18085..7d268e8c366a 100644 --- a/arch/arm/mach-rmobile/Kconfig.rzg2l +++ b/arch/arm/mach-rmobile/Kconfig.rzg2l @@ -5,6 +5,7 @@ if RZG2L

config R9A07G044L bool "Renesas R9A07G044L SoC" + imply CLK_R9A07G044 help Enable support for the R9A07G044L SoC used in the RZ/G2L.

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 437a82cd48be..927d62cf99a3 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -156,3 +156,12 @@ config CLK_R9A06G032 depends on CLK_RENESAS help Enable this to support the clocks on Renesas R9A06G032 SoC. + +config CLK_RZG2L + bool "Renesas RZ/G2L family clock support" + depends on CLK_RENESAS + select DM_RESET + +config CLK_R9A07G044 + bool "RZ/G2L (R9A07G044L) clock support" + depends on CLK_RZG2L diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 48373e61b901..df7e225e9ca4 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -23,3 +23,5 @@ obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o +obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o +obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c new file mode 100644 index 000000000000..e215db7caf15 --- /dev/null +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G2L CPG driver + * + * Copyright (C) 2021-2023 Renesas Electronics Corp. + */ + +#include <common.h> +#include <dm/device.h> +#include <dt-bindings/clock/r9a07g044-cpg.h> +#include <linux/clk-provider.h> + +#include "rzg2l-cpg.h" + +/* Divider tables */ +static const struct clk_div_table dtable_1_8[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {0, 0}, +}; + +static const struct clk_div_table dtable_1_32[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {4, 32}, + {0, 0}, +}; + +static const struct clk_div_table dtable_16_128[] = { + {0, 16}, + {1, 32}, + {2, 64}, + {3, 128}, + {0, 0}, +}; + +/* Mux clock tables */ +static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; +static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" }; +static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; +static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; +static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; + +static const struct { + struct cpg_core_clk common[56]; +} core_clks = { + .common = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + + /* Internal Core Clocks */ + DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), + DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), + DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), + DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), + + DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), + DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6), + + DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), + + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), + DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), + DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), + DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), + DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), + + DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), + DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), + + DEF_FIXED(".pll2_533_div2", CLK_PLL2_533_DIV2, CLK_PLL2_533, 1, 2), + + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), + DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), + DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), + DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), + DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), + + DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), + DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), + DEF_MUX_RO(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2), + DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL), + DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2), + DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4), + DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2, + DIVDSILPCLK, dtable_16_128), + + /* Core output clk */ + DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8), + DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32), + DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), + DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), + DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32), + DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), + DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32), + DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), + DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), + DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2), + DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), + DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), + DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi), + DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi), + DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), + DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), + DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8), + DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1), + DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2), + DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2), + DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT), + DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1), + DEF_FIXED("M4", R9A07G044_CLK_M4, CLK_DIV_DSI_LPCLK, 1, 1), + }, +}; + +static const struct { + struct rzg2l_mod_clk common[79]; +} mod_clks = { + .common = { + DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1, + 0x514, 0), + DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2, + 0x518, 0), + DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, + 0x518, 1), + DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1, + 0x52c, 0), + DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, + 0x52c, 1), + DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0, + 0x534, 0), + DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, + 0x534, 1), + DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, + 0x534, 2), + DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0, + 0x538, 0), + DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0, + 0x540, 0), + DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0, + 0x544, 0), + DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0, + 0x544, 1), + DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0, + 0x544, 2), + DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0, + 0x544, 3), + DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, + 0x548, 0), + DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, + 0x548, 1), + DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0, + 0x548, 2), + DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK, + 0x548, 3), + DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1, + 0x550, 0), + DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0, + 0x550, 1), + DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4, + 0x554, 0), + DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4, + 0x554, 1), + DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0, + 0x554, 2), + DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1, + 0x554, 3), + DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4, + 0x554, 4), + DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4, + 0x554, 5), + DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1, + 0x554, 6), + DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1, + 0x554, 7), + DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G, + 0x558, 0), + DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1, + 0x558, 1), + DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, + 0x558, 2), + DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2, + 0x564, 0), + DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2, + 0x564, 1), + DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT, + 0x564, 2), + DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0, + 0x564, 3), + DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1, + 0x568, 0), + DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2, + 0x568, 1), + DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1, + 0x568, 2), + DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2, + 0x568, 3), + DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3, + 0x568, 4), + DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4, + 0x568, 5), + DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0, + 0x56c, 0), + DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT, + 0x56c, 0), + DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3, + 0x56c, 1), + DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, + 0x570, 0), + DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 1), + DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0, + 0x570, 2), + DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 3), + DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0, + 0x570, 4), + DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 5), + DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0, + 0x570, 6), + DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 7), + DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1, + 0x578, 0), + DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1, + 0x578, 1), + DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1, + 0x578, 2), + DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1, + 0x578, 3), + DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0, + 0x57c, 0), + DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT, + 0x57c, 0), + DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0, + 0x57c, 1), + DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT, + 0x57c, 1), + DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, + 0x580, 0), + DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0, + 0x580, 1), + DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0, + 0x580, 2), + DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0, + 0x580, 3), + DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 0), + DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 1), + DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 2), + DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 3), + DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 4), + DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, + 0x588, 0), + DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0, + 0x588, 1), + DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0, + 0x590, 0), + DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0, + 0x590, 1), + DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0, + 0x590, 2), + DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0, + 0x594, 0), + DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, + 0x598, 0), + DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU, + 0x5a8, 0), + DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0, + 0x5a8, 1), + DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU, + 0x5ac, 0), + }, +}; + +static const struct rzg2l_reset r9a07g044_resets[] = { + DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0), + DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1), + DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0), + DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0), + DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0), + DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1), + DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2), + DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0), + DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0), + DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0), + DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1), + DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2), + DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3), + DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0), + DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1), + DEF_RST(R9A07G044_SPI_RST, 0x850, 0), + DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0), + DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1), + DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0), + DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1), + DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2), + DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0), + DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1), + DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2), + DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0), + DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1), + DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2), + DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0), + DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0), + DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1), + DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2), + DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3), + DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0), + DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1), + DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2), + DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3), + DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0), + DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1), + DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0), + DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1), + DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2), + DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3), + DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0), + DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1), + DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2), + DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3), + DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4), + DEF_RST(R9A07G044_SCI0_RST, 0x888, 0), + DEF_RST(R9A07G044_SCI1_RST, 0x888, 1), + DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0), + DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1), + DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2), + DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0), + DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1), + DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0), + DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1), + DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0), + DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1), + DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0), +}; + +const struct rzg2l_cpg_info r9a07g044_cpg_info = { + /* Core Clocks */ + .core_clks = core_clks.common, + .num_core_clks = ARRAY_SIZE(core_clks.common), + + /* Module Clocks */ + .mod_clks = mod_clks.common, + .num_mod_clks = ARRAY_SIZE(mod_clks.common), + .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1, + + /* Resets */ + .resets = r9a07g044_resets, + .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ + + .has_clk_mon_regs = true, +}; + +static const struct udevice_id r9a07g044_cpg_ids[] = { + { + .compatible = "renesas,r9a07g044-cpg", + .data = (unsigned long)&r9a07g044_cpg_info, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(r9a07g044_cpg) = { + .name = "r9a07g044-cpg", + .id = UCLASS_NOP, + .of_match = r9a07g044_cpg_ids, + .bind = rzg2l_cpg_bind, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c new file mode 100644 index 000000000000..1e8ea109b5ca --- /dev/null +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -0,0 +1,502 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G2L Clock Pulse Generator + * + * Copyright (C) 2021-2023 Renesas Electronics Corp. + * + * Based on renesas-cpg-mssr.c + * + * Copyright (C) 2015 Glider bvba + * Copyright (C) 2013 Ideas On Board SPRL + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#include <common.h> +#include <asm/io.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <dm/lists.h> +#include <dt-bindings/clock/renesas-cpg-mssr.h> +#include <linux/clk-provider.h> +#include <linux/iopoll.h> +#include <reset-uclass.h> +#include <reset.h> + +#include "rzg2l-cpg.h" + +#define CLK_MON_R(reg) (0x180 + (reg)) + +static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int id); +static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char *name); + +struct rzg2l_cpg_data { + void __iomem *base; + struct rzg2l_cpg_info *info; +}; + +/* The top 16 bits of the clock ID are used to identify if it is a core clock or + * a module clock. + */ +#define CPG_CLK_TYPE_SHIFT 16 +#define CPG_CLK_ID_MASK 0xffff +#define CPG_CLK_ID(x) ((x) & CPG_CLK_ID_MASK) +#define CPG_CLK_PACK(type, id) (((type) << CPG_CLK_TYPE_SHIFT) | CPG_CLK_ID(id)) + +static inline bool is_mod_clk(unsigned int id) +{ + return (id >> CPG_CLK_TYPE_SHIFT) == CPG_MOD; +} + +static int rzg2l_cpg_clk_set(struct clk *clk, bool enable) +{ + struct rzg2l_cpg_data *data = + (struct rzg2l_cpg_data *)dev_get_driver_data(clk->dev); + unsigned int cpg_clk_id = CPG_CLK_ID(clk->id); + const struct rzg2l_mod_clk *mod_clk = NULL; + u32 value; + unsigned int i; + + dev_dbg(clk->dev, "%s %s clock %u\n", enable ? "enable" : "disable", + is_mod_clk(clk->id) ? "module" : "core", cpg_clk_id); + if (!is_mod_clk(clk->id)) { + dev_err(clk->dev, "ID %lu is not a module clock\n", clk->id); + return -EINVAL; + } + + for (i = 0; i < data->info->num_mod_clks; i++) { + if (data->info->mod_clks[i].id == cpg_clk_id) { + mod_clk = &data->info->mod_clks[i]; + break; + } + } + + if (!mod_clk) { + dev_err(clk->dev, "Module clock %u not found\n", cpg_clk_id); + return -ENODEV; + } + + value = (BIT(mod_clk->bit) << 16); + if (enable) + value |= BIT(mod_clk->bit); + writel(value, data->base + mod_clk->off); + + if (enable && readl_poll_timeout(data->base + CLK_MON_R(mod_clk->off), + value, (value & BIT(mod_clk->bit)), + 10)) { + dev_err(clk->dev, "Timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int rzg2l_cpg_clk_enable(struct clk *clk) +{ + return rzg2l_cpg_clk_set(clk, true); +} + +static int rzg2l_cpg_clk_disable(struct clk *clk) +{ + return rzg2l_cpg_clk_set(clk, false); +} + +static int rzg2l_cpg_clk_of_xlate(struct clk *clk, + struct ofnode_phandle_args *args) +{ + struct rzg2l_cpg_data *data = + (struct rzg2l_cpg_data *)dev_get_driver_data(clk->dev); + u32 cpg_clk_type, cpg_clk_id; + bool found = false; + unsigned int i; + + if (args->args_count != 2) { + dev_dbg(clk->dev, "Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + cpg_clk_type = args->args[0]; + cpg_clk_id = args->args[1]; + + switch (cpg_clk_type) { + case CPG_CORE: + for (i = 0; i < data->info->num_core_clks; i++) { + if (data->info->core_clks[i].id == cpg_clk_id) { + found = true; + break; + } + } + if (!found) { + dev_dbg(clk->dev, + "Invalid second argument %u: Must be a valid core clock ID\n", + cpg_clk_id); + return -EINVAL; + } + break; + case CPG_MOD: + for (i = 0; i < data->info->num_mod_clks; i++) { + if (data->info->mod_clks[i].id == cpg_clk_id) { + found = true; + break; + } + } + if (!found) { + dev_dbg(clk->dev, + "Invalid second argument %u: Must be a valid module clock ID\n", + cpg_clk_id); + return -EINVAL; + } + break; + default: + dev_dbg(clk->dev, + "Invalid first argument %u: Must be CPG_CORE or CPG_MOD\n", + cpg_clk_type); + return -EINVAL; + } + + clk->id = CPG_CLK_PACK(cpg_clk_type, cpg_clk_id); + + return 0; +} + +static ulong rzg2l_sdhi_clk_get_rate(struct udevice *dev, const struct cpg_core_clk *cc) +{ + struct rzg2l_cpg_data *data = + (struct rzg2l_cpg_data *)dev_get_driver_data(dev); + ulong offset = CPG_CONF_OFFSET(cc->conf); + int shift = CPG_CONF_BITPOS(cc->conf); + u32 mask = CPG_CONF_BITMASK(cc->conf); + unsigned int sel; + + sel = (readl(data->base + offset) >> shift) & mask; + + if (!sel || sel > cc->num_parents) { + dev_err(dev, "Invalid SEL_SDHI%d_SET value %u\n", shift / 4, sel); + return -EIO; + } + return rzg2l_cpg_clk_get_rate_by_name(dev, cc->parent_names[sel - 1]); +} + +static ulong rzg2l_div_clk_get_rate(struct udevice *dev, const struct cpg_core_clk *cc) +{ + struct rzg2l_cpg_data *data = + (struct rzg2l_cpg_data *)dev_get_driver_data(dev); + ulong offset = CPG_CONF_OFFSET(cc->conf); + int shift = CPG_CONF_BITPOS(cc->conf); + u32 mask = CPG_CONF_BITMASK(cc->conf); + unsigned int sel, i; + + sel = (readl(data->base + offset) >> shift) & mask; + + for (i = 0; cc->dtable[i].div; i++) { + if (cc->dtable[i].val == sel) + return rzg2l_cpg_clk_get_rate_by_id(dev, cc->parent) / cc->dtable[i].div; + } + dev_err(dev, "Invalid selector value %u for clock %s\n", sel, cc->name); + return -EINVAL; +} + +static ulong rzg2l_core_clk_get_rate(struct udevice *dev, const struct cpg_core_clk *cc) +{ + switch (cc->type) { + case CLK_TYPE_FF: + ulong parent_rate = rzg2l_cpg_clk_get_rate_by_id(dev, cc->parent); + return parent_rate * cc->mult / cc->div; + case CLK_TYPE_IN: + struct clk clk_in; + clk_get_by_name(dev, cc->name, &clk_in); + return clk_get_rate(&clk_in); + case CLK_TYPE_SD_MUX: + return rzg2l_sdhi_clk_get_rate(dev, cc); + case CLK_TYPE_DIV: + return rzg2l_div_clk_get_rate(dev, cc); + default: + dev_err(dev, "get_rate needed for clock %u, type %d\n", cc->id, cc->type); + return -ENOSYS; + } +} + +static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int id) +{ + struct rzg2l_cpg_data *data = + (struct rzg2l_cpg_data *)dev_get_driver_data(dev); + unsigned int cpg_clk_id = CPG_CLK_ID(id); + unsigned int i; + + if (is_mod_clk(id)) { + for (i = 0; i < data->info->num_mod_clks; i++) { + if (data->info->mod_clks[i].id == cpg_clk_id) + return rzg2l_cpg_clk_get_rate_by_id(dev, + data->info->mod_clks[i].parent); + } + + dev_err(dev, "Module clock ID %u not found\n", cpg_clk_id); + return -ENODEV; + } + + for (i = 0; i < data->info->num_core_clks; i++) { + if (data->info->core_clks[i].id == cpg_clk_id) + return rzg2l_core_clk_get_rate(dev, &data->info->core_clks[i]); + } + + dev_err(dev, "Core clock ID %u not found\n", cpg_clk_id); + return -ENODEV; +} + +static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char *name) +{ + struct rzg2l_cpg_data *data = + (struct rzg2l_cpg_data *)dev_get_driver_data(dev); + unsigned int i; + + for (i = 0; i < data->info->num_mod_clks; i++) { + if (!strcmp(name, data->info->mod_clks[i].name)) + return rzg2l_cpg_clk_get_rate_by_id(dev, data->info->mod_clks[i].parent); + } + for (i = 0; i < data->info->num_core_clks; i++) { + if (!strcmp(name, data->info->core_clks[i].name)) + return rzg2l_core_clk_get_rate(dev, &data->info->core_clks[i]); + } + + dev_err(dev, "Clock name %s not found\n", name); + return -EINVAL; +} + +static ulong rzg2l_cpg_clk_get_rate(struct clk *clk) +{ + return rzg2l_cpg_clk_get_rate_by_id(clk->dev, clk->id); +} + +static ulong rzg2l_sdhi_clk_set_rate(struct udevice *dev, const struct cpg_core_clk *cc, ulong rate) +{ + struct rzg2l_cpg_data *data = + (struct rzg2l_cpg_data *)dev_get_driver_data(dev); + ulong offset = CPG_CONF_OFFSET(cc->conf); + int shift = CPG_CONF_BITPOS(cc->conf); + int channel, new_sel, prev_sel; + ulong target_rate; + unsigned int i; + u32 value; + + prev_sel = (readl(data->base + offset) >> shift) & 0x3; + channel = shift / 4; + + /* Round the requested rate down, unless it is below the minimum + * supported rate. Assume that the parent clock names are listed in + * order of descending rate. + */ + for (i = 0; i < cc->num_parents; i++) { + target_rate = rzg2l_cpg_clk_get_rate_by_name(dev, cc->parent_names[i]); + if (rate >= target_rate) { + new_sel = i + 1; + break; + } + } + if (!new_sel) + new_sel = cc->num_parents - 1; + + if (new_sel == prev_sel) + return target_rate; + dev_dbg(dev, "sdhi set_rate rate=%lu target_rate=%lu sel=%d\n", + rate, target_rate, new_sel); + + /* + * As per the HW manual, we should not directly switch from 533 MHz to + * 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz) + * to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first, + * and then switch to the target setting (2’b01 (533 MHz) or 2’b10 + * (400 MHz)). + */ + if (new_sel != SEL_SDHI_266MHz && prev_sel != SEL_SDHI_266MHz) { + u32 waitbit; + int ret; + + dev_dbg(dev, "sdhi set_rate via 266MHz\n"); + value = (SEL_SDHI_WRITE_ENABLE | SEL_SDHI_266MHz) << shift; + writel(value, data->base + offset); + + /* Wait for the switch to complete. */ + waitbit = channel ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS; + ret = readl_poll_timeout(data->base + CPG_CLKSTATUS, value, + !(value & waitbit), + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); + if (ret) { + dev_err(dev, "Failed to switch SDHI%d clock source\n", channel); + return -EIO; + } + } + + value = (SEL_SDHI_WRITE_ENABLE | new_sel) << shift; + writel(value, data->base + offset); + + return target_rate; +} + +static ulong rzg2l_core_clk_set_rate(struct udevice *dev, const struct cpg_core_clk *cc, ulong rate) +{ + if (cc->type == CLK_TYPE_SD_MUX) + return rzg2l_sdhi_clk_set_rate(dev, cc, rate); + + /* The sdhi driver calls clk_set_rate for SD0_DIV4 and SD1_DIV4, even + * though they're in a fixed relationship with SD0 and SD1 respectively. + * To allow the driver to proceed, simply return the current rates + * without making any change. + */ + if (cc->id == CLK_SD0_DIV4 || cc->id == CLK_SD1_DIV4) + return rzg2l_core_clk_get_rate(dev, cc); + + dev_err(dev, "set_rate needed for clock %u, type %d\n", cc->id, cc->type); + return -ENOSYS; +} + +static ulong rzg2l_cpg_clk_set_rate_by_id(struct udevice *dev, unsigned int id, ulong rate) +{ + struct rzg2l_cpg_data *data = + (struct rzg2l_cpg_data *)dev_get_driver_data(dev); + unsigned int cpg_clk_id = CPG_CLK_ID(id); + unsigned int i; + + if (is_mod_clk(id)) { + for (i = 0; i < data->info->num_mod_clks; i++) { + if (data->info->mod_clks[i].id == cpg_clk_id) + return rzg2l_cpg_clk_set_rate_by_id(dev, + data->info->mod_clks[i].parent, + rate); + } + + dev_err(dev, "Module clock ID %u not found\n", cpg_clk_id); + return -ENODEV; + } + + for (i = 0; i < data->info->num_core_clks; i++) { + if (data->info->core_clks[i].id == cpg_clk_id) + return rzg2l_core_clk_set_rate(dev, &data->info->core_clks[i], rate); + } + + dev_err(dev, "Core clock ID %u not found\n", cpg_clk_id); + return -ENODEV; +} + +static ulong rzg2l_cpg_clk_set_rate(struct clk *clk, ulong rate) +{ + return rzg2l_cpg_clk_set_rate_by_id(clk->dev, clk->id, rate); +} + +static const struct clk_ops rzg2l_cpg_clk_ops = { + .enable = rzg2l_cpg_clk_enable, + .disable = rzg2l_cpg_clk_disable, + .of_xlate = rzg2l_cpg_clk_of_xlate, + .get_rate = rzg2l_cpg_clk_get_rate, + .set_rate = rzg2l_cpg_clk_set_rate, +}; + +U_BOOT_DRIVER(rzg2l_cpg_clk) = { + .name = "rzg2l-cpg-clk", + .id = UCLASS_CLK, + .ops = &rzg2l_cpg_clk_ops, + .flags = DM_FLAG_VITAL, +}; + +static int rzg2l_cpg_rst_set(struct reset_ctl *reset_ctl, bool asserted) +{ + struct rzg2l_cpg_data *data = + (struct rzg2l_cpg_data *)dev_get_driver_data(reset_ctl->dev); + const struct rzg2l_reset *rst; + u32 value; + + dev_dbg(reset_ctl->dev, "%s %lu\n", asserted ? "assert" : "deassert", reset_ctl->id); + if (reset_ctl->id >= data->info->num_resets) { + dev_err(reset_ctl->dev, "Invalid reset id %lu\n", reset_ctl->id); + return -EINVAL; + } + rst = &data->info->resets[reset_ctl->id]; + + value = BIT(rst->bit) << 16; + if (!asserted) + value |= BIT(rst->bit); + writel(value, data->base + rst->off); + + return 0; +} + +static int rzg2l_cpg_rst_assert(struct reset_ctl *reset_ctl) +{ + return rzg2l_cpg_rst_set(reset_ctl, true); +} + +static int rzg2l_cpg_rst_deassert(struct reset_ctl *reset_ctl) +{ + return rzg2l_cpg_rst_set(reset_ctl, false); +} + +static int rzg2l_cpg_rst_of_xlate(struct reset_ctl *reset_ctl, + struct ofnode_phandle_args *args) +{ + struct rzg2l_cpg_data *data = + (struct rzg2l_cpg_data *)dev_get_driver_data(reset_ctl->dev); + + if (args->args[0] >= data->info->num_resets) + return -EINVAL; + + reset_ctl->id = args->args[0]; + return 0; +} + +static const struct reset_ops rzg2l_cpg_rst_ops = { + .rst_assert = rzg2l_cpg_rst_assert, + .rst_deassert = rzg2l_cpg_rst_deassert, + .of_xlate = rzg2l_cpg_rst_of_xlate, +}; + +U_BOOT_DRIVER(rzg2l_cpg_rst) = { + .name = "rzg2l-cpg-rst", + .id = UCLASS_RESET, + .ops = &rzg2l_cpg_rst_ops, + .flags = DM_FLAG_VITAL, +}; + +int rzg2l_cpg_bind(struct udevice *parent) +{ + struct udevice *cdev, *rdev; + struct rzg2l_cpg_data *data; + struct driver *drv; + int ret; + + data = devm_kmalloc(parent, sizeof(*data), 0); + if (!data) + return -ENOMEM; + + data->base = dev_read_addr_ptr(parent); + if (!data->base) + return -EINVAL; + + data->info = (struct rzg2l_cpg_info *)dev_get_driver_data(parent); + if (!data->info) + return -EINVAL; + + drv = lists_driver_lookup_name("rzg2l-cpg-clk"); + if (!drv) + return -ENOENT; + + ret = device_bind_with_driver_data(parent, drv, parent->name, + (ulong)data, dev_ofnode(parent), + &cdev); + if (ret) + return ret; + + drv = lists_driver_lookup_name("rzg2l-cpg-rst"); + if (!drv) { + device_unbind(cdev); + return -ENOENT; + } + + ret = device_bind_with_driver_data(parent, drv, parent->name, + (ulong)data, dev_ofnode(parent), + &rdev); + if (ret) + device_unbind(cdev); + + return ret; +} diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h new file mode 100644 index 000000000000..f7a9a2156319 --- /dev/null +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -0,0 +1,318 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * RZ/G2L Clock Pulse Generator + * + * Copyright (C) 2021-2023 Renesas Electronics Corp. + * + */ + +#ifndef __RENESAS_RZG2L_CPG_H__ +#define __RENESAS_RZG2L_CPG_H__ + +#define CPG_SIPLL5_STBY (0x140) +#define CPG_SIPLL5_CLK1 (0x144) +#define CPG_SIPLL5_CLK3 (0x14C) +#define CPG_SIPLL5_CLK4 (0x150) +#define CPG_SIPLL5_CLK5 (0x154) +#define CPG_SIPLL5_MON (0x15C) +#define CPG_PL1_DDIV (0x200) +#define CPG_PL2_DDIV (0x204) +#define CPG_PL3A_DDIV (0x208) +#define CPG_PL6_DDIV (0x210) +#define CPG_PL2SDHI_DSEL (0x218) +#define CPG_CLKSTATUS (0x280) +#define CPG_PL3_SSEL (0x408) +#define CPG_PL6_SSEL (0x414) +#define CPG_PL6_ETH_SSEL (0x418) +#define CPG_PL5_SDIV (0x420) +#define CPG_RST_MON (0x680) +#define CPG_OTHERFUNC1_REG (0xBE8) + +#define CPG_SIPLL5_STBY_RESETB BIT(0) +#define CPG_SIPLL5_STBY_RESETB_WEN BIT(16) +#define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18) +#define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20) +#define CPG_SIPLL5_CLK4_RESV_LSB (0xFF) +#define CPG_SIPLL5_MON_PLL5_LOCK BIT(4) + +#define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16) + +#define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16) +#define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24) + +#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) +#define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) + +#define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 20000 + +/* n = 0/1/2 for PLL1/4/6 */ +#define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) +#define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) + +#define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12) + +#define DDIV_PACK(offset, bitpos, size) \ + (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) +#define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2) +#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) +#define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2) +#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) +#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) +#define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) +#define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2) + +#define SEL_PLL_PACK(offset, bitpos, size) \ + (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) + +#define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) +#define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1) +#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) +#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) + +#define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2) +#define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2) + +#define SEL_SDHI_533MHz 1 +#define SEL_SDHI_400MHz 2 +#define SEL_SDHI_266MHz 3 +#define SEL_SDHI_WRITE_ENABLE 0x10000 + +/* Unpack CPG conf value create by DDIV_PACK() or SEL_PLL_PACK(). */ +#define CPG_CONF_OFFSET(x) ((x) >> 20) +#define CPG_CONF_BITPOS(x) (((x) >> 12) & 0xff) +#define CPG_CONF_SIZE(x) (((x) >> 8) & 0xf) +#define CPG_CONF_BITMASK(x) GENMASK(CPG_CONF_SIZE(x) - 1, 0) + +#define EXTAL_FREQ_IN_MEGA_HZ (24) + +/** + * Definitions of CPG Core Clocks + * + * These include: + * - Clock outputs exported to DT + * - External input clocks + * - Internal CPG clocks + */ +struct cpg_core_clk { + const char *name; + unsigned int id; + unsigned int parent; + unsigned int div; + unsigned int mult; + unsigned int type; + unsigned int conf; + const struct clk_div_table *dtable; + const char * const *parent_names; + int flag; + int mux_flags; + int num_parents; +}; + +enum clk_types { + /* Generic */ + CLK_TYPE_IN, /* External Clock Input */ + CLK_TYPE_FF, /* Fixed Factor Clock */ + CLK_TYPE_SAM_PLL, + + /* Clock with divider */ + CLK_TYPE_DIV, + + /* Clock with clock source selector */ + CLK_TYPE_MUX, + + /* Clock with SD clock source selector */ + CLK_TYPE_SD_MUX, + + /* Clock for SIPLL5 */ + CLK_TYPE_SIPLL5, + + /* Clock for PLL5_4 clock source selector */ + CLK_TYPE_PLL5_4_MUX, + + /* Clock for DSI divider */ + CLK_TYPE_DSI_DIV, + +}; + +#define DEF_TYPE(_name, _id, _type...) \ + { .name = _name, .id = _id, .type = _type } +#define DEF_BASE(_name, _id, _type, _parent...) \ + DEF_TYPE(_name, _id, _type, .parent = _parent) +#define DEF_SAMPLL(_name, _id, _parent, _conf) \ + DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) +#define DEF_INPUT(_name, _id) \ + DEF_TYPE(_name, _id, CLK_TYPE_IN) +#define DEF_FIXED(_name, _id, _parent, _mult, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) +#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ + DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ + .parent = _parent, .dtable = _dtable, \ + .flag = CLK_DIVIDER_HIWORD_MASK) +#define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ + DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ + .parent = _parent, .dtable = _dtable, \ + .flag = CLK_DIVIDER_READ_ONLY) +#define DEF_MUX(_name, _id, _conf, _parent_names) \ + DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ + .parent_names = _parent_names, \ + .num_parents = ARRAY_SIZE(_parent_names), \ + .mux_flags = CLK_MUX_HIWORD_MASK) +#define DEF_MUX_RO(_name, _id, _conf, _parent_names) \ + DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ + .parent_names = _parent_names, \ + .num_parents = ARRAY_SIZE(_parent_names), \ + .mux_flags = CLK_MUX_READ_ONLY) +#define DEF_SD_MUX(_name, _id, _conf, _parent_names) \ + DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \ + .parent_names = _parent_names, \ + .num_parents = ARRAY_SIZE(_parent_names)) +#define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ + DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) +#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \ + DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \ + .parent_names = _parent_names, \ + .num_parents = ARRAY_SIZE(_parent_names)) +#define DEF_DSI_DIV(_name, _id, _parent, _flag) \ + DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag) + +/** + * struct rzg2l_mod_clk - Module Clocks definitions + * + * @name: handle between common and hardware-specific interfaces + * @id: clock index in array containing all Core and Module Clocks + * @parent: id of parent clock + * @off: register offset + * @bit: ON/MON bit + * @is_coupled: flag to indicate coupled clock + */ +struct rzg2l_mod_clk { + const char *name; + unsigned int id; + unsigned int parent; + u16 off; + u8 bit; + bool is_coupled; +}; + +#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ + { \ + .name = (_name), \ + .id = (_id), \ + .parent = (_parent), \ + .off = (_off), \ + .bit = (_bit), \ + .is_coupled = (_is_coupled), \ + } + +#define DEF_MOD(_name, _id, _parent, _off, _bit) \ + DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false) + +#define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ + DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true) + +/** + * struct rzg2l_reset - Reset definitions + * + * @off: register offset + * @bit: reset bit + * @monbit: monitor bit in CPG_RST_MON register, -1 if none + */ +struct rzg2l_reset { + u16 off; + u8 bit; + s8 monbit; +}; + +#define DEF_RST_MON(_id, _off, _bit, _monbit) \ + [_id] = { \ + .off = (_off), \ + .bit = (_bit), \ + .monbit = (_monbit) \ + } +#define DEF_RST(_id, _off, _bit) \ + DEF_RST_MON(_id, _off, _bit, -1) + +/** + * struct rzg2l_cpg_info - SoC-specific CPG Description + * + * @core_clks: Array of Core Clock definitions + * @num_core_clks: Number of entries in core_clks[] + * + * @mod_clks: Array of Module Clock definitions + * @num_mod_clks: Number of entries in mod_clks[] + * @num_hw_mod_clks: Number of Module Clocks supported by the hardware + * + * @resets: Array of Module Reset definitions + * @num_resets: Number of entries in resets[] + * + * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers + */ +struct rzg2l_cpg_info { + /* Core Clocks */ + const struct cpg_core_clk *core_clks; + unsigned int num_core_clks; + + /* Module Clocks */ + const struct rzg2l_mod_clk *mod_clks; + unsigned int num_mod_clks; + unsigned int num_hw_mod_clks; + + /* Resets */ + const struct rzg2l_reset *resets; + unsigned int num_resets; + + bool has_clk_mon_regs; +}; + +extern const struct rzg2l_cpg_info r9a07g044_cpg_info; + +int rzg2l_cpg_bind(struct udevice *parent); + +/* Clock IDs start at an offset to avoid overlapping with core & module clock + * IDs defined in the dt-bindings headers. + */ +enum clk_ids { + /* External Input Clocks */ + CLK_EXTAL = 0x100, + + /* Internal Core Clocks */ + CLK_OSC_DIV1000 = 0x200, + CLK_PLL1, + CLK_PLL2, + CLK_PLL2_DIV2, + CLK_PLL2_DIV2_8, + CLK_PLL2_DIV2_10, + CLK_PLL3, + CLK_PLL3_400, + CLK_PLL3_533, + CLK_M2_DIV2, + CLK_PLL3_DIV2, + CLK_PLL3_DIV2_2, + CLK_PLL3_DIV2_4, + CLK_PLL3_DIV2_4_2, + CLK_SEL_PLL3_3, + CLK_DIV_PLL3_C, + CLK_PLL4, + CLK_PLL5, + CLK_PLL5_FOUTPOSTDIV, + CLK_PLL5_FOUT1PH0, + CLK_PLL5_FOUT3, + CLK_PLL5_250, + CLK_PLL6, + CLK_PLL6_250, + CLK_P1_DIV2, + CLK_PLL2_800, + CLK_PLL2_SDHI_533, + CLK_PLL2_SDHI_400, + CLK_PLL2_SDHI_266, + CLK_SD0_DIV4, + CLK_SD1_DIV4, + CLK_SEL_GPU2, + CLK_SEL_PLL5_4, + CLK_DSI_DIV, + CLK_PLL2_533, + CLK_PLL2_533_DIV2, + CLK_DIV_DSI_LPCLK, +}; + +#endif

The RZ/G2L family uses CONFIG_RCAR_64 but does not share a common PFC driver with the R-Car gen3 & gen4 boards.

Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- arch/arm/mach-rmobile/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index fc37f6c79e50..91f544c78337 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -9,7 +9,6 @@ config RCAR_64 select PHY select PINCONF select PINCTRL - select PINCTRL_PFC select POSITION_INDEPENDENT imply CMD_FS_UUID imply CMD_GPT @@ -29,6 +28,7 @@ config RCAR_GEN3 bool "Renesas ARM SoCs R-Car Gen3 (64bit)" select RCAR_64 select SUPPORT_SPL + select PINCTRL_PFC imply SPL imply SPL_BOARD_INIT imply SPL_GZIP @@ -43,6 +43,7 @@ config RCAR_GEN3 config RCAR_GEN4 bool "Renesas ARM SoCs R-Car Gen4 (64bit)" select RCAR_64 + select PINCTRL_PFC

config RZA1 prompt "Renesas ARM SoCs RZ/A1 (32bit)"

This driver provides pinctrl and gpio control for the Renesas RZ/G2L (R9A07G044) SoC.

This patch is based on the corresponding Linux v6.5 driver.

Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- arch/arm/mach-rmobile/Kconfig | 1 + drivers/pinctrl/renesas/Kconfig | 9 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/rzg2l-pfc.c | 906 ++++++++++++++++++++++++++++ 4 files changed, 917 insertions(+) create mode 100644 drivers/pinctrl/renesas/rzg2l-pfc.c

diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 91f544c78337..973e84fcf7ba 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -76,6 +76,7 @@ config RZG2L imply SYS_MALLOC_F imply RENESAS_SDHI imply CLK_RZG2L + imply PINCTRL_RZG2L help Enable support for the Renesas RZ/G2L family of SoCs, including the the RZ/G2L itself (based on the R9A07G044 SoC). diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 0ea39b4a3f11..b58a6990befe 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -138,6 +138,15 @@ config PINCTRL_PFC_R7S72100 help Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.

+config PINCTRL_RZG2L + bool "Renesas RZ/G2L family pin control driver" + depends on PINCTRL + depends on PINCTRL_GENERIC + depends on PINCONF + help + Support the pin function controller (PFC) on the Renesas RZ/G2L SoC + family. + endif

config PINCTRL_RZN1 diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 1a61c39d8471..9e1cdd42769a 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -21,3 +21,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o +obj-$(CONFIG_PINCTRL_RZG2L) += rzg2l-pfc.o diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c new file mode 100644 index 000000000000..59c037ba944a --- /dev/null +++ b/drivers/pinctrl/renesas/rzg2l-pfc.c @@ -0,0 +1,906 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G2L Pin Function Controller + * + * Copyright (C) 2021-2023 Renesas Electronics Corp. + */ + +#include <common.h> +#include <asm-generic/gpio.h> +#include <asm/io.h> +#include <asm/types.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <dm/lists.h> +#include <dm/pinctrl.h> +#include <clk.h> +#include <reset.h> + +/* PIN capabilities */ +#define PIN_CFG_IOLH_A BIT(0) +#define PIN_CFG_IOLH_B BIT(1) +#define PIN_CFG_SR BIT(2) +#define PIN_CFG_IEN BIT(3) +#define PIN_CFG_PUPD BIT(4) +#define PIN_CFG_IO_VMC_SD0 BIT(5) +#define PIN_CFG_IO_VMC_SD1 BIT(6) +#define PIN_CFG_IO_VMC_QSPI BIT(7) +#define PIN_CFG_IO_VMC_ETH0 BIT(8) +#define PIN_CFG_IO_VMC_ETH1 BIT(9) +#define PIN_CFG_FILONOFF BIT(10) +#define PIN_CFG_FILNUM BIT(11) +#define PIN_CFG_FILCLKSEL BIT(12) + +#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ + PIN_CFG_SR | \ + PIN_CFG_PUPD | \ + PIN_CFG_FILONOFF | \ + PIN_CFG_FILNUM | \ + PIN_CFG_FILCLKSEL) + +#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ + PIN_CFG_FILONOFF | \ + PIN_CFG_FILNUM | \ + PIN_CFG_FILCLKSEL) + +/* GPIO port data macros: + * n indicates number of pins in the port, a is the register index + * and f is pin configuration capabilities supported. + */ +#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) +#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) +#define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20) +#define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) + +/* Dedicated pin data macros: + * BIT(31) indicates dedicated pin, p is the register index while + * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits + * (b * 8) and f is the pin configuration capabilities supported. + */ +#define RZG2L_SINGLE_PIN BIT(31) +#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ + ((p) << 24) | ((b) << 20) | (f)) +#define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24) +#define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) +#define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) + +/* Pinmux data encoded in the device tree uses: + * 16 lower bits [15:0] for pin identifier + * 16 higher bits [31:16] for pin mux function + */ +#define MUX_PIN_ID_MASK GENMASK(15, 0) +#define MUX_FUNC_MASK GENMASK(31, 16) +#define RZG2L_PINS_PER_PORT 8 +#define RZG2L_PINMUX_TO_PORT(conf) (((conf) & MUX_PIN_ID_MASK) / RZG2L_PINS_PER_PORT) +#define RZG2L_PINMUX_TO_PIN(conf) (((conf) & MUX_PIN_ID_MASK) % RZG2L_PINS_PER_PORT) +#define RZG2L_PINMUX_TO_FUNC(conf) (((conf) & MUX_FUNC_MASK) >> 16) + +/* Register offsets and values. */ +#define P(n) (0x0000 + 0x10 + (n)) +#define PM(n) (0x0100 + 0x20 + (n) * 2) +#define PMC(n) (0x0200 + 0x10 + (n)) +#define PFC(n) (0x0400 + 0x40 + (n) * 4) +#define PIN(n) (0x0800 + 0x10 + (n)) +#define IOLH(n) (0x1000 + (n) * 8) +#define IEN(n) (0x1800 + (n) * 8) +#define PWPR (0x3014) +#define SD_CH(n) (0x3000 + (n) * 4) +#define QSPI (0x3008) + +#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ +#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ + +#define PWPR_B0WI BIT(7) /* Bit Write Disable */ +#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ + +#define PM_MASK 0x03 +#define PVDD_MASK 0x01 +#define PFC_MASK 0x07 +#define IEN_MASK 0x01 +#define IOLH_MASK 0x03 + +#define PM_HIGH_Z 0x0 +#define PM_INPUT 0x1 +#define PM_OUTPUT 0x2 +#define PM_OUTPUT_IEN 0x3 + +struct rzg2l_pfc_driver_data { + uint num_dedicated_pins; + uint num_ports; + const u32 *gpio_configs; +}; + +struct rzg2l_pfc_data { + void __iomem *base; + uint num_dedicated_pins; + uint num_ports; + uint num_pins; + const u32 *gpio_configs; + bool pfc_enabled; +}; + +struct rzg2l_dedicated_configs { + const char *name; + u32 config; +}; + +/* + * We need to ensure that the module clock is enabled and all resets are + * de-asserted before using either the gpio or pinctrl functionality. Error + * handling can be quite simple here as if the PFC cannot be enabled then we + * will not be able to progress with the boot anyway. + */ +static int rzg2l_pfc_enable(struct udevice *dev) +{ + struct rzg2l_pfc_data *data = + (struct rzg2l_pfc_data *)dev_get_driver_data(dev); + struct reset_ctl_bulk rsts; + struct clk clk; + int ret; + + if (data->pfc_enabled) + return 0; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get gpio module clock\n"); + return ret; + } + + ret = clk_enable(&clk); + if (ret < 0) { + dev_err(dev, "failed to enable gpio module clock\n"); + return ret; + } + + ret = reset_get_bulk(dev, &rsts); + if (ret < 0) { + dev_err(dev, "failed to get reset lines\n"); + return ret; + } + + ret = reset_deassert_bulk(&rsts); + if (ret < 0) { + dev_err(dev, "failed to de-assert reset lines\n"); + return ret; + } + + data->pfc_enabled = true; + return 0; +} + +static inline bool rzg2l_port_validate(struct rzg2l_pfc_data *data, + u32 port, u8 pin) +{ + return (port < data->num_ports) && + (pin < RZG2L_GPIO_PORT_GET_PINCNT(data->gpio_configs[port])); +} + +/* Decode a pin selector, returning the port index and setting *pin to the pin + * index. Returns -1 on error, which can be checked directly or by calling + * rzg2l_port_validate(). + */ +static int rzg2l_selector_decode(struct rzg2l_pfc_data *data, + unsigned int selector, + u8 *pin) +{ + int port; + + selector -= data->num_dedicated_pins; + for (port = 0; port < data->num_ports; port++) { + u8 num_pins = RZG2L_GPIO_PORT_GET_PINCNT(data->gpio_configs[port]); + if (selector < num_pins) { + *pin = (u8)selector; + return port; + } + selector -= num_pins; + } + return -EINVAL; +} + +static unsigned int rzg2l_selector_encode(struct rzg2l_pfc_data *data, + u32 port, u8 pin) +{ + unsigned int selector = data->num_dedicated_pins + pin; + u32 i; + + for (i = 0; i < port; i++) + selector += RZG2L_GPIO_PORT_GET_PINCNT(data->gpio_configs[i]); + + return selector; +} + +static void rzg2l_gpio_set(struct rzg2l_pfc_data *data, + u32 port, u8 pin, bool value) +{ + u8 reg8 = readb(data->base + P(port)); + + if (value) + writeb(reg8 | BIT(pin), data->base + P(port)); + else + writeb(reg8 & ~BIT(pin), data->base + P(port)); +} + +static int rzg2l_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct rzg2l_pfc_data *data = + (struct rzg2l_pfc_data *)dev_get_driver_data(dev); + u32 port = RZG2L_PINMUX_TO_PORT(offset); + u8 pin = RZG2L_PINMUX_TO_PIN(offset); + u16 pm_state; + + pm_state = (readw(data->base + PM(port)) >> (pin * 2)) & PM_MASK; + switch (pm_state) { + case PM_INPUT: + return !!(readb(data->base + PIN(port)) & BIT(pin)); + case PM_OUTPUT: + case PM_OUTPUT_IEN: + return !!(readb(data->base + P(port)) & BIT(pin)); + default: /* PM_HIGH_Z */ + return 0; + } +} + +static int rzg2l_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct rzg2l_pfc_data *data = + (struct rzg2l_pfc_data *)dev_get_driver_data(dev); + u32 port = RZG2L_PINMUX_TO_PORT(offset); + u8 pin = RZG2L_PINMUX_TO_PIN(offset); + + rzg2l_gpio_set(data, port, pin, (bool)value); + return 0; +} + +static void rzg2l_gpio_set_direction(struct rzg2l_pfc_data *data, + u32 port, u8 pin, bool output) +{ + u16 reg16; + + reg16 = readw(data->base + PM(port)); + reg16 &= ~(PM_MASK << (pin * 2)); + + reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (pin * 2); + writew(reg16, data->base + PM(port)); +} + +static int rzg2l_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct rzg2l_pfc_data *data = + (struct rzg2l_pfc_data *)dev_get_driver_data(dev); + u32 port = RZG2L_PINMUX_TO_PORT(offset); + u8 pin = RZG2L_PINMUX_TO_PIN(offset); + + rzg2l_gpio_set_direction(data, port, pin, false); + return 0; +} + +static int rzg2l_gpio_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct rzg2l_pfc_data *data = + (struct rzg2l_pfc_data *)dev_get_driver_data(dev); + u32 port = RZG2L_PINMUX_TO_PORT(offset); + u8 pin = RZG2L_PINMUX_TO_PIN(offset); + + rzg2l_gpio_set(data, port, pin, (bool)value); + rzg2l_gpio_set_direction(data, port, pin, true); + return 0; +} + +static int rzg2l_gpio_request(struct udevice *dev, unsigned int offset, + const char *label) +{ + struct rzg2l_pfc_data *data = + (struct rzg2l_pfc_data *)dev_get_driver_data(dev); + u32 port = RZG2L_PINMUX_TO_PORT(offset); + u8 pin = RZG2L_PINMUX_TO_PIN(offset); + u8 reg8; + + if (!rzg2l_port_validate(data, port, pin)) { + dev_err(dev, "Invalid GPIO %u:%u\n", port, pin); + return -EINVAL; + } + + /* Select GPIO mode in PMC Register */ + reg8 = readb(data->base + PMC(port)); + reg8 &= ~BIT(pin); + writeb(reg8, data->base + PMC(port)); + + return 0; +} + +static int rzg2l_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct rzg2l_pfc_data *data = + (struct rzg2l_pfc_data *)dev_get_driver_data(dev); + u32 port = RZG2L_PINMUX_TO_PORT(offset); + u8 pin = RZG2L_PINMUX_TO_PIN(offset); + u16 pm_state; + u8 pmc_state; + + if (!rzg2l_port_validate(data, port, pin)) { + /* Running `gpio status -a` at the u-boot command line will + * iterate through all GPIO offsets with no understanding of + * which are valid and which are not. So we need to return + * something meaningful even for the invalid GPIOs. + */ + return GPIOF_UNKNOWN; + } + + /* Check if the pin is in GPIO or function mode. */ + pmc_state = readb(data->base + PMC(port)) & BIT(pin); + if (pmc_state) + return GPIOF_FUNC; + + /* Check the pin direction. */ + pm_state = (readw(data->base + PM(port)) >> (pin * 2)) & PM_MASK; + switch (pm_state) { + case PM_INPUT: + return GPIOF_INPUT; + case PM_OUTPUT: + case PM_OUTPUT_IEN: + return GPIOF_OUTPUT; + default: /* PM_HIGH_Z */ + return GPIOF_UNUSED; + } +} + +static const struct dm_gpio_ops rzg2l_gpio_ops = { + .direction_input = rzg2l_gpio_direction_input, + .direction_output = rzg2l_gpio_direction_output, + .get_value = rzg2l_gpio_get_value, + .set_value = rzg2l_gpio_set_value, + .request = rzg2l_gpio_request, + .get_function = rzg2l_gpio_get_function, +}; + +static int rzg2l_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct ofnode_phandle_args args; + int ret; + + uc_priv->bank_name = "rzg2l-pfc-gpio"; + ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges", + NULL, 3, 0, &args); + if (ret < 0) { + dev_err(dev, "Failed to parse gpio-ranges\n"); + return -EINVAL; + } + + uc_priv->gpio_count = args.args[2]; + return rzg2l_pfc_enable(dev); +} + +U_BOOT_DRIVER(rzg2l_pfc_gpio) = { + .name = "rzg2l-pfc-gpio", + .id = UCLASS_GPIO, + .ops = &rzg2l_gpio_ops, + .probe = rzg2l_gpio_probe, +}; + +static const char * const rzg2l_gpio_names[] = { + "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", + "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", + "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", + "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", + "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", + "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", + "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", + "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", + "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", + "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", + "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", + "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", + "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", + "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", + "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", + "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", + "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", + "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", + "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", + "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", + "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", + "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", + "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", + "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", + "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", + "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", + "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", + "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", + "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", + "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", + "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", + "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", + "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", + "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", + "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", + "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", + "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", + "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", + "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", + "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", + "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", + "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", + "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", + "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", + "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", + "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", + "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", + "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", + "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", +}; + +static const u32 r9a07g044_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), +}; + +static const struct { + struct rzg2l_dedicated_configs common[35]; + struct rzg2l_dedicated_configs rzg2l_pins[7]; +} rzg2l_dedicated_pins = { + .common = { + { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, + (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, + { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, + (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, + { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, + (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, + { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, + { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, + { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, + { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, + { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, + { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, + { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, + }, + .rzg2l_pins = { + { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + } +}; + +static void rzg2l_rmw_pin_config(struct rzg2l_pfc_data *data, u32 offset, + u8 pin, u32 mask, u32 val) +{ + void __iomem *addr = data->base + offset; + u32 reg; + + /* handle _L/_H for 32-bit register read/write */ + if (pin >= 4) { + pin -= 4; + addr += 4; + } + + reg = readl(addr) & ~(mask << (pin * 8)); + writel(reg | (val << (pin * 8)), addr); +} + +static int rzg2l_get_pins_count(struct udevice *dev) +{ + struct rzg2l_pfc_data *data = + (struct rzg2l_pfc_data *)dev_get_driver_data(dev); + + return data->num_dedicated_pins + data->num_pins; +} + +static const char *rzg2l_get_pin_name(struct udevice *dev, unsigned int selector) +{ + struct rzg2l_pfc_data *data = + (struct rzg2l_pfc_data *)dev_get_driver_data(dev); + int port; + u8 pin; + + if (selector < data->num_dedicated_pins) { + if (selector >= ARRAY_SIZE(rzg2l_dedicated_pins.common)) { + unsigned int u = selector - ARRAY_SIZE(rzg2l_dedicated_pins.common); + return rzg2l_dedicated_pins.rzg2l_pins[u].name; + } else { + return rzg2l_dedicated_pins.common[selector].name; + } + } + + port = rzg2l_selector_decode(data, selector, &pin); + if (port < 0) + return "(invalid pin)"; + return rzg2l_gpio_names[pin + 8 * port]; +} + +static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, + unsigned int param, unsigned int argument) +{ + struct rzg2l_pfc_data *data = + (struct rzg2l_pfc_data *)dev_get_driver_data(dev); + u32 cfg, port_offset; + u8 pin; + + if (pin_selector >= data->num_dedicated_pins) { + /* The pin selector refers to a multiplexed pin */ + int port = rzg2l_selector_decode(data, pin_selector, &pin); + if (port < 0) { + dev_err(dev, "Invalid pin selector %u:%u\n", port, pin); + return port; + } + + cfg = data->gpio_configs[port]; + port_offset = port + 0x10; + } else { + /* The pin selector refers to a dedicated function pin */ + const struct rzg2l_dedicated_configs *dedicated_config; + + if (pin_selector >= data->num_dedicated_pins) { + dev_err(dev, "Invalid dedicated pin %u\n", pin_selector); + return -EINVAL; + } + + if (pin_selector >= ARRAY_SIZE(rzg2l_dedicated_pins.common)) { + pin_selector -= ARRAY_SIZE(rzg2l_dedicated_pins.common); + dedicated_config = &rzg2l_dedicated_pins.rzg2l_pins[pin_selector]; + } else { + dedicated_config = &rzg2l_dedicated_pins.common[pin_selector]; + } + + port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(dedicated_config->config); + pin = RZG2L_SINGLE_PIN_GET_BIT(dedicated_config->config); + cfg = RZG2L_SINGLE_PIN_GET_CFGS(dedicated_config->config); + } + + switch (param) { + case PIN_CONFIG_INPUT_ENABLE: { + if (!(cfg & PIN_CFG_IEN)) { + dev_err(dev, "pin does not support IEN\n"); + return -EINVAL; + } + + dev_dbg(dev, "port off %u:%u set IEN=%u\n", + port_offset, pin, argument); + rzg2l_rmw_pin_config(data, IEN(port_offset), pin, IEN_MASK, !!argument); + break; + } + + case PIN_CONFIG_POWER_SOURCE: { + void __iomem *addr; + u32 pwr_reg = 0x0; + + /* argument is in mV */ + if (argument != 1800 && argument != 3300) { + dev_err(dev, "Invalid mV %u\n", argument); + return -EINVAL; + } + + if (cfg & PIN_CFG_IO_VMC_SD0) { + dev_dbg(dev, "port off %u:%u set SD_CH 0 PVDD=%u\n", + port_offset, pin, argument); + pwr_reg = SD_CH(0); + } else if (cfg & PIN_CFG_IO_VMC_SD1) { + dev_dbg(dev, "port off %u:%u set SD_CH 1 PVDD=%u\n", + port_offset, pin, argument); + pwr_reg = SD_CH(1); + } else if (cfg & PIN_CFG_IO_VMC_QSPI) { + dev_dbg(dev, "port off %u:%u set QSPI PVDD=%u\n", + port_offset, pin, argument); + pwr_reg = QSPI; + } else { + dev_dbg(dev, "pin power source is not selectable\n"); + return -EINVAL; + } + + addr = data->base + pwr_reg; + writel((argument == 1800) ? PVDD_1800 : PVDD_3300, addr); + break; + } + + default: + dev_err(dev, "Invalid pinconf parameter\n"); + return -EOPNOTSUPP; + } + + return 0; +} + +static int rzg2l_pinmux_property_set(struct udevice *dev, u32 pinmux_group) +{ + struct rzg2l_pfc_data *data = + (struct rzg2l_pfc_data *)dev_get_driver_data(dev); + u32 port, pin, func, pfc_state, reg; + u8 pmc_state; + + func = RZG2L_PINMUX_TO_FUNC(pinmux_group); + if (func > 5) { + dev_err(dev, "Invalid pin function %u\n", func); + return -EINVAL; + } + + port = RZG2L_PINMUX_TO_PORT(pinmux_group); + pin = RZG2L_PINMUX_TO_PIN(pinmux_group); + if (!rzg2l_port_validate(data, port, pin)) { + dev_err(dev, "Invalid pin selector %u:%u\n", port, pin); + return -EINVAL; + } + + /* Check current PMC & PFC to decide if we need to change anything. */ + pmc_state = readb(data->base + PMC(port)) & BIT(pin); + pfc_state = (readl(data->base + PFC(port)) >> (pin * 4)) & PFC_MASK; + if (pmc_state && pfc_state == func) + return 0; + + dev_dbg(dev, "pinmux port %u pin %u func %u\n", port, pin, func); + + /* Set pin to 'Non-use (Hi-Z input protection)' */ + reg = readw(data->base + PM(port)); + reg &= ~(PM_MASK << (pin * 2)); + writew(reg, data->base + PM(port)); + + /* Temporarily switch to GPIO mode with PMC register */ + reg = readb(data->base + PMC(port)); + writeb(reg & ~BIT(pin), data->base + PMC(port)); + + /* Set the PWPR register to allow PFC register to write */ + writel(0x0, data->base + PWPR); /* B0WI=0, PFCWE=0 */ + writel(PWPR_PFCWE, data->base + PWPR); /* B0WI=0, PFCWE=1 */ + + /* Select Pin function mode with PFC register */ + reg = readl(data->base + PFC(port)); + reg &= ~(PFC_MASK << (pin * 4)); + writel(reg | (func << (pin * 4)), data->base + PFC(port)); + + /* Set the PWPR register to be write-protected */ + writel(0x0, data->base + PWPR); /* B0WI=0, PFCWE=0 */ + writel(PWPR_B0WI, data->base + PWPR); /* B0WI=1, PFCWE=0 */ + + /* Switch to Peripheral pin function with PMC register */ + reg = readb(data->base + PMC(port)); + writeb(reg | BIT(pin), data->base + PMC(port)); + + return rzg2l_selector_encode(data, port, pin); +} + +static int rzg2l_get_pin_muxing(struct udevice *dev, unsigned int selector, + char *buf, int size) +{ + struct rzg2l_pfc_data *data = + (struct rzg2l_pfc_data *)dev_get_driver_data(dev); + u32 pmc_state; + int port; + u8 pin; + + if (selector < data->num_dedicated_pins) { + snprintf(buf, size, rzg2l_get_pin_name(dev, selector)); + return 0; + } + + port = rzg2l_selector_decode(data, selector, &pin); + if (port < 0) { + dev_err(dev, "Invalid pin selector %u:%u\n", port, pin); + return port; + } + + pmc_state = readb(data->base + PMC(port)) & BIT(pin); + if (pmc_state) { + u32 pfc_state = (readl(data->base + PFC(port)) >> (pin * 4)) & PFC_MASK; + snprintf(buf, size, "Function %d", pfc_state); + return 0; + } + + snprintf(buf, size, "GPIO"); + return 0; +} + +static const struct pinconf_param rzg2l_pinconf_params[] = { + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 /* mV */ }, +}; + +static const struct pinctrl_ops rzg2l_pinctrl_ops = { + .get_pins_count = rzg2l_get_pins_count, + .get_pin_name = rzg2l_get_pin_name, + + .pinconf_num_params = ARRAY_SIZE(rzg2l_pinconf_params), + .pinconf_params = rzg2l_pinconf_params, + .pinconf_set = rzg2l_pinconf_set, + + .pinmux_property_set = rzg2l_pinmux_property_set, + .set_state = pinctrl_generic_set_state, + .get_pin_muxing = rzg2l_get_pin_muxing, +}; + +static int rzg2l_pinctrl_probe(struct udevice *dev) +{ + return rzg2l_pfc_enable(dev); +} + +U_BOOT_DRIVER(rzg2l_pfc_pinctrl) = { + .name = "rzg2l-pfc-pinctrl", + .id = UCLASS_PINCTRL, + .ops = &rzg2l_pinctrl_ops, + .probe = rzg2l_pinctrl_probe, +}; + +static const struct rzg2l_pfc_driver_data r9a07g044_driver_data = { + .num_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), + .num_ports = ARRAY_SIZE(r9a07g044_gpio_configs), + .gpio_configs = r9a07g044_gpio_configs, +}; + +static const struct udevice_id rzg2l_pfc_ids[] = { + { .compatible = "renesas,r9a07g044-pinctrl", .data = (ulong)&r9a07g044_driver_data }, + { /* sentinel */ } +}; + +static int rzg2l_pfc_bind(struct udevice *parent) +{ + struct rzg2l_pfc_driver_data *driver_data; + struct udevice *gpio_dev, *pinctrl_dev; + struct rzg2l_pfc_data *data; + struct driver *drv; + unsigned int i; + int ret; + + driver_data = + (struct rzg2l_pfc_driver_data *)dev_get_driver_data(parent); + if (!driver_data) + return -EINVAL; + data = devm_kmalloc(parent, sizeof(*data), 0); + if (!data) + return -ENOMEM; + + data->base = dev_read_addr_ptr(parent); + if (!data->base) + return -EINVAL; + data->num_dedicated_pins = driver_data->num_dedicated_pins; + data->num_ports = driver_data->num_ports; + data->gpio_configs = driver_data->gpio_configs; + data->pfc_enabled = false; + + data->num_pins = 0; + for (i = 0; i < data->num_ports; i++) + data->num_pins += RZG2L_GPIO_PORT_GET_PINCNT(data->gpio_configs[i]); + dev_dbg(parent, "%u dedicated pins, %u muxed ports, %u muxed pins\n", + data->num_dedicated_pins, data->num_ports, data->num_pins); + + drv = lists_driver_lookup_name("rzg2l-pfc-gpio"); + if (!drv) + return -ENOENT; + + ret = device_bind_with_driver_data(parent, drv, parent->name, + (ulong)data, dev_ofnode(parent), + &gpio_dev); + if (ret) + return ret; + + drv = lists_driver_lookup_name("rzg2l-pfc-pinctrl"); + if (!drv) { + device_unbind(gpio_dev); + return -ENOENT; + } + + ret = device_bind_with_driver_data(parent, drv, parent->name, + (ulong)data, dev_ofnode(parent), + &pinctrl_dev); + if (ret) + device_unbind(gpio_dev); + + return ret; +} + +U_BOOT_DRIVER(rzg2l_pfc) = { + .name = "rzg2l-pfc", + .id = UCLASS_NOP, + .of_match = rzg2l_pfc_ids, + .bind = rzg2l_pfc_bind, +};

On the Renesas RZ/G2L SoC family, we must ensure that the required clock signals are enabled and the reset signal is de-asserted before we try to communicate with the SDHI module.

Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- drivers/mmc/renesas-sdhi.c | 61 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 8e716f74491f..170c5dcc2ebe 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -20,6 +20,7 @@ #include <linux/io.h> #include <linux/sizes.h> #include <power/regulator.h> +#include <reset.h> #include <asm/unaligned.h> #include "tmio-common.h"

@@ -964,6 +965,8 @@ static int renesas_sdhi_probe(struct udevice *dev) u32 quirks = dev_get_driver_data(dev); struct fdt_resource reg_res; DECLARE_GLOBAL_DATA_PTR; + struct clk imclk2, aclk; + struct reset_ctl rst; int ret;

priv->clk_get_rate = renesas_sdhi_clk_get_rate; @@ -1012,6 +1015,49 @@ static int renesas_sdhi_probe(struct udevice *dev) goto err_clkh; }

+ if (IS_ENABLED(CONFIG_RZG2L)) { + /* + * On members of the RZ/G2L SoC family, we need to enable + * additional chip detect and bus clocks, then release the SDHI + * module from reset. + */ + ret = clk_get_by_name(dev, "cd", &imclk2); + if (ret < 0) { + dev_err(dev, "failed to get imclk2 (chip detect clk)\n"); + goto err_get_imclk2; + } + + ret = clk_get_by_name(dev, "aclk", &aclk); + if (ret < 0) { + dev_err(dev, "failed to get aclk\n"); + goto err_get_aclk; + } + + ret = clk_enable(&imclk2); + if (ret < 0) { + dev_err(dev, "failed to enable imclk2 (chip detect clk)\n"); + goto err_imclk2; + } + + ret = clk_enable(&aclk); + if (ret < 0) { + dev_err(dev, "failed to enable aclk\n"); + goto err_aclk; + } + + ret = reset_get_by_index(dev, 0, &rst); + if (ret < 0) { + dev_err(dev, "failed to get reset line\n"); + goto err_reset; + } + + ret = reset_deassert(&rst); + if (ret < 0) { + dev_err(dev, "failed to de-assert reset line\n"); + goto err_reset; + } + } + priv->quirks = quirks; ret = tmio_sd_probe(dev, quirks); if (ret) @@ -1028,6 +1074,21 @@ static int renesas_sdhi_probe(struct udevice *dev) return 0;

err_tmio_probe: + if (IS_ENABLED(CONFIG_RZG2L)) + reset_assert(&rst); +err_reset: + if (IS_ENABLED(CONFIG_RZG2L)) + clk_disable(&aclk); +err_aclk: + if (IS_ENABLED(CONFIG_RZG2L)) + clk_disable(&imclk2); +err_imclk2: + if (IS_ENABLED(CONFIG_RZG2L)) + clk_free(&aclk); +err_get_aclk: + if (IS_ENABLED(CONFIG_RZG2L)) + clk_free(&imclk2); +err_get_imclk2: clk_disable(&priv->clk); err_clkh: clk_free(&priv->clkh);

We don't want to rely on source files including <asm/types.h> before <asm/arch/rmobile.h>.

Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- arch/arm/mach-rmobile/include/mach/rmobile.h | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index d326d5545a6f..053ad08add00 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -45,6 +45,8 @@ #define RMOBILE_CPU_TYPE_R8A779G0 0x5C

#ifndef __ASSEMBLY__ +#include <asm/types.h> + const u8 *rzg_get_cpu_name(void); u32 rmobile_get_cpu_type(void); u32 rmobile_get_cpu_rev_integer(void);

The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes a devicetree blob to the bootloader as an argument in the same was previous R-Car gen3/gen4 SoCs. This blob contains a compatible string which can be used to identify the particular SoC we are running on.

Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- arch/arm/mach-rmobile/Makefile | 5 +- arch/arm/mach-rmobile/cpu_info-rzg2l.c | 63 ++++++++++++++++++++ arch/arm/mach-rmobile/include/mach/rmobile.h | 1 + 3 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rmobile/cpu_info-rzg2l.c

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 4eddba53ed2a..45d6a0e2a28a 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -10,8 +10,11 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o -obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o +obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o memmap-gen3.o +obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o +obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o +obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o

ifneq ($(CONFIG_R8A779A0),) obj-$(CONFIG_ARMV8_PSCI) += psci-r8a779a0.o diff --git a/arch/arm/mach-rmobile/cpu_info-rzg2l.c b/arch/arm/mach-rmobile/cpu_info-rzg2l.c new file mode 100644 index 000000000000..de4892ee901e --- /dev/null +++ b/arch/arm/mach-rmobile/cpu_info-rzg2l.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021,2023 Renesas Electronics Corporation + * + */ + +#include <common.h> +#include <asm/io.h> +#include <linux/libfdt.h> + +#define SYSC_LSI_DEVID 0x11020A04 + +/* If the firmware passed a device tree, use it for soc identification. */ +extern u64 rcar_atf_boot_args[]; + +/* CPU information table */ +struct tfa_info { + const char *soc_name; + const char *cpu_name; + u32 cpu_type; +}; + +static const struct tfa_info tfa_info[] = { + { "renesas,r9a07g044l2", "R9A07G044L", RMOBILE_CPU_TYPE_R9A07G044L }, +}; + +static const struct tfa_info invalid_tfa_info = { NULL, "(invalid)", 0 }; + +static const struct tfa_info *get_tfa_info(void) +{ + void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); + + if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) { + unsigned int i; + for (i = 0; i < ARRAY_SIZE(tfa_info); i++) { + if (!fdt_node_check_compatible(atf_fdt_blob, 0, + tfa_info[i].soc_name)) + return &tfa_info[i]; + } + } + + return &invalid_tfa_info; +} + +const u8 *rzg_get_cpu_name(void) +{ + return get_tfa_info()->cpu_name; +} + +u32 rmobile_get_cpu_type(void) +{ + return get_tfa_info()->cpu_type; +} + +u32 rmobile_get_cpu_rev_integer(void) +{ + return (readl(SYSC_LSI_DEVID) >> 28) + 1; +} + +u32 rmobile_get_cpu_rev_fraction(void) +{ + return 0; +} diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index 053ad08add00..88b8b78671b2 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -43,6 +43,7 @@ #define RMOBILE_CPU_TYPE_R8A779A0 0x59 #define RMOBILE_CPU_TYPE_R8A779F0 0x5A #define RMOBILE_CPU_TYPE_R8A779G0 0x5C +#define RMOBILE_CPU_TYPE_R9A07G044L 0x9A070440

#ifndef __ASSEMBLY__ #include <asm/types.h>