[U-Boot] [PATCH v4 04/28] armv8/ls2085a: Fix generic timer clock source
The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot.
Signed-off-by: York Sun yorksun@freescale.com CC: Mark Rutland mark.rutland@arm.com
---
Changes in v4: Remove temporary variable cntfrq.
Changes in v3: Move secondary core fix to mp.c. Replace hard-coded value with COUNTER_FREQUENCY.
Changes in v2: Fix CNTFRQ for secondary cores when COUNTER_FREQUENCY_REAL is defined.
README | 8 ++++++++ arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 24 ++++++++++++++++++++++++ arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 6 ++++++ arch/arm/cpu/armv8/fsl-lsch3/mp.c | 7 +++++++ arch/arm/cpu/armv8/fsl-lsch3/mp.h | 1 + board/freescale/ls2085a/ls2085a.c | 18 ------------------ include/configs/ls2085a_common.h | 6 +++++- 7 files changed, 51 insertions(+), 19 deletions(-)
diff --git a/README b/README index e710226..f063a74 100644 --- a/README +++ b/README @@ -690,6 +690,14 @@ The following options need to be configured: exists, unlike the similar options in the Linux kernel. Do not set these options unless they apply!
+ COUNTER_FREQUENCY + Generic timer clock source frequency. + + COUNTER_FREQUENCY_REAL + Generic timer clock source frequency if the real clock is + different from COUNTER_FREQUENCY, and can only be determined + at run time. + NOTE: The following can be machine specific errata. These do have ability to provide rudimentary version and machine specific checks, but expect no product checks. diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 94fd147..e985181 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -395,3 +395,27 @@ int arch_early_init_r(void)
return 0; } + +int timer_init(void) +{ + u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; + u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; +#ifdef COUNTER_FREQUENCY_REAL + unsigned long cntfrq = COUNTER_FREQUENCY_REAL; + + /* Update with accurate clock frequency */ + asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); +#endif + + /* Enable timebase for all clusters. + * It is safe to do so even some clusters are not enabled. + */ + out_le32(cltbenr, 0xf); + + /* Enable clock for timer + * This is a global setting. + */ + out_le32(cntcr, 0x1); + + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S index 886576e..53bdb44 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -224,6 +224,9 @@ ENTRY(secondary_boot_func) /* physical address of this cpus spin table element */ add x11, x1, x0
+ ldr x0, =__real_cntfrq + ldr x0, [x0] + msr cntfrq_el0, x0 /* set with real frequency */ str x9, [x11, #16] /* LPID */ mov x4, #1 str x4, [x11, #8] /* STATUS */ @@ -275,6 +278,9 @@ ENDPROC(secondary_switch_to_el1)
/* 64 bit alignment for elements accessed as data */ .align 4 + .global __real_cntfrq +__real_cntfrq: + .quad COUNTER_FREQUENCY .globl __secondary_boot_code_size .type __secondary_boot_code_size, %object /* Secondary Boot Code ends here */ diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-lsch3/mp.c index ce9c0c1..da7853a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c @@ -31,6 +31,13 @@ int fsl_lsch3_wake_seconday_cores(void) int i, timeout = 10; u64 *table = get_spin_tbl_addr();
+#ifdef COUNTER_FREQUENCY_REAL + /* update for secondary cores */ + __real_cntfrq = COUNTER_FREQUENCY_REAL; + flush_dcache_range((unsigned long)&__real_cntfrq, + (unsigned long)&__real_cntfrq + 8); +#endif + cores = cpu_mask(); /* Clear spin table so that secondary processors * observe the correct value after waking up from wfe. diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h index 66144d6..c985d6a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h @@ -26,6 +26,7 @@ #define id_to_core(x) ((x & 3) | (x >> 6)) #ifndef __ASSEMBLY__ extern u64 __spin_table[]; +extern u64 __real_cntfrq; extern u64 *secondary_boot_code; extern size_t __secondary_boot_code_size; int fsl_lsch3_wake_seconday_cores(void); diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c index e78c63a..bd016e9 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2085a/ls2085a.c @@ -55,24 +55,6 @@ int dram_init(void) return 0; }
-int timer_init(void) -{ - u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; - u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; - - /* Enable timebase for all clusters. - * It is safe to do so even some clusters are not enabled. - */ - out_le32(cltbenr, 0xf); - - /* Enable clock for timer - * This is a global setting. - */ - out_le32(cntcr, 0x1); - - return 0; -} - /* * Board specific reset that is system reset. */ diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 5721b18..f6b3ed0 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -72,7 +72,11 @@ #define CONFIG_DP_DDR_NUM_CTRLS 1
/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 12000000 /* 12MHz */ +/* + * This is not an accurate number. It is used in start.S. The frequency + * will be udpated later when get_bus_freq(0) is available. + */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
From: Scott Wood scottwood@freescale.com
This adds NAND boot support for LS2085AQDS, using SPL framework.
To form a NAND image, append u-boot-with-spl.bin after a proper nand boot RCW and flash to the beginning of NAND.
Signed-off-by: Scott Wood scottwood@freescale.com Signed-off-by: York Sun yorksun@freescale.com
---
Changes in v4: Update MAINTAINERS file
Changes in v3: None Changes in v2: None
arch/arm/Kconfig | 1 + arch/arm/cpu/armv8/fsl-lsch3/soc.c | 48 ++++++++++++++++ arch/arm/cpu/armv8/u-boot-spl.lds | 77 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 9 +++ arch/arm/lib/crt0_64.S | 7 +++ board/freescale/ls2085aqds/MAINTAINERS | 1 + board/freescale/ls2085aqds/ddr.c | 4 ++ common/spl/spl.c | 2 +- common/spl/spl_nand.c | 2 +- configs/ls2085aqds_nand_defconfig | 4 ++ drivers/misc/fsl_ifc.c | 12 ++++ drivers/mtd/nand/fsl_ifc_spl.c | 2 +- include/configs/ls2085a_common.h | 29 ++++++++++ include/configs/ls2085aqds.h | 50 +++++++++++++++-- 14 files changed, 240 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/armv8/u-boot-spl.lds create mode 100644 configs/ls2085aqds_nand_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7478eb4..46a48a0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -652,6 +652,7 @@ config TARGET_LS2085AQDS bool "Support ls2085aqds" select ARM64 select ARMV8_MULTIENTRY + select SUPPORT_SPL help Support for Freescale LS2085AQDS platform The LS2085A Development System (QDS) is a high-performance diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c index 17700ef..ca00108 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c @@ -6,8 +6,13 @@
#include <common.h> #include <fsl_ifc.h> +#include <nand.h> +#include <spl.h> #include <asm/arch-fsl-lsch3/soc.h> #include <asm/io.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR;
static void erratum_a008751(void) { @@ -18,8 +23,51 @@ static void erratum_a008751(void) #endif }
+static void erratum_rcw_src(void) +{ +#if defined(CONFIG_SPL) + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; + u32 val; + + val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); + val &= ~DCFG_PORSR1_RCW_SRC; + val |= DCFG_PORSR1_RCW_SRC_NOR; + out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); +#endif +} + void fsl_lsch3_early_init_f(void) { erratum_a008751(); + erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ } + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + board_early_init_f(); + timer_init(); + env_init(); + gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); + + serial_init(); + console_init_f(); + dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NAND; +} +#endif diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds new file mode 100644 index 0000000..4df339c --- /dev/null +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2013 + * David Feng fenghua@phytium.com.cn + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V aneesh@ti.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_start) +SECTIONS +{ + .text : { + . = ALIGN(8); + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } >.sram + + .rodata : { + . = ALIGN(8); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } >.sram + + .data : { + . = ALIGN(8); + *(.data*) + } >.sram + + .u_boot_list : { + . = ALIGN(8); + KEEP(*(SORT(.u_boot_list*))); + } >.sram + + .image_copy_end : { + . = ALIGN(8); + *(.__image_copy_end) + } >.sram + + .end : { + . = ALIGN(8); + *(.__end) + } >.sram + + .bss_start : { + . = ALIGN(8); + KEEP(*(.__bss_start)); + } >.sdram + + .bss : { + *(.bss*) + . = ALIGN(8); + } >.sdram + + .bss_end : { + KEEP(*(.__bss_end)); + } >.sdram + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 403b2ef..77c20ab 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -130,6 +130,15 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
+/* Device Configuration */ +#define DCFG_BASE 0x01e00000 +#define DCFG_PORSR1 0x000 +#define DCFG_PORSR1_RCW_SRC 0xff800000 +#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 + +#define DCFG_DCSR_BASE 0X700100000ULL +#define DCFG_DCSR_PORCR1 0x000 + /* Supplemental Configuration */ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 7756396..bf4ca99 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -61,13 +61,18 @@ ENTRY(_main) /* * Set up initial C runtime environment and call board_init_f(0). */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) + ldr x0, =(CONFIG_SPL_STACK) +#else ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) +#endif sub x0, x0, #GD_SIZE /* allocate one GD above SP */ bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ mov x18, sp /* GD is above SP */ mov x0, #0 bl board_init_f
+#if !defined(CONFIG_SPL_BUILD) /* * Set up intermediate environment (new sp and gd) and call * relocate_code(addr_moni). Trick here is that we'll return @@ -110,4 +115,6 @@ clear_loop:
/* NOTREACHED - board_init_r() does not return */
+#endif /* !CONFIG_SPL_BUILD */ + ENDPROC(_main) diff --git a/board/freescale/ls2085aqds/MAINTAINERS b/board/freescale/ls2085aqds/MAINTAINERS index 74b3721..fbed672 100644 --- a/board/freescale/ls2085aqds/MAINTAINERS +++ b/board/freescale/ls2085aqds/MAINTAINERS @@ -5,3 +5,4 @@ F: board/freescale/ls2085aqds/ F: board/freescale/ls2085a/ls2085aqds.c F: include/configs/ls2085aqds.h F: configs/ls2085aqds_defconfig +F: configs/ls2085aqds_nand_defconfig diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2085aqds/ddr.c index 6cd5e8b..8d71ae1 100644 --- a/board/freescale/ls2085aqds/ddr.c +++ b/board/freescale/ls2085aqds/ddr.c @@ -147,9 +147,13 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size;
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + return fsl_ddr_sdram_size(); +#else puts("Initializing DDR....using SPD\n");
dram_size = fsl_ddr_sdram(); +#endif
return dram_size; } diff --git a/common/spl/spl.c b/common/spl/spl.c index cd75bbc..6d5cb0e 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -113,7 +113,7 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) typedef void __noreturn (*image_entry_noargs_t)(void);
image_entry_noargs_t image_entry = - (image_entry_noargs_t) spl_image->entry_point; + (image_entry_noargs_t)(unsigned long)spl_image->entry_point;
debug("image entry point: 0x%X\n", spl_image->entry_point); image_entry(); diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index b7801cb..b8c369d 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -91,7 +91,7 @@ void spl_nand_load_image(void) sizeof(*header), (void *)header); spl_parse_image_header(header); nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - spl_image.size, (void *)spl_image.load_addr); + spl_image.size, (void *)(unsigned long)spl_image.load_addr); nand_deselect(); } #endif diff --git a/configs/ls2085aqds_nand_defconfig b/configs/ls2085aqds_nand_defconfig new file mode 100644 index 0000000..446206a --- /dev/null +++ b/configs/ls2085aqds_nand_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS2085AQDS=y diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index 45d299c..a33efdb 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -168,13 +168,25 @@ void init_final_memctl_regs(void) #ifdef CONFIG_SYS_CSPR0_FINAL set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL); #endif +#ifdef CONFIG_SYS_AMASK0_FINAL + set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); +#endif #ifdef CONFIG_SYS_CSPR1_FINAL set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL); #endif #ifdef CONFIG_SYS_AMASK1_FINAL set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL); #endif +#ifdef CONFIG_SYS_CSPR2_FINAL + set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL); +#endif +#ifdef CONFIG_SYS_AMASK2_FINAL + set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); +#endif #ifdef CONFIG_SYS_CSPR3_FINAL set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL); #endif +#ifdef CONFIG_SYS_AMASK3_FINAL + set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); +#endif } diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index 2fb9fb1..fccbfb5 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -66,7 +66,7 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size) { struct fsl_ifc_runtime *ifc = runtime_regs_address(); u32 status; - u32 eccstat[4]; + u32 eccstat[8]; int bufperpage = page_size / 512; int bufnum_end, i;
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 44c6845..9bc3869 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -28,7 +28,11 @@ #define CONFIG_ARCH_MISC_INIT
/* Link Definitions */ +#ifdef CONFIG_SPL +#define CONFIG_SYS_TEXT_BASE 0x80400000 +#else #define CONFIG_SYS_TEXT_BASE 0x30100000 +#endif
#ifdef CONFIG_EMU #define CONFIG_SYS_NO_FLASH @@ -47,7 +51,9 @@ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#ifndef CONFIG_SPL #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#endif #ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ #define CONFIG_SYS_DDR_RAW_TIMING @@ -272,4 +278,27 @@ unsigned long get_dram_size_to_hide(void);
#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MAX_SIZE 0x16000 +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_TEXT_BASE 0x1800a000 + +#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + #endif /* __LS2_COMMON_H */ diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h index 5ac5b63..0203276 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2085aqds.h @@ -147,10 +147,12 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RCW_SRC_NAND 0x107 #define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0) @@ -176,6 +178,43 @@ unsigned long get_board_ddr_clk(void); FTIM2_GPCM_TWP(0x3E)) #define CONFIG_SYS_CS3_FTIM3 0x0
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY +#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SPL_PAD_TO 0x1ff40 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 * 1024) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) +#else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR @@ -204,6 +243,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x2000 +#endif + /* Debug Server firmware */ #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL @@ -249,11 +294,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_FSL_MEMAC #define CONFIG_PCI /* Enable PCIE */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote:
From: Scott Wood scottwood@freescale.com
This adds NAND boot support for LS2085AQDS, using SPL framework.
To form a NAND image, append u-boot-with-spl.bin after a proper nand boot RCW and flash to the beginning of NAND.
Do we want to do it this way, or should we keep the RCW in a separate block?
What constitutes a "proper nand boot RCW" (those were not my words)? There are details in this patch regarding offsets that need to match details in the PBI (which is more than just RCW).
It would also be nice to sort out loading the environment during SPL.
-Scott
On 03/20/2015 02:15 PM, Scott Wood wrote:
On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote:
From: Scott Wood scottwood@freescale.com
This adds NAND boot support for LS2085AQDS, using SPL framework.
To form a NAND image, append u-boot-with-spl.bin after a proper nand boot RCW and flash to the beginning of NAND.
Do we want to do it this way, or should we keep the RCW in a separate block?
I would like to see RCW in a separated block.
What constitutes a "proper nand boot RCW" (those were not my words)? There are details in this patch regarding offsets that need to match details in the PBI (which is more than just RCW).
It is not your original words. Yours was "To form a NAND image, append u-boot-with-spl.bin after PBL_0x3_0x07_1333_nand.bin and flash to the beginning of NAND.". I try to make the message generic. A proper nand boot RCW means the RCW should contains PBI commands to set bootloc and block copy the image. Since RCW is not in the scope of u-boot, I cannot refer to any specific file.
Do you want to include an RCW file into u-boot, like those for powerpc boards?
It would also be nice to sort out loading the environment during SPL.
That can be an additional patch when you have it.
York
On Fri, 2015-03-20 at 14:23 -0700, York Sun wrote:
On 03/20/2015 02:15 PM, Scott Wood wrote:
On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote:
From: Scott Wood scottwood@freescale.com
This adds NAND boot support for LS2085AQDS, using SPL framework.
To form a NAND image, append u-boot-with-spl.bin after a proper nand boot RCW and flash to the beginning of NAND.
Do we want to do it this way, or should we keep the RCW in a separate block?
I would like to see RCW in a separated block.
OK. In that case the offsets in this patch will need to change.
What constitutes a "proper nand boot RCW" (those were not my words)? There are details in this patch regarding offsets that need to match details in the PBI (which is more than just RCW).
It is not your original words. Yours was "To form a NAND image, append u-boot-with-spl.bin after PBL_0x3_0x07_1333_nand.bin and flash to the beginning of NAND.". I try to make the message generic. A proper nand boot RCW means the RCW should contains PBI commands to set bootloc and block copy the image. Since RCW is not in the scope of u-boot, I cannot refer to any specific file.
Yes, I know you can't refer to the file, but it needs to be made clear what the expectations of that PBI file are.
Do you want to include an RCW file into u-boot, like those for powerpc boards?
Not really. I'd rather have rcw.git published for all use cases (like http://git.freescale.com/git/cgit.cgi/layerscape/ls1021a/rcw.git/ but updated for ls2085a and without the repository being chip-specific (at least in name)).
On PPC we had to have U-Boot do it because the U-Boot image itself had to be encoded in the PBI. That thankfully isn't the case here.
-Scott
On 03/20/2015 02:33 PM, Scott Wood wrote:
On Fri, 2015-03-20 at 14:23 -0700, York Sun wrote:
On 03/20/2015 02:15 PM, Scott Wood wrote:
On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote:
From: Scott Wood scottwood@freescale.com
This adds NAND boot support for LS2085AQDS, using SPL framework.
To form a NAND image, append u-boot-with-spl.bin after a proper nand boot RCW and flash to the beginning of NAND.
Do we want to do it this way, or should we keep the RCW in a separate block?
I would like to see RCW in a separated block.
OK. In that case the offsets in this patch will need to change.
What constitutes a "proper nand boot RCW" (those were not my words)? There are details in this patch regarding offsets that need to match details in the PBI (which is more than just RCW).
It is not your original words. Yours was "To form a NAND image, append u-boot-with-spl.bin after PBL_0x3_0x07_1333_nand.bin and flash to the beginning of NAND.". I try to make the message generic. A proper nand boot RCW means the RCW should contains PBI commands to set bootloc and block copy the image. Since RCW is not in the scope of u-boot, I cannot refer to any specific file.
Yes, I know you can't refer to the file, but it needs to be made clear what the expectations of that PBI file are.
I think a proper solution would be to put detail instruction into board README file by adding
To form the NAND image, append u-boot-with-spl.bin after RCW image. The RCW image should have these PBI commands
CCSR 4-byte write to 0x00e00404, data=0x00000000 CCSR 4-byte write to 0x00e00400, data=0x1800a000 Block Copy: SRC=0x0104, SRC_ADDR=0x000000c0, DEST_ADDR=0x1800a000, BLOCK_SIZE=0x00014000
We need to revise the SRS_ADDR if moving u-boot to a separated block. Please advise what address is appropriate.
Please also advise the BLOCK_SIZE. Does it need to be fixed, or min(0x14000, sizeof(u-boot-spl.bin))?
Do you want to include an RCW file into u-boot, like those for powerpc boards?
Not really. I'd rather have rcw.git published for all use cases (like http://git.freescale.com/git/cgit.cgi/layerscape/ls1021a/rcw.git/ but updated for ls2085a and without the repository being chip-specific (at least in name)).
On PPC we had to have U-Boot do it because the U-Boot image itself had to be encoded in the PBI. That thankfully isn't the case here.
This is good.
York
On Fri, 2015-03-20 at 14:44 -0700, York Sun wrote:
On 03/20/2015 02:33 PM, Scott Wood wrote:
On Fri, 2015-03-20 at 14:23 -0700, York Sun wrote:
On 03/20/2015 02:15 PM, Scott Wood wrote:
On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote:
From: Scott Wood scottwood@freescale.com
This adds NAND boot support for LS2085AQDS, using SPL framework.
To form a NAND image, append u-boot-with-spl.bin after a proper nand boot RCW and flash to the beginning of NAND.
Do we want to do it this way, or should we keep the RCW in a separate block?
I would like to see RCW in a separated block.
OK. In that case the offsets in this patch will need to change.
What constitutes a "proper nand boot RCW" (those were not my words)? There are details in this patch regarding offsets that need to match details in the PBI (which is more than just RCW).
It is not your original words. Yours was "To form a NAND image, append u-boot-with-spl.bin after PBL_0x3_0x07_1333_nand.bin and flash to the beginning of NAND.". I try to make the message generic. A proper nand boot RCW means the RCW should contains PBI commands to set bootloc and block copy the image. Since RCW is not in the scope of u-boot, I cannot refer to any specific file.
Yes, I know you can't refer to the file, but it needs to be made clear what the expectations of that PBI file are.
I think a proper solution would be to put detail instruction into board README file by adding
To form the NAND image, append u-boot-with-spl.bin after RCW image. The RCW image should have these PBI commands
CCSR 4-byte write to 0x00e00404, data=0x00000000 CCSR 4-byte write to 0x00e00400, data=0x1800a000 Block Copy: SRC=0x0104, SRC_ADDR=0x000000c0, DEST_ADDR=0x1800a000, BLOCK_SIZE=0x00014000
We need to revise the SRS_ADDR if moving u-boot to a separated block. Please advise what address is appropriate.
It should be equal to the NAND block size (not to be confused with PBI block copy size).
Please also advise the BLOCK_SIZE. Does it need to be fixed, or min(0x14000, sizeof(u-boot-spl.bin))?
It should be fixed because we don't want it to have to be updated every time the SPL build changes.
-Scott
On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote:
[snip]
It would also be nice to sort out loading the environment during SPL.
*ears perk up*. Please elaborate :) We have SPL environment support, we have SPL NAND Environment support today. It doesn't get passed along to the running U-Boot and it's used for some limited cases (network and redundancy). I'd like to hear about more and better ways of using it.
On Fri, 2015-03-20 at 17:37 -0400, Tom Rini wrote:
On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote:
[snip]
It would also be nice to sort out loading the environment during SPL.
*ears perk up*. Please elaborate :) We have SPL environment support, we have SPL NAND Environment support today. It doesn't get passed along to the running U-Boot and it's used for some limited cases (network and redundancy). I'd like to hear about more and better ways of using it.
In common/spl/spl_nand.c, why does it only load the environment when CONFIG_NAND_ENV_DST is defined, yet it never uses the value of CONFIG_NAND_ENV_DST? I also don't see any boards definind CONFIG_NAND_ENV_DST (apparently the only one that ever used it was smdk6400 which has been removed).
Is there some other way that the environment is supposed to be getting loaded from NAND (rather than using the default environment) during SPL?
-Scott
On Fri, Mar 20, 2015 at 04:44:19PM -0500, Scott Wood wrote:
On Fri, 2015-03-20 at 17:37 -0400, Tom Rini wrote:
On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote:
[snip]
It would also be nice to sort out loading the environment during SPL.
*ears perk up*. Please elaborate :) We have SPL environment support, we have SPL NAND Environment support today. It doesn't get passed along to the running U-Boot and it's used for some limited cases (network and redundancy). I'd like to hear about more and better ways of using it.
In common/spl/spl_nand.c, why does it only load the environment when CONFIG_NAND_ENV_DST is defined, yet it never uses the value of CONFIG_NAND_ENV_DST? I also don't see any boards definind CONFIG_NAND_ENV_DST (apparently the only one that ever used it was smdk6400 which has been removed).
Is there some other way that the environment is supposed to be getting loaded from NAND (rather than using the default environment) during SPL?
Yeah, it's loaded via env_init() being called (see spl_net.c or board/ti/).
On Fri, 2015-03-20 at 20:18 -0400, Tom Rini wrote:
On Fri, Mar 20, 2015 at 04:44:19PM -0500, Scott Wood wrote:
On Fri, 2015-03-20 at 17:37 -0400, Tom Rini wrote:
On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote:
[snip]
It would also be nice to sort out loading the environment during SPL.
*ears perk up*. Please elaborate :) We have SPL environment support, we have SPL NAND Environment support today. It doesn't get passed along to the running U-Boot and it's used for some limited cases (network and redundancy). I'd like to hear about more and better ways of using it.
In common/spl/spl_nand.c, why does it only load the environment when CONFIG_NAND_ENV_DST is defined, yet it never uses the value of CONFIG_NAND_ENV_DST? I also don't see any boards definind CONFIG_NAND_ENV_DST (apparently the only one that ever used it was smdk6400 which has been removed).
Is there some other way that the environment is supposed to be getting loaded from NAND (rather than using the default environment) during SPL?
Yeah, it's loaded via env_init() being called (see spl_net.c or board/ti/).
The NAND version of env_init() does not access NAND. It loads from CONFIG_NAND_ENV_DST (but again, no board sets that) or from an embedded environment.
-Scott
On Fri, Mar 20, 2015 at 07:28:16PM -0500, Scott Wood wrote:
On Fri, 2015-03-20 at 20:18 -0400, Tom Rini wrote:
On Fri, Mar 20, 2015 at 04:44:19PM -0500, Scott Wood wrote:
On Fri, 2015-03-20 at 17:37 -0400, Tom Rini wrote:
On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote:
[snip]
It would also be nice to sort out loading the environment during SPL.
*ears perk up*. Please elaborate :) We have SPL environment support, we have SPL NAND Environment support today. It doesn't get passed along to the running U-Boot and it's used for some limited cases (network and redundancy). I'd like to hear about more and better ways of using it.
In common/spl/spl_nand.c, why does it only load the environment when CONFIG_NAND_ENV_DST is defined, yet it never uses the value of CONFIG_NAND_ENV_DST? I also don't see any boards definind CONFIG_NAND_ENV_DST (apparently the only one that ever used it was smdk6400 which has been removed).
Is there some other way that the environment is supposed to be getting loaded from NAND (rather than using the default environment) during SPL?
Yeah, it's loaded via env_init() being called (see spl_net.c or board/ti/).
The NAND version of env_init() does not access NAND. It loads from CONFIG_NAND_ENV_DST (but again, no board sets that) or from an embedded environment.
OK, you're right. I had only used it really on the network side for NAND in ENV and for that default is what we wanted anyhow so I didn't notice.
From: Scott Wood scottwood@freescale.com
Enable NAND boot support using SPL framework. To boot from NAND, either use DIP switches on board, or "qixis_reset nand" command.
Signed-off-by: Scott Wood scottwood@freescale.com Singed-off-by: York Sun yorksun@freescale.com
---
Changes in v4: Update MAINTAINERS file
Changes in v3: None Changes in v2: None
arch/arm/Kconfig | 1 + board/freescale/ls2085ardb/MAINTAINERS | 1 + board/freescale/ls2085ardb/ddr.c | 4 ++++ configs/ls2085ardb_nand_defconfig | 4 ++++ include/configs/ls2085ardb.h | 40 ++++++++++++++++++++++++++++---- 5 files changed, 45 insertions(+), 5 deletions(-) create mode 100644 configs/ls2085ardb_nand_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 46a48a0..7cbbf37 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -663,6 +663,7 @@ config TARGET_LS2085ARDB bool "Support ls2085ardb" select ARM64 select ARMV8_MULTIENTRY + select SUPPORT_SPL help Support for Freescale LS2085ARDB platform. The LS2080A Reference design board (RDB) is a high-performance diff --git a/board/freescale/ls2085ardb/MAINTAINERS b/board/freescale/ls2085ardb/MAINTAINERS index 436039f..d5cce40 100644 --- a/board/freescale/ls2085ardb/MAINTAINERS +++ b/board/freescale/ls2085ardb/MAINTAINERS @@ -5,3 +5,4 @@ F: board/freescale/ls2085ardb/ F: board/freescale/ls2085a/ls2085ardb.c F: include/configs/ls2085ardb.h F: configs/ls2085ardb_defconfig +F: configs/ls2085ardb_nand_defconfig diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2085ardb/ddr.c index 6cd5e8b..8d71ae1 100644 --- a/board/freescale/ls2085ardb/ddr.c +++ b/board/freescale/ls2085ardb/ddr.c @@ -147,9 +147,13 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size;
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + return fsl_ddr_sdram_size(); +#else puts("Initializing DDR....using SPD\n");
dram_size = fsl_ddr_sdram(); +#endif
return dram_size; } diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig new file mode 100644 index 0000000..39ba8c5 --- /dev/null +++ b/configs/ls2085ardb_nand_defconfig @@ -0,0 +1,4 @@ ++S:CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" ++S:CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS2085ARDB=y diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h index 24400e4..34aa3e5 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2085ardb.h @@ -139,11 +139,13 @@ unsigned long get_board_sys_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RST_CTL_RESET_EN 0x30 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RCW_SRC_NAND 0x119 #define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0) @@ -169,6 +171,33 @@ unsigned long get_board_sys_clk(void); FTIM2_GPCM_TWP(0x3E)) #define CONFIG_SYS_CS3_FTIM3 0x0
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (1536 * 1024) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SPL_PAD_TO 0x7ff40 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (512 * 1024) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) +#else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR @@ -187,6 +216,12 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x2000 +#endif + /* Debug Server firmware */ #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL @@ -232,11 +267,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_FSL_MEMAC #define CONFIG_PCI /* Enable PCIE */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
participants (3)
-
Scott Wood -
Tom Rini -
York Sun