[U-Boot] [PATCH 2/2] armv8: ls1012a: Update Refresh cycle for DDR

Refresh cycle value must be selected based on the frequency of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT] should be based on round up (tREFI/tCK) formula. For 500MHz, mdref value should be 0x0f3c8000.
Signed-off-by: Calvin Johnson calvin.johnson@nxp.com Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com --- include/fsl_mmdc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h index 833696b..a939d89 100644 --- a/include/fsl_mmdc.h +++ b/include/fsl_mmdc.h @@ -43,7 +43,7 @@
#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067
-#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x103e8000 +#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x0f3c8000
#define START_REFRESH 0x00000001

On 07/19/2016 03:24 AM, Prabhakar Kushwaha wrote:
Refresh cycle value must be selected based on the frequency of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT] should be based on round up (tREFI/tCK) formula. For 500MHz, mdref value should be 0x0f3c8000.
Signed-off-by: Calvin Johnson calvin.johnson@nxp.com Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com
include/fsl_mmdc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to fsl-qoriq master, awaiting upstream. Thanks.
York
participants (2)
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Prabhakar Kushwaha
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york sun