Hi Gabe

On Tue, Dec 6, 2011 at 9:12 AM, Gabe Black gabeblack@chromium.org wrote:

U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point.

Then let's just do it now - PCI is very standardised and I see no reason for the hose setup and scan to be too specific. If the case comes along later that a SoC or board needs something specific, we can add hooks or weaken the functions then. But for now, let's just create a standard implementation in arch/c86/lib/pci.c

It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it.

A hook is installed to configure PCI bus bridges as they encountered by u-boot. The hook extracts the secondary bus number from the bridge's config space and then recursively scans that bus.

Thanks! I think I am seeing this issue as well - Now I know how to deal with it :)

Signed-off-by: Gabe Black gabeblack@chromium.org

board/chromebook-x86/coreboot/coreboot_pci.c | 33 ++++++++++++++++++++++++++ 1 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/board/chromebook-x86/coreboot/coreboot_pci.c b/board/chromebook-x86/coreboot/coreboot_pci.c index 732ca3c..2ec6059 100644 --- a/board/chromebook-x86/coreboot/coreboot_pci.c +++ b/board/chromebook-x86/coreboot/coreboot_pci.c @@ -25,6 +25,39 @@

• MA 02111-1307 USA

*/

+#include <common.h> +#include <pci.h> +#include <asm/pci.h>

+static struct pci_controller coreboot_hose;

+#define X86_PCI_CONFIG_ADDR 0xCF8 +#define X86_PCI_CONFIG_DATA 0xCFC

Not needed [1],[2] (I missed arch/x86/include/asm/arch-sc520/pci.h in that patch so I'll fix that)

+static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,

•                         struct pci_config_table *table)
  

+{

•   u8 secondary;
  

•   hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
  

•   hose->last_busno = max(hose->last_busno, secondary);
  

•   pci_hose_scan_bus(hose, secondary);
  

+}

+static struct pci_config_table pci_coreboot_config_table[] = {

•   /* vendor, device, class, bus, dev, func */
  

•   { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
  

•     PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge},
  

Looks like one too many PCI_ANY_ID's to me

•   {}
  

+};

void pci_init_board(void) {

•   coreboot_hose.config_table = pci_coreboot_config_table;
  

•   coreboot_hose.first_busno = 0;
  

•   coreboot_hose.last_busno = 0;
  

•   coreboot_hose.region_count = 0;
  

•   pci_setup_type1(&coreboot_hose);
  

•   pci_register_hose(&coreboot_hose);
  

•   pci_hose_scan(&coreboot_hose);
  

Is there a reason this is not:

hose->last_busno = pci_hose_scan(hose);

I'm thinking that the presence of a bridge might confuse the issue. If so, is there something we need to change to deal with it (i.e. does the U-Boot PCI code in general have issues with PCI brdiges that needs to be dealt with)?

}

[1]http://patchwork.ozlabs.org/patch/124348/ [2]http://git.denx.de/?p=u-boot.git;a=commitdiff;h=1cfcf0370132315d6eee375

Regards,

Graeme