[U-Boot] [PATCH v4 0/2] sunxi: fix eMMC stability issues on A64
eMMC seems to require new clocking mode and calibration on A64, otherwise it is pretty unstable on some boards (e.g. Pinebook) with some eMMCs.
v2: - improve comment about calibration for eMMC on A64 - simplify ifdef-s around configuring delays v3: - fix fallout due to ifdef simplification in v2 v4: - really fix ifdefs this time
Vasily Khoruzhick (2): sunxi-mmc: use new mode on A64 mmc: sunxi: run calibration on A64
arch/arm/include/asm/arch-sunxi/mmc.h | 6 +++++- arch/arm/mach-sunxi/Kconfig | 1 + drivers/mmc/sunxi_mmc.c | 13 +++++++++++++ 3 files changed, 19 insertions(+), 1 deletion(-)
That is necessary for using automatic calibration on A64 eMMC.
Signed-off-by: Vasily khoruzhick anarsoul@gmail.com --- arch/arm/mach-sunxi/Kconfig | 1 + drivers/mmc/sunxi_mmc.c | 2 ++ 2 files changed, 3 insertions(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 66fb094ac5..8a35033d1f 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -257,6 +257,7 @@ config MACH_SUN50I select SUNXI_GEN_SUN6I select SUN6I_PRCM select SUNXI_HIGH_SRAM + select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index fe6d82c7b4..34739c98b9 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -166,7 +166,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
if (new_mode) { #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE +#ifndef CONFIG_MACH_SUN50I val = CCM_MMC_CTRL_MODE_SEL_NEW; +#endif setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); #endif } else {
Hi,
On Fri, Jun 01, 2018 at 06:28:37PM -0700, Vasily Khoruzhick wrote:
That is necessary for using automatic calibration on A64 eMMC.
Signed-off-by: Vasily khoruzhick anarsoul@gmail.com
arch/arm/mach-sunxi/Kconfig | 1 + drivers/mmc/sunxi_mmc.c | 2 ++ 2 files changed, 3 insertions(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 66fb094ac5..8a35033d1f 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -257,6 +257,7 @@ config MACH_SUN50I select SUNXI_GEN_SUN6I select SUN6I_PRCM select SUNXI_HIGH_SRAM
- select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index fe6d82c7b4..34739c98b9 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -166,7 +166,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
if (new_mode) { #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE +#ifndef CONFIG_MACH_SUN50I
Didn't we agree on introducing another Kconfig option here?
Maxime
Along with using new mode it fixes eMMC instability on Pinebook
Signed-off-by: Vasily Khoruzhick anarsoul@gmail.com --- arch/arm/include/asm/arch-sunxi/mmc.h | 6 +++++- drivers/mmc/sunxi_mmc.c | 11 +++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index 1574b8e8fe..d6664a01f2 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -46,7 +46,9 @@ struct sunxi_mmc { u32 cbda; /* 0x94 */ u32 res2[26]; #ifdef CONFIG_SUNXI_GEN_SUN6I - u32 res3[64]; + u32 res3[17]; + u32 samp_dl; + u32 res4[46]; #endif u32 fifo; /* 0x100 / 0x200 FIFO access address */ }; @@ -130,5 +132,7 @@ struct sunxi_mmc { #define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) #define SUNXI_MMC_COMMON_RESET (1 << 18)
+#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7) + struct mmc *sunxi_mmc_init(int sdc_no); #endif /* _SUNXI_MMC_H */ diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 34739c98b9..9e47e06239 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -225,6 +225,17 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc) rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; writel(rval, &priv->reg->clkcr);
+#ifdef CONFIG_MACH_SUN50I + /* A64 needs to run calibration on eMMC controller and we + * have to set delay of zero before starting calibration. + * Allwinner BSP driver sets a delay only in the case of + * using HS400 which is not supported by mainline U-Boot or + * Linux at the moment + */ + if (priv->mmc_no == 2) + writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl); +#endif + /* Re-enable Clock */ rval |= SUNXI_MMC_CLK_ENABLE; writel(rval, &priv->reg->clkcr);
participants (2)
-
Maxime Ripard -
Vasily Khoruzhick