From: Franklin S Cooper Jr fcooper@ti.com

By default VOUT3 occupies the pins required for NAND. Therefore, create a seperate entry that can be use to reconfigure these pins to work for NAND.

On the EVM SWITCH 8 pins 0 and 1 will be used to determine if NAND is enabled or not. For NAND to be selected pin 0 should be on and pin 1 should be off. Any other combination will assume NAND shouldn't be enabled.

Signed-off-by: Franklin S Cooper Jr fcooper@ti.com Signed-off-by: Faiz Abbas faiz_abbas@ti.com --- board/ti/dra7xx/mux_data.h | 60 ++++++++++++++++++++++++++++---------- 1 file changed, 44 insertions(+), 16 deletions(-)

diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index f1f6bd5316..75da5cb608 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -220,22 +220,6 @@ const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = { };

const struct pad_conf_entry dra71x_core_padconf_array[] = { - {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ - {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ - {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ - {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */ - {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */ - {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */ - {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */ - {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */ - {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */ - {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */ - {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */ - {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */ - {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */ - {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */ - {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */ - {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */ {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */ {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */ {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */ @@ -370,6 +354,50 @@ const struct pad_conf_entry dra71x_core_padconf_array[] = { {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */ };

+const struct pad_conf_entry dra71x_vout3_padconf_array[] = { + {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ + {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ + {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ + {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */ + {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */ + {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */ + {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */ + {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */ + {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */ + {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */ + {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */ + {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */ + {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */ + {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */ + {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */ + {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */ +}; + +const struct pad_conf_entry dra71x_nand_padconf_array[] = { + {GPMC_AD0, (M0 | PIN_INPUT)}, /* gpmc_ad0.gpmc_ad0 */ + {GPMC_AD1, (M0 | PIN_INPUT)}, /* gpmc_ad1.gpmc_ad1 */ + {GPMC_AD2, (M0 | PIN_INPUT)}, /* gpmc_ad2.gpmc_ad2 */ + {GPMC_AD3, (M0 | PIN_INPUT)}, /* gpmc_ad3.gpmc_ad3 */ + {GPMC_AD4, (M0 | PIN_INPUT)}, /* gpmc_ad4.gpmc_ad4 */ + {GPMC_AD5, (M0 | PIN_INPUT)}, /* gpmc_ad5.gpmc_ad5 */ + {GPMC_AD6, (M0 | PIN_INPUT)}, /* gpmc_ad6.gpmc_ad6 */ + {GPMC_AD7, (M0 | PIN_INPUT)}, /* gpmc_ad7.gpmc_ad7 */ + {GPMC_AD8, (M0 | PIN_INPUT)}, /* gpmc_ad8.gpmc_ad8 */ + {GPMC_AD9, (M0 | PIN_INPUT)}, /* gpmc_ad9.gpmc_ad9 */ + {GPMC_AD10, (M0 | PIN_INPUT)}, /* gpmc_ad10.gpmc_ad10 */ + {GPMC_AD11, (M0 | PIN_INPUT)}, /* gpmc_ad11.gpmc_ad11 */ + {GPMC_AD12, (M0 | PIN_INPUT)}, /* gpmc_ad12.gpmc_ad12 */ + {GPMC_AD13, (M0 | PIN_INPUT)}, /* gpmc_ad13.gpmc_ad13 */ + {GPMC_AD14, (M0 | PIN_INPUT)}, /* gpmc_ad14.gpmc_ad14 */ + {GPMC_AD15, (M0 | PIN_INPUT)}, /* gpmc_ad15.gpmc_ad15 */ + {GPMC_CS0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_cs0.gpmc_cs0 */ + {GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLDOWN)}, /* gpmc_advn_ale.gpmc_advn_ale */ + {GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpmc_oen_ren */ + {GPMC_WEN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpmc_wen */ + {GPMC_BEN0, (M0 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.gpmc_ben0 */ + {GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpmc_wait0 */ +}; + const struct pad_conf_entry early_padconf[] = { {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */ {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */

From: Franklin S Cooper Jr fcooper@ti.com

If SW 8 pins 0 and 1 indicate that NAND should be enabled then the pins pinmux must be reconfigured for NAND mode.

Therefore, enable NAND by reconfiguring the pinmux.

Signed-off-by: Franklin S Cooper Jr fcooper@ti.com Signed-off-by: Faiz Abbas faiz_abbas@ti.com --- board/ti/dra7xx/evm.c | 56 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+)

diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index d69641e3a0..446ce8399c 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -27,6 +27,7 @@ #include <environment.h> #include <dwc3-uboot.h> #include <dwc3-omap-uboot.h> +#include <i2c.h> #include <ti-usb-phy-uboot.h> #include <miiphy.h>

@@ -55,6 +56,10 @@ DECLARE_GLOBAL_DATA_PTR;

#define SYSINFO_BOARD_NAME_MAX_LEN 37

+/* I2C I/O Expander */ +#define NAND_PCF8575_ADDR 0x21 +#define NAND_PCF8575_I2C_BUS_NUM 0 + const struct omap_sysinfo sysinfo = { "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" }; @@ -777,6 +782,44 @@ void set_muxconf_regs(void) early_padconf, ARRAY_SIZE(early_padconf)); }

+#if defined(CONFIG_NAND) +static int nand_sw_detect(void) +{ + int rc; + uchar data[2]; + struct udevice *dev; + + rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM, + NAND_PCF8575_ADDR, 0, &dev); + if (rc) + return -1; + + rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data)); + if (rc) + return -1; + + /* We are only interested in P10 and P11 on PCF8575 which is equal to + * bits 8 and 9. + */ + data[1] = data[1] & 0x3; + + /* Ensure only P11 is set and P10 is cleared. This ensures only + * NAND (P10) is configured and not NOR (P11) which are both low + * true signals. NAND and NOR settings should not be enabled at + * the same time. + */ + if (data[1] == 0x2) + return 0; + + return -1; +} +#else +int nand_sw_detect(void) +{ + return -1; +} +#endif + #ifdef CONFIG_IODELAY_RECALIBRATION void recalibrate_iodelay(void) { @@ -796,6 +839,19 @@ void recalibrate_iodelay(void) npads = ARRAY_SIZE(dra71x_core_padconf_array); iodelay = dra71_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array); + /* If SW8 on the EVM is set to enable NAND then + * overwrite the pins used by VOUT3 with NAND. + */ + if (!nand_sw_detect()) { + delta_pads = dra71x_nand_padconf_array; + delta_npads = + ARRAY_SIZE(dra71x_nand_padconf_array); + } else { + delta_pads = dra71x_vout3_padconf_array; + delta_npads = + ARRAY_SIZE(dra71x_vout3_padconf_array); + } + } else if (board_is_dra72x_revc_or_later()) { delta_pads = dra72x_rgmii_padconf_array_revc; delta_npads =

Add NAND support to dra71x-evm defconfig

Signed-off-by: Faiz Abbas faiz_abbas@ti.com --- configs/dra7xx_evm_defconfig | 3 +++ configs/dra7xx_hs_evm_defconfig | 3 +++ 2 files changed, 6 insertions(+)

diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 3f25a2ec28..d71d989c4c 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_SPL=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -66,6 +67,8 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_OMAP_HS=y +CONFIG_NAND=y +CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index ee28e0c6ec..4642da3c01 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_DMA_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -70,6 +71,8 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_OMAP_HS=y +CONFIG_NAND=y +CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y

Now that NAND is supported on DRA71x include various NAND environment settings

Signed-off-by: Faiz Abbas faiz_abbas@ti.com --- configs/dra7xx_evm_defconfig | 4 +++- configs/dra7xx_hs_evm_defconfig | 4 +++- include/configs/dra7xx_evm.h | 2 +- include/configs/ti_omap5_common.h | 3 ++- include/environment/ti/nand.h | 26 ++++++++++++++++++++++++++ 5 files changed, 35 insertions(+), 4 deletions(-) create mode 100644 include/environment/ti/nand.h

diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index d71d989c4c..68eab7184e 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -23,13 +23,15 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),2m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 4642da3c01..076c800332 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -33,7 +33,9 @@ CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),2m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index f36a9c3e08..955d315608 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -136,7 +136,7 @@ 50, 51, 52, 53, 54, 55, 56, 57, } #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00140000 /* NAND: SPL related configs */ /* NAND: SPL falcon mode configs */ #ifdef CONFIG_SPL_OS_BOOT diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index ba57c40182..7c08e47d3d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -56,6 +56,7 @@

#include <environment/ti/boot.h> #include <environment/ti/mmc.h> +#include <environment/ti/nand.h>

#define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ @@ -65,6 +66,7 @@ DEFAULT_FDT_TI_ARGS \ DFUARGS \ NETARGS \ + NANDARGS \

/* * SPL related defines. The Public RAM memory map the ROM defines the @@ -100,7 +102,6 @@

#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (128 << 20)) - #ifdef CONFIG_SPL_BUILD #undef CONFIG_TIMER #endif diff --git a/include/environment/ti/nand.h b/include/environment/ti/nand.h new file mode 100644 index 0000000000..f838cb3ed1 --- /dev/null +++ b/include/environment/ti/nand.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * + * Environment variable definitions for NAND on TI boards. + */ + +#ifdef CONFIG_NAND +#define NANDARGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ + "nand read ${loadaddr} NAND.kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#else +#define NANDARGS "" +#endif +