This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it.

Cc: Angelo Durgehello angelo.dureghello@timesys.com Cc: TsiChung Liew Tsi-Chung.Liew@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/m68k/Kconfig | 9 - arch/m68k/cpu/mcf5445x/speed.c | 19 - arch/m68k/dts/M54455EVB.dts | 34 -- arch/m68k/dts/M54455EVB_a66.dts | 34 -- arch/m68k/dts/M54455EVB_i66.dts | 34 -- arch/m68k/dts/M54455EVB_intel.dts | 34 -- arch/m68k/dts/M54455EVB_stm33.dts | 34 -- arch/m68k/dts/Makefile | 5 - arch/m68k/include/asm/immap.h | 7 +- board/freescale/m54455evb/Kconfig | 15 - board/freescale/m54455evb/MAINTAINERS | 10 - board/freescale/m54455evb/Makefile | 7 - board/freescale/m54455evb/README | 407 ---------------------- board/freescale/m54455evb/m54455evb.c | 217 ------------ board/freescale/m54455evb/sbf_dram_init.S | 100 ------ configs/M54455EVB_a66_defconfig | 44 --- configs/M54455EVB_defconfig | 45 --- configs/M54455EVB_i66_defconfig | 44 --- configs/M54455EVB_intel_defconfig | 44 --- configs/M54455EVB_stm33_defconfig | 47 --- include/configs/M54455EVB.h | 356 ------------------- 21 files changed, 2 insertions(+), 1544 deletions(-) delete mode 100644 arch/m68k/dts/M54455EVB.dts delete mode 100644 arch/m68k/dts/M54455EVB_a66.dts delete mode 100644 arch/m68k/dts/M54455EVB_i66.dts delete mode 100644 arch/m68k/dts/M54455EVB_intel.dts delete mode 100644 arch/m68k/dts/M54455EVB_stm33.dts delete mode 100644 board/freescale/m54455evb/Kconfig delete mode 100644 board/freescale/m54455evb/MAINTAINERS delete mode 100644 board/freescale/m54455evb/Makefile delete mode 100644 board/freescale/m54455evb/README delete mode 100644 board/freescale/m54455evb/m54455evb.c delete mode 100644 board/freescale/m54455evb/sbf_dram_init.S delete mode 100644 configs/M54455EVB_a66_defconfig delete mode 100644 configs/M54455EVB_defconfig delete mode 100644 configs/M54455EVB_i66_defconfig delete mode 100644 configs/M54455EVB_intel_defconfig delete mode 100644 configs/M54455EVB_stm33_defconfig delete mode 100644 include/configs/M54455EVB.h

diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index cf45d789d63d..ac20ed230265 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -123,10 +123,6 @@ config M54451 bool select MCF5445x

-config M54455 - bool - select MCF5445x - config M52277 bool select MCF5227x @@ -199,10 +195,6 @@ config TARGET_M54451EVB bool "Support M54451EVB" select M54451

-config TARGET_M54455EVB - bool "Support M54455EVB" - select M54455 - config TARGET_AMCORE bool "Support AMCORE" select M5307 @@ -229,7 +221,6 @@ source "board/freescale/m5329evb/Kconfig" source "board/freescale/m5373evb/Kconfig" source "board/freescale/m54418twr/Kconfig" source "board/freescale/m54451evb/Kconfig" -source "board/freescale/m54455evb/Kconfig" source "board/sysam/amcore/Kconfig" source "board/sysam/stmark2/Kconfig"

diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index a0b9af8866b3..4809bb49d1cd 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -141,9 +141,6 @@ void setup_5445x_clocks(void) int bPci; #endif

-#ifdef CONFIG_M54455EVB - u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3); -#endif u8 bootmode;

/* To determine PCI is present or not */ @@ -163,22 +160,6 @@ void setup_5445x_clocks(void) #endif }

-#ifdef CONFIG_M54455EVB - bootmode = (in_8(cpld) & 0x03); - - if (bootmode != 3) { - /* Temporary read from CCR- fixed fb issue, must be the same clock - as pci or input clock, causing cpld/fpga read inconsistancy */ - fbtemp = pPllmult[ccm->ccr & fbpll_mask]; - - /* Break down into small pieces, code still in flex bus */ - pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF; - temp = fbtemp - 1; - pcrvalue |= PLL_PCR_OUTDIV3(temp); - - out_be32(&pll->pcr, pcrvalue); - } -#endif #ifdef CONFIG_M54451EVB /* No external logic to read the bootmode, hard coded from built */ #ifdef CONFIG_CF_SBF diff --git a/arch/m68k/dts/M54455EVB.dts b/arch/m68k/dts/M54455EVB.dts deleted file mode 100644 index b0ffb5144d8e..000000000000 --- a/arch/m68k/dts/M54455EVB.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5445x.dtsi" - -/ { - model = "Freescale M54455EVB"; - compatible = "fsl,M54455EVB"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M54455EVB_a66.dts b/arch/m68k/dts/M54455EVB_a66.dts deleted file mode 100644 index c2557bd2e6b3..000000000000 --- a/arch/m68k/dts/M54455EVB_a66.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5445x.dtsi" - -/ { - model = "Freescale M54455EVB_a66"; - compatible = "fsl,M54455EVB_a66"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M54455EVB_i66.dts b/arch/m68k/dts/M54455EVB_i66.dts deleted file mode 100644 index 3c9161bfae27..000000000000 --- a/arch/m68k/dts/M54455EVB_i66.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5445x.dtsi" - -/ { - model = "Freescale M54455EVB_i66"; - compatible = "fsl,M54455EVB_i66"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M54455EVB_intel.dts b/arch/m68k/dts/M54455EVB_intel.dts deleted file mode 100644 index 54209d25a70d..000000000000 --- a/arch/m68k/dts/M54455EVB_intel.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5445x.dtsi" - -/ { - model = "Freescale M54455EVB_intel"; - compatible = "fsl,M5275EVB_intel"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M54455EVB_stm33.dts b/arch/m68k/dts/M54455EVB_stm33.dts deleted file mode 100644 index 701b9a719b4b..000000000000 --- a/arch/m68k/dts/M54455EVB_stm33.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5445x.dtsi" - -/ { - model = "Freescale M54455EVB_stm33"; - compatible = "fsl,M5275EVB_stm33"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile index 47260a101d8a..15441cdfd387 100644 --- a/arch/m68k/dts/Makefile +++ b/arch/m68k/dts/Makefile @@ -25,11 +25,6 @@ dtb-$(CONFIG_TARGET_M54418TWR) += M54418TWR.dtb \ M54418TWR_nand_rmii_lowfreq.dtb dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \ M54451EVB_stmicro.dtb -dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \ - M54455EVB_intel.dtb \ - M54455EVB_stm33.dtb \ - M54455EVB_a66.dtb \ - M54455EVB_i66.dtb dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb

diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index cabdb0f1a5e0..07d9745b1438 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -330,14 +330,11 @@

#endif /* CONFIG_M54418 */

-#if defined(CONFIG_M54451) || defined(CONFIG_M54455) +#if defined(CONFIG_M54451) #include <asm/immap_5445x.h> #include <asm/m5445x.h>

#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) -#if defined(CONFIG_M54455EVB) -#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#endif

#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))

@@ -364,7 +361,7 @@ #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) #define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE) #endif -#endif /* CONFIG_M54451 || CONFIG_M54455 */ +#endif /* CONFIG_M54451 */

#ifdef CONFIG_M547x #include <asm/immap_547x_8x.h> diff --git a/board/freescale/m54455evb/Kconfig b/board/freescale/m54455evb/Kconfig deleted file mode 100644 index 096bce83121a..000000000000 --- a/board/freescale/m54455evb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M54455EVB - -config SYS_CPU - default "mcf5445x" - -config SYS_BOARD - default "m54455evb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M54455EVB" - -endif diff --git a/board/freescale/m54455evb/MAINTAINERS b/board/freescale/m54455evb/MAINTAINERS deleted file mode 100644 index 27ced3c7b1fa..000000000000 --- a/board/freescale/m54455evb/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -M54455EVB BOARD -M: TsiChung Liew Tsi-Chung.Liew@nxp.com -S: Maintained -F: board/freescale/m54455evb/ -F: include/configs/M54455EVB.h -F: configs/M54455EVB_defconfig -F: configs/M54455EVB_a66_defconfig -F: configs/M54455EVB_i66_defconfig -F: configs/M54455EVB_intel_defconfig -F: configs/M54455EVB_stm33_defconfig diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile deleted file mode 100644 index eff8ab066060..000000000000 --- a/board/freescale/m54455evb/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m54455evb.o -extra-y += sbf_dram_init.o diff --git a/board/freescale/m54455evb/README b/board/freescale/m54455evb/README deleted file mode 100644 index 26d3cc81fd55..000000000000 --- a/board/freescale/m54455evb/README +++ /dev/null @@ -1,407 +0,0 @@ -Freescale MCF54455EVB ColdFire Development Board -================================================ - -TsiChung Liew(Tsi-Chung.Liew@freescale.com) -Created 4/08/07 -=========================================== - - -Changed files: -============== - -- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init -- board/freescale/m54455evb/flash.c Atmel and INTEL flash support -- board/freescale/m54455evb/Makefile Makefile -- board/freescale/m54455evb/config.mk config make -- board/freescale/m54455evb/u-boot.lds Linker description - -- common/cmd_bdinfo.c Clock frequencies output -- common/cmd_mii.c mii support - -- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code -- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs -- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support -- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock -- arch/m68k/cpu/mcf5445x/Makefile Makefile -- arch/m68k/cpu/mcf5445x/config.mk config make -- arch/m68k/cpu/mcf5445x/start.S start up assembly code - -- board/freescale/m54455evb/README This readme file - -- drivers/net/mcffec.c ColdFire common FEC driver -- drivers/serial/mcfuart.c ColdFire common UART driver - -- include/asm-m68k/bitops.h Bit operation function export -- include/asm-m68k/byteorder.h Byte order functions -- include/asm-m68k/fec.h FEC structure and definition -- include/asm-m68k/fsl_i2c.h I2C structure and definition -- include/asm-m68k/global_data.h Global data structure -- include/asm-m68k/immap.h ColdFire specific header file and driver macros -- include/asm-m68k/immap_5445x.h mcf5445x specific header file -- include/asm-m68k/io.h io functions -- include/asm-m68k/m5445x.h mcf5445x specific header file -- include/asm-m68k/posix_types.h Posix -- include/asm-m68k/processor.h header file -- include/asm-m68k/ptrace.h Exception structure -- include/asm-m68k/rtc.h Realtime clock header file -- include/asm-m68k/string.h String function export -- include/asm-m68k/timer.h Timer structure and definition -- include/asm-m68k/types.h Data types definition -- include/asm-m68k/uart.h Uart structure and definition -- include/asm-m68k/u-boot.h U-Boot structure - -- include/configs/M54455EVB.h Board specific configuration file - -- arch/m68k/lib/board.c board init function -- arch/m68k/lib/cache.c -- arch/m68k/lib/interrupts Coldfire common interrupt functions -- arch/m68k/lib/m68k_linux.c -- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) -- arch/m68k/lib/traps.c Exception init code - -- rtc/mcfrtc.c Realtime clock Driver - -1 MCF5445x specific Options/Settings -==================================== -1.1 pre-loader is no longer suppoer in thie coldfire family - -1.2 Configuration settings for M54455EVB Development Board -CONFIG_MCF5445x -- define for all MCF5445x CPUs -CONFIG_M54455 -- define for all Freescale MCF54455 CPUs -CONFIG_M54455EVB -- define for M54455EVB board - -CONFIG_MCFUART -- define to use common CF Uart driver -CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 -CONFIG_BAUDRATE -- define UART baudrate - -CONFIG_MCFRTC -- define to use common CF RTC driver -CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h -CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency -RTC_DEBUG -- define to show RTC debug message -CONFIG_CMD_DATE -- enable to use date feature in U-Boot - -CONFIG_MCFFEC -- define to use common CF FEC driver -CONFIG_MII -- enable to use MII driver -CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c -CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery -CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer -CONFIG_SYS_FAULT_ECHO_LINK_DOWN-- -CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration -CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration -CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register -CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register -MCFFEC_TOUT_LOOP -- set FEC timeout loop -CONFIG_HAS_ETH1 -- define to enable second FEC in U-Boot - -CONFIG_ISO_PARTITION -- enable ISO read/write -CONFIG_DOS_PARTITION -- enable DOS read/write -CONFIG_IDE_RESET -- define ide_reset() -CONFIG_IDE_PREINIT -- define ide_preinit() -CONFIG_ATAPI -- define ATAPI support -CONFIG_LBA48 -- define LBA48 (larger than 120GB) support -CONFIG_SYS_IDE_MAXBUS -- define max channel -CONFIG_SYS_IDE_MAXDEVICE -- define max devices per channel -CONFIG_SYS_ATA_BASE_ADDR -- define ATA base address -CONFIG_SYS_ATA_IDE0_OFFSET -- define ATA IDE0 offset -CONFIG_SYS_ATA_DATA_OFFSET -- define ATA data IO -CONFIG_SYS_ATA_REG_OFFSET -- define for normal register accesses -CONFIG_SYS_ATA_ALT_OFFSET -- define for alternate registers -CONFIG_SYS_ATA_STRIDE -- define for Interval between registers -_IO_BASE -- define for IO base address - -CONFIG_MCFTMR -- define to use DMA timer - -CONFIG_SYS_FSL_I2C -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset -CONFIG_SYS_IMMR -- define for MBAR offset - -CONFIG_PCI -- define for PCI support -CONFIG_PCI_PNP -- define for Plug n play support -CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset -CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset -CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size -CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset -CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset -CONFIG_SYS_PCI_IO_SIZE -- PCI IO size -CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset -CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset -CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size - -CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc - -CONFIG_SYS_MBAR -- define MBAR offset - -CONFIG_SYS_ATMEL_BOOT -- To determine the U-Boot is booted from Atmel or Intel - -CONFIG_MONITOR_IS_IN_RAM -- Not support - -CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM - -CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register -CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register -CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register - -CONFIG_SYS_ATMEL_BASE -- defines the Atmel Flash base -CONFIG_SYS_INTEL_BASE -- defines the Intel Flash base - -CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base -CONFIG_SYS_SDRAM_BASE1 -- defines the DRAM Base 1 - -2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL -=========================================== -2.1. System memory map: - Flash: 0x00000000-0x3FFFFFFF (1024MB) - DDR: 0x40000000-0x7FFFFFFF (1024MB) - SRAM: 0x80000000-0x8FFFFFFF (256MB) - ATA: 0x90000000-0x9FFFFFFF (256MB) - PCI: 0xA0000000-0xBFFFFFFF (512MB) - FlexBus: 0xC0000000-0xDFFFFFFF (512MB) - IP: 0xF0000000-0xFFFFFFFF (256MB) - -2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and - linux kernel, you can customize it based on your system requirements: - Atmel boot: - Flash0: 0x00000000-0x0007FFFF (512KB) - Flash1: 0x04000000-0x05FFFFFF (32MB) - Intel boot: - Flash0: 0x00000000-0x01FFFFFF (32MB) - Flash1: 0x04000000-0x0407FFFF (512KB) - - CPLD: 0x08000000-0x08FFFFFF (16MB) - FPGA: 0x09000000-0x09FFFFFF (16MB) - DDR: 0x40000000-0x4FFFFFFF (256MB) - SRAM: 0x80000000-0x80007FFF (32KB) - IP: 0xFC000000-0xFC0FFFFF (64KB) - -3. SWITCH SETTINGS -================== -3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL - SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state - SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down - 1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active - SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down - SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL - -4. COMPILATION -============== -4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version) -from codesourcery.com was used. Download it from: -http://www.codesourcery.com/gnu_toolchains/coldfire/download.html - -4.2 Compilation - export CROSS_COMPILE=cross-compile-prefix - cd u-boot-1.x.x - make distclean - make M54455EVB_config, or - default to atmel 33Mhz input clock - make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock - make M54455EVB_a33_config, or - default to atmel 33Mhz input clock - make M54455EVB_a66_config, or - default to atmel 66Mhz input clock - make M54455EVB_intel_config, or - default to intel 33Mhz input clock - make M54455EVB_i33_config, or - default to intel 33Mhz input clock - make M54455EVB_i66_config, or - default to intel 66Mhz input clock - make - -5. SCREEN DUMP -============== -5.1 M54455EVB Development board - Boot from Atmel (NOTE: May not show exactly the same) - -U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08) - -CPU: Freescale MCF54455 (Mask:48 Version:1) - CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz - PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz -Board: Freescale M54455 EVB -I2C: ready -DRAM: 256 MB -FLASH: 16.5 MB -In: serial -Out: serial -Err: serial -Net: FEC0, FEC1 -IDE: Bus 0: not available --> print -bootargs=root=/dev/ram rw -bootdelay=1 -baudrate=115200 -ethaddr=00:e0:0c:bc:e5:60 -eth1addr=00:e0:0c:bc:e5:61 -hostname=M54455EVB -netdev=eth0 -inpclk=33333333 -loadaddr=40010000 -load=tftp ${loadaddr) ${u-boot} -upd=run load; run prog -prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save -ethact=FEC0 -mtdids=nor0=M54455EVB-1 -mtdparts=M54455EVB-1:16m(user) -u-boot=u-boot54455.bin -filesize=292b4 -fileaddr=40010000 -gatewayip=192.168.1.1 -netmask=255.255.255.0 -ipaddr=192.168.1.3 -serverip=192.168.1.2 -stdin=serial -stdout=serial -stderr=serial -mem=261632k - -Environment size: 563/8188 bytes --> bdinfo -memstart = 0x40000000 -memsize = 0x10000000 -flashstart = 0x00000000 -flashsize = 0x01080000 -flashoffset = 0x00000000 -sramstart = 0x80000000 -sramsize = 0x00008000 -mbar = 0xFC000000 -busfreq = 133.333 MHz -pcifreq = 33.333 MHz -flbfreq = 66.666 MHz -inpfreq = 33.333 MHz -vcofreq = 533.333 MHz -ethaddr = 00:E0:0C:BC:E5:60 -eth1addr = 00:E0:0C:BC:E5:61 -ip_addr = 192.168.1.3 -baudrate = 115200 bps --> --> help -? - alias for 'help' -base - print or set address offset -bdinfo - print Board Info structure -boot - boot default, i.e., run 'bootcmd' -bootd - boot default, i.e., run 'bootcmd' -bootelf - Boot from an ELF image in memory -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -bootvx - Boot vxWorks from an ELF image -cmp - memory compare -coninfo - print console devices and information -cp - memory copy -crc32 - checksum calculation -date - get/set/reset date & time -dcache - enable or disable data cache -diskboot- boot from IDE device -echo - echo args to console -erase - erase FLASH memory -ext2load- load binary file from a Ext2 filesystem -ext2ls - list files in a directory (default /) -fatinfo - print information about filesystem -fatload - load binary file from a dos filesystem -fatls - list files in a directory (default /) -flinfo - print FLASH memory information -fsinfo - print information about filesystems -fsload - load binary file from a filesystem image -go - start application at address 'addr' -help - print online help -i2c - I2C sub-system -icache - enable or disable instruction cache -ide - IDE sub-system -iminfo - print header information for application image -imls - list all images found in flash -itest - return true/false on integer compare -loadb - load binary file over serial line (kermit mode) -loads - load S-Record file over serial line -loady - load binary file over serial line (ymodem mode) -loop - infinite loop on address range -ls - list files in a directory (default /) -md - memory display -mii - MII utility commands -mm - memory modify (auto-incrementing) -mtest - simple RAM test -mw - memory write (fill) -nfs - boot image via network using NFS protocol -nm - memory modify (constant address) -pci - list and access PCI Configuration Space -ping - send ICMP ECHO_REQUEST to network host -printenv- print environment variables -protect - enable or disable FLASH write protection -rarpboot- boot image via network using RARP/TFTP protocol -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -sleep - delay execution for some time -source - run script from memory -tftpboot- boot image via network using TFTP protocol -version - print monitor version -->bootm 4000000 - -## Booting image at 04000000 ... - Image Name: Linux Kernel Image - Created: 2007-08-14 15:13:00 UTC - Image Type: M68K Linux Kernel Image (uncompressed) - Data Size: 2301952 Bytes = 2.2 MB - Load Address: 40020000 - Entry Point: 40020000 - Verifying Checksum ... OK -OK -Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr -erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007 -starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB -Built 1 zonelists. Total pages: 32624 -Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph -ysmap-flash.0:5M(kernel)ro,-(jffs2) -PID hash table entries: 1024 (order: 10, 4096 bytes) -Console: colour dummy device 80x25 -Dentry cache hash table entries: 32768 (order: 4, 131072 bytes) -Inode-cache hash table entries: 16384 (order: 3, 65536 bytes) -Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init) -Mount-cache hash table entries: 1024 -NET: Registered protocol family 16 -SCSI subsystem initialized -NET: Registered protocol family 2 -IP route cache hash table entries: 2048 (order: 0, 8192 bytes) -TCP established hash table entries: 8192 (order: 2, 32768 bytes) -TCP bind hash table entries: 4096 (order: 1, 16384 bytes) -TCP: Hash tables configured (established 8192 bind 4096) -TCP reno registered -JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc. -io scheduler noop registered -io scheduler anticipatory registered -io scheduler deadline registered -io scheduler cfq registered (default) -ColdFire internal UART serial driver version 1.00 -ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART -ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART -ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART -RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize -loop: loaded (max 8 devices) -FEC ENET Version 0.2 -fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849 -eth0: ethernet 00:08:ee:00:e4:19 -physmap platform flash device: 01000000 at 04000000 -physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank - Intel/Sharp Extended Query Table at 0x0031 -Using buffer write method -cfi_cmdset_0001: Erase suspend on write enabled -2 cmdlinepart partitions found on MTD device physmap-flash.0 -Creating 2 MTD partitions on "physmap-flash.0": -0x00000000-0x00500000 : "kernel" -mtd: Giving out device 0 to kernel -0x00500000-0x01000000 : "jffs2" -mtd: Giving out device 1 to jffs2 -mice: PS/2 mouse device common for all mice -i2c /dev entries driver -TCP cubic registered -NET: Registered protocol family 1 -NET: Registered protocol family 17 -NET: Registered protocol family 15 -VFS: Mounted root (jffs2 filesystem). -Setting the hostname to freescale -Mounting filesystems -mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory -Starting syslogd and klogd -Setting up networking on loopback device: -Setting up networking on eth0: -eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX. -Adding static route for default gateway to 172.27.255.254: -Setting nameserver to 172.27.0.1 in /etc/resolv.conf: -Starting inetd: -/ # diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c deleted file mode 100644 index c749ee407e77..000000000000 --- a/board/freescale/m54455evb/m54455evb.c +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include <common.h> -#include <init.h> -#include <pci.h> -#include <asm/global_data.h> -#include <asm/immap.h> -#include <asm/io.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale M54455 EVB\n"); - return 0; -}; - -int dram_init(void) -{ - u32 dramsize; -#ifdef CONFIG_CF_SBF - /* - * Serial Boot: The dram is already initialized in start.S - * only require to return DRAM size - */ - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1; -#else - sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); - gpio_t *gpio = (gpio_t *)(MMAP_GPIO); - u32 i; - - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1; - - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - - out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH); - - out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); - out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i); - - out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); - - /* Issue PALL */ - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); - - /* Issue LEMR */ - out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408); - out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300); - - udelay(500); - - /* Issue PALL */ - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); - - /* Perform two refresh cycles */ - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); - - out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200); - - out_be32(&sdram->sdcr, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); - - udelay(100); -#endif - gd->ram_size = dramsize << 1; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} - -#if defined(CONFIG_IDE) -#include <ata.h> - -int ide_preinit(void) -{ - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - u32 tmp; - - tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10; - setbits_8(&gpio->par_fec, tmp); - tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) | - (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW)); - setbits_be16(&gpio->par_feci2c, tmp); - - setbits_be16(&gpio->par_ata, - GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 | - GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 | - GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ | - GPIO_PAR_ATA_IORDY_IORDY); - setbits_be16(&gpio->par_pci, - GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ); - - return (0); -} - -void ide_set_reset(int idereset) -{ - atac_t *ata = (atac_t *) MMAP_ATA; - long period; - /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ - int piotms[5][9] = { - {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ - {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ - {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ - {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ - {25, 70, 20, 10, 20, 5, 10, 0, 35} - }; /* PIO 4 */ - - if (idereset) { - /* control reset */ - out_8(&ata->cr, 0); - udelay(10000); - } else { -#define CALC_TIMING(t) (t + period - 1) / period - period = 1000000000 / gd->bus_clk; /* period in ns */ - - /*ata->ton = CALC_TIMING (180); */ - out_8(&ata->t1, CALC_TIMING(piotms[2][0])); - out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); - out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); - out_8(&ata->ta, CALC_TIMING(piotms[2][8])); - out_8(&ata->trd, CALC_TIMING(piotms[2][7])); - out_8(&ata->t4, CALC_TIMING(piotms[2][3])); - out_8(&ata->t9, CALC_TIMING(piotms[2][6])); - - /* IORDY enable */ - out_8(&ata->cr, 0x40); - udelay(200000); - /* IORDY enable */ - setbits_8(&ata->cr, 0x01); - } -} -#endif - -#if defined(CONFIG_PCI) -/* - * Initialize PCI devices, report devices found. - */ -static struct pci_controller hose; -extern void pci_mcf5445x_init(struct pci_controller *hose); - -void pci_init_board(void) -{ - pci_mcf5445x_init(&hose); -} -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_FLASH_CFI_LEGACY) -#include <flash.h> -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) -{ - int sect[] = CONFIG_SYS_ATMEL_SECT; - int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ; - int i, j, k; - - if (base != CONFIG_SYS_ATMEL_BASE) - return 0; - - info->flash_id = 0x01000000; - info->portwidth = 1; - info->chipwidth = 1; - info->buffer_size = 1; - info->erase_blk_tout = 16384; - info->write_tout = 2; - info->buffer_write_tout = 5; - info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */ - info->cmd_reset = 0x00F0; - info->interface = FLASH_CFI_X8; - info->legacy_unlock = 0; - info->manufacturer_id = (u16) ATM_MANUFACT; - info->device_id = ATM_ID_LV040; - info->device_id2 = 0; - - info->ext_addr = 0; - info->cfi_version = 0x3133; - info->cfi_offset = 0x0000; - info->addr_unlock1 = 0x00000555; - info->addr_unlock2 = 0x000002AA; - info->name = "CFI conformant"; - - info->size = 0; - info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT; - info->start[0] = base; - for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) { - info->size += sect[i] * sectsz[i]; - - for (j = 0; j < sect[i]; j++, k++) { - info->start[k + 1] = info->start[k] + sectsz[i]; - info->protect[k] = 0; - } - } - - return 1; -} -#endif /* CONFIG_SYS_FLASH_CFI */ diff --git a/board/freescale/m54455evb/sbf_dram_init.S b/board/freescale/m54455evb/sbf_dram_init.S deleted file mode 100644 index fe5bb05ddc9a..000000000000 --- a/board/freescale/m54455evb/sbf_dram_init.S +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Board-specific sbf ddr/sdram init. - * - * (C) Copyright 2017 Angelo Dureghello angelo@sysam.it - */ - - #include <config.h> - -.global sbf_dram_init -.text - -sbf_dram_init: - /* Dram Initialization a1, a2, and d0 */ - /* mscr sdram */ - move.l #0xFC0A4074, %a1 - move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) - nop - - /* SDRAM Chip 0 and 1 */ - move.l #0xFC0B8110, %a1 - move.l #0xFC0B8114, %a2 - - /* calculate the size */ - move.l #0x13, %d1 - move.l #(CONFIG_SYS_SDRAM_SIZE), %d2 -#ifdef CONFIG_SYS_SDRAM_BASE1 - lsr.l #1, %d2 -#endif - -dramsz_loop: - lsr.l #1, %d2 - add.l #1, %d1 - cmp.l #1, %d2 - bne dramsz_loop -#ifdef CONFIG_SYS_NAND_BOOT - beq asm_nand_chk_status -#endif - /* SDRAM Chip 0 and 1 */ - move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) - or.l %d1, (%a1) -#ifdef CONFIG_SYS_SDRAM_BASE1 - move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2) - or.l %d1, (%a2) -#endif - nop - - /* dram cfg1 and cfg2 */ - move.l #0xFC0B8008, %a1 - move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1) - nop - move.l #0xFC0B800C, %a2 - move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2) - nop - - move.l #0xFC0B8000, %a1 /* Mode */ - move.l #0xFC0B8004, %a2 /* Ctrl */ - - /* Issue PALL */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) - nop - - /* Issue LEMR */ - move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1) - nop - move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1) - nop - - move.l #1000, %d1 - bsr asm_delay - - /* Issue PALL */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) - nop - - /* Perform two refresh cycles */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0 - nop - move.l %d0, (%a2) - move.l %d0, (%a2) - nop - - move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1) - nop - - move.l #500, %d1 - bsr asm_delay - - move.l #(CONFIG_SYS_SDRAM_CTRL), %d1 - and.l #0x7FFFFFFF, %d1 - - or.l #0x10000C00, %d1 - - move.l %d1, (%a2) - nop - - move.l #2000, %d1 - bsr asm_delay - - rts diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig deleted file mode 100644 index 50bdb2c0cce3..000000000000 --- a/configs/M54455EVB_a66_defconfig +++ /dev/null @@ -1,44 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_a66" -CONFIG_TARGET_M54455EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666" -CONFIG_BOOTDELAY=1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_ISO_PARTITION=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0x4040000 -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig deleted file mode 100644 index 40d025f66eaf..000000000000 --- a/configs/M54455EVB_defconfig +++ /dev/null @@ -1,45 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x4000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="M54455EVB" -CONFIG_TARGET_M54455EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333" -CONFIG_BOOTDELAY=1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="-> " -CONFIG_CMD_IMLS=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_ISO_PARTITION=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0x4040000 -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig deleted file mode 100644 index 97d5d15ad65b..000000000000 --- a/configs/M54455EVB_i66_defconfig +++ /dev/null @@ -1,44 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x0 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_i66" -CONFIG_TARGET_M54455EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666" -CONFIG_BOOTDELAY=1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_ISO_PARTITION=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0x40000 -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig deleted file mode 100644 index d82f091fea33..000000000000 --- a/configs/M54455EVB_intel_defconfig +++ /dev/null @@ -1,44 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x0 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_intel" -CONFIG_TARGET_M54455EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333" -CONFIG_BOOTDELAY=1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_ISO_PARTITION=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0x40000 -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig deleted file mode 100644 index 147d87e87894..000000000000 --- a/configs/M54455EVB_stm33_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x4FE00000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x30000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_stm33" -CONFIG_TARGET_M54455EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333" -CONFIG_BOOTDELAY=1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_ISO_PARTITION=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_USE_ENV_SPI_CS=y -CONFIG_ENV_SPI_CS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h deleted file mode 100644 index f3621d6326ef..000000000000 --- a/include/configs/M54455EVB.h +++ /dev/null @@ -1,356 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF54455 EVB board. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M54455EVB_H -#define _M54455EVB_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_M54455EVB /* M54455EVB board */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*) - -#undef CONFIG_WATCHDOG - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Network configuration */ -#ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_HAS_ETH1 -# define CONFIG_ETHPRIME "FEC0" -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 - -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#define CONFIG_HOSTNAME "M54455EVB" -#ifdef CONFIG_SYS_STMICRO_BOOT -/* ST Micro serial flash */ -#define CONFIG_SYS_LOAD_ADDR2 0x40010013 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "sbfhdr=sbfhdr.bin\0" \ - "uboot=u-boot.bin\0" \ - "load=tftp ${loadaddr} ${sbfhdr};" \ - "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ - "upd=run load; run prog\0" \ - "prog=sf probe 0:1 1000000 3;" \ - "sf erase 0 30000;" \ - "sf write ${loadaddr} 0 0x30000;" \ - "save\0" \ - "" -#else -/* Atmel and Intel */ -#ifdef CONFIG_SYS_ATMEL_BOOT -# define CONFIG_SYS_UBOOT_END 0x0403FFFF -#elif defined(CONFIG_SYS_INTEL_BOOT) -# define CONFIG_SYS_UBOOT_END 0x3FFFF -#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "uboot=u-boot.bin\0" \ - "load=tftp ${loadaddr} ${uboot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ - " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ - "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ - __stringify(CONFIG_SYS_UBOOT_END) ";" \ - "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ - " ${filesize}; save\0" \ - "" -#endif - -/* ATA configuration */ -#define CONFIG_IDE_RESET 1 -#define CONFIG_IDE_PREINIT 1 -#define CONFIG_ATAPI -#undef CONFIG_LBA48 - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 2 - -#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ - -/* Realtime clock */ -#define CONFIG_MCFRTC -#undef RTC_DEBUG -#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) - -/* Timer */ -#define CONFIG_MCFTMR - -/* I2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -/* DSPI and Serial Flash */ -#define CONFIG_CF_DSPI -#define CONFIG_SYS_SBFHDR_SIZE 0x13 - -/* PCI */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 - -#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_SYS_PCI_IO_BUS 0xB1000000 -#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS -#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 -#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS -#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 -#endif - -/* FPGA - Spartan 2 */ -/* experiment -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_SYS_FPGA_CHECK_CTRLC -*/ - -/* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK - -#define CONFIG_PRAM 2048 /* 2048 KB */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) - -#define CONFIG_SYS_MBAR 0xFC000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_BASE1 0x48000000 -#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x65311610 -#define CONFIG_SYS_SDRAM_CFG2 0x59670000 -#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x00010033 -#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA - -#ifdef CONFIG_CF_SBF -# define CONFIG_SERIAL_BOOT -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) -#else -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -/* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* - * Configuration for environment - * Environment is not embedded in u-boot. First time runing may have env - * crc error warning if there is no correct environment on the flash. - */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_STMICRO_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE -#endif -#ifdef CONFIG_SYS_ATMEL_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE -#endif -#ifdef CONFIG_SYS_INTEL_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE -#endif - -#ifdef CONFIG_SYS_FLASH_CFI - -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -# define CONFIG_SYS_FLASH_CHECKSUM -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } -# define CONFIG_FLASH_CFI_LEGACY - -#ifdef CONFIG_FLASH_CFI_LEGACY -# define CONFIG_SYS_ATMEL_REGION 4 -# define CONFIG_SYS_ATMEL_TOTALSECT 11 -# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} -# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} -#endif -#endif - -/* - * This is setting for JFFS2 support in u-boot. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ -#ifdef CONFIG_CMD_JFFS2 -#ifdef CF_STMICRO_BOOT -# define CONFIG_JFFS2_DEV "nor1" -# define CONFIG_JFFS2_PART_SIZE 0x01000000 -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) -#endif -#ifdef CONFIG_SYS_ATMEL_BOOT -# define CONFIG_JFFS2_DEV "nor1" -# define CONFIG_JFFS2_PART_SIZE 0x01000000 -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) -#endif -#ifdef CONFIG_SYS_INTEL_BOOT -# define CONFIG_JFFS2_DEV "nor0" -# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) -#endif -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ - CF_CACR_ICINVA | CF_CACR_EUSP) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ - CF_CACR_DEC | CF_CACR_DDCM_P | \ - CF_CACR_DCINVA) & ~CF_CACR_ICINVA) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -/* - * CS0 - NOR Flash 1, 2, 4, or 8MB - * CS1 - CompactFlash and registers - * CS2 - CPLD - * CS3 - FPGA - * CS4 - Available - * CS5 - Available - */ - -#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) - /* Atmel Flash */ -#define CONFIG_SYS_CS0_BASE 0x04000000 -#define CONFIG_SYS_CS0_MASK 0x00070001 -#define CONFIG_SYS_CS0_CTRL 0x00001140 -/* Intel Flash */ -#define CONFIG_SYS_CS1_BASE 0x00000000 -#define CONFIG_SYS_CS1_MASK 0x01FF0001 -#define CONFIG_SYS_CS1_CTRL 0x00000D60 - -#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE -#else -/* Intel Flash */ -#define CONFIG_SYS_CS0_BASE 0x00000000 -#define CONFIG_SYS_CS0_MASK 0x01FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00000D60 - /* Atmel Flash */ -#define CONFIG_SYS_CS1_BASE 0x04000000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x00001140 - -#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE -#endif - -/* CPLD */ -#define CONFIG_SYS_CS2_BASE 0x08000000 -#define CONFIG_SYS_CS2_MASK 0x00070001 -#define CONFIG_SYS_CS2_CTRL 0x003f1140 - -/* FPGA */ -#define CONFIG_SYS_CS3_BASE 0x09000000 -#define CONFIG_SYS_CS3_MASK 0x00070001 -#define CONFIG_SYS_CS3_CTRL 0x00000020 - -#endif /* _M54455EVB_H */

This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it.

Cc: Angelo Durgehello angelo.dureghello@timesys.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/m68k/Kconfig | 5 - arch/m68k/dts/M54418TWR.dts | 34 --- arch/m68k/dts/M54418TWR_nand_mii.dts | 34 --- arch/m68k/dts/M54418TWR_nand_rmii.dts | 34 --- arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts | 34 --- arch/m68k/dts/M54418TWR_serial_mii.dts | 34 --- arch/m68k/dts/M54418TWR_serial_rmii.dts | 34 --- arch/m68k/dts/Makefile | 6 - board/freescale/m54418twr/Kconfig | 15 - board/freescale/m54418twr/MAINTAINERS | 11 - board/freescale/m54418twr/Makefile | 7 - board/freescale/m54418twr/m54418twr.c | 117 -------- board/freescale/m54418twr/sbf_dram_init.S | 85 ------ configs/M54418TWR_defconfig | 36 --- configs/M54418TWR_nand_mii_defconfig | 33 -- configs/M54418TWR_nand_rmii_defconfig | 33 -- configs/M54418TWR_nand_rmii_lowfreq_defconfig | 33 -- configs/M54418TWR_serial_mii_defconfig | 36 --- configs/M54418TWR_serial_rmii_defconfig | 36 --- doc/README.m54418twr | 245 --------------- include/configs/M54418TWR.h | 283 ------------------ 21 files changed, 1185 deletions(-) delete mode 100644 arch/m68k/dts/M54418TWR.dts delete mode 100644 arch/m68k/dts/M54418TWR_nand_mii.dts delete mode 100644 arch/m68k/dts/M54418TWR_nand_rmii.dts delete mode 100644 arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts delete mode 100644 arch/m68k/dts/M54418TWR_serial_mii.dts delete mode 100644 arch/m68k/dts/M54418TWR_serial_rmii.dts delete mode 100644 board/freescale/m54418twr/Kconfig delete mode 100644 board/freescale/m54418twr/MAINTAINERS delete mode 100644 board/freescale/m54418twr/Makefile delete mode 100644 board/freescale/m54418twr/m54418twr.c delete mode 100644 board/freescale/m54418twr/sbf_dram_init.S delete mode 100644 configs/M54418TWR_defconfig delete mode 100644 configs/M54418TWR_nand_mii_defconfig delete mode 100644 configs/M54418TWR_nand_rmii_defconfig delete mode 100644 configs/M54418TWR_nand_rmii_lowfreq_defconfig delete mode 100644 configs/M54418TWR_serial_mii_defconfig delete mode 100644 configs/M54418TWR_serial_rmii_defconfig delete mode 100644 doc/README.m54418twr delete mode 100644 include/configs/M54418TWR.h

diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index ac20ed230265..c48b8a543d9a 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -187,10 +187,6 @@ config TARGET_M5373EVB bool "Support M5373EVB" select M5373

-config TARGET_M54418TWR - bool "Support M54418TWR" - select M54418 - config TARGET_M54451EVB bool "Support M54451EVB" select M54451 @@ -219,7 +215,6 @@ source "board/freescale/m5282evb/Kconfig" source "board/freescale/m53017evb/Kconfig" source "board/freescale/m5329evb/Kconfig" source "board/freescale/m5373evb/Kconfig" -source "board/freescale/m54418twr/Kconfig" source "board/freescale/m54451evb/Kconfig" source "board/sysam/amcore/Kconfig" source "board/sysam/stmark2/Kconfig" diff --git a/arch/m68k/dts/M54418TWR.dts b/arch/m68k/dts/M54418TWR.dts deleted file mode 100644 index 058707fdf03c..000000000000 --- a/arch/m68k/dts/M54418TWR.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5441x.dtsi" - -/ { - model = "Freescale M54418TWR"; - compatible = "fsl,M54418TWR"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M54418TWR_nand_mii.dts b/arch/m68k/dts/M54418TWR_nand_mii.dts deleted file mode 100644 index 8afcb0fb99f8..000000000000 --- a/arch/m68k/dts/M54418TWR_nand_mii.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5441x.dtsi" - -/ { - model = "Freescale M54418TWR_nand_mii"; - compatible = "fsl,M54418TWR_nand_mii"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M54418TWR_nand_rmii.dts b/arch/m68k/dts/M54418TWR_nand_rmii.dts deleted file mode 100644 index fc2eb5b3bc32..000000000000 --- a/arch/m68k/dts/M54418TWR_nand_rmii.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5441x.dtsi" - -/ { - model = "Freescale M54418TWR_nand_rmii"; - compatible = "fsl,M54418TWR_nand_rmii"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts deleted file mode 100644 index a39d1023b247..000000000000 --- a/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5441x.dtsi" - -/ { - model = "Freescale M54418TWR_nand_rmii_lowfreq"; - compatible = "fsl,M54418TWR_nand_rmii_lowfreq"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M54418TWR_serial_mii.dts b/arch/m68k/dts/M54418TWR_serial_mii.dts deleted file mode 100644 index edf98db0037f..000000000000 --- a/arch/m68k/dts/M54418TWR_serial_mii.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5441x.dtsi" - -/ { - model = "Freescale M54418TWR_serial_mii"; - compatible = "fsl,M54418TWR_serial_mii"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M54418TWR_serial_rmii.dts b/arch/m68k/dts/M54418TWR_serial_rmii.dts deleted file mode 100644 index e4639fe431df..000000000000 --- a/arch/m68k/dts/M54418TWR_serial_rmii.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5441x.dtsi" - -/ { - model = "Freescale M54418TWR_serial_rmii"; - compatible = "fsl,M54418TWR_serial_rmii"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile index 15441cdfd387..829edb8dbc27 100644 --- a/arch/m68k/dts/Makefile +++ b/arch/m68k/dts/Makefile @@ -17,12 +17,6 @@ dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb -dtb-$(CONFIG_TARGET_M54418TWR) += M54418TWR.dtb \ - M54418TWR_nand_mii.dtb \ - M54418TWR_nand_rmii.dtb \ - M54418TWR_serial_mii.dtb \ - M54418TWR_serial_rmii.dtb \ - M54418TWR_nand_rmii_lowfreq.dtb dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \ M54451EVB_stmicro.dtb dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb diff --git a/board/freescale/m54418twr/Kconfig b/board/freescale/m54418twr/Kconfig deleted file mode 100644 index 4199a3f549a5..000000000000 --- a/board/freescale/m54418twr/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M54418TWR - -config SYS_CPU - default "mcf5445x" - -config SYS_BOARD - default "m54418twr" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M54418TWR" - -endif diff --git a/board/freescale/m54418twr/MAINTAINERS b/board/freescale/m54418twr/MAINTAINERS deleted file mode 100644 index f88aed99d657..000000000000 --- a/board/freescale/m54418twr/MAINTAINERS +++ /dev/null @@ -1,11 +0,0 @@ -M54418TWR BOARD -#M: - -S: Maintained -F: board/freescale/m54418twr/ -F: include/configs/M54418TWR.h -F: configs/M54418TWR_defconfig -F: configs/M54418TWR_nand_mii_defconfig -F: configs/M54418TWR_nand_rmii_defconfig -F: configs/M54418TWR_nand_rmii_lowfreq_defconfig -F: configs/M54418TWR_serial_mii_defconfig -F: configs/M54418TWR_serial_rmii_defconfig diff --git a/board/freescale/m54418twr/Makefile b/board/freescale/m54418twr/Makefile deleted file mode 100644 index aa53874ccd84..000000000000 --- a/board/freescale/m54418twr/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# Copyright 2010-2012 Freescale Semiconductor, Inc. -# TsiChung Liew (Tsi-Chung.Liew@freescale.com) - -obj-y = m54418twr.o -extra-y += sbf_dram_init.o - diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c deleted file mode 100644 index ca8993197e3e..000000000000 --- a/board/freescale/m54418twr/m54418twr.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include <common.h> -#include <init.h> -#include <spi.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/immap.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - /* - * need to to: - * Check serial flash size. if 2mb evb, else 8mb demo - */ - puts("Board: "); - puts("Freescale MCF54418 Tower System\n"); - return 0; -}; - -int dram_init(void) -{ - u32 dramsize; - -#if defined(CONFIG_SERIAL_BOOT) - /* - * Serial Boot: The dram is already initialized in start.S - * only require to return DRAM size - */ - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; -#else - sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); - ccm_t *ccm = (ccm_t *)MMAP_CCM; - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - pm_t *pm = (pm_t *) MMAP_PM; - u32 i; - - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; - - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - - out_8(&pm->pmcr0, 0x2E); - out_8(&gpio->mscr_sdram, 1); - - clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF); - setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK); - - out_be32(&sdram->rcrcr, 0x40000000); - out_be32(&sdram->padcr, 0x01030203); - - out_be32(&sdram->cr00, 0x01010101); - out_be32(&sdram->cr01, 0x00000101); - out_be32(&sdram->cr02, 0x01010100); - out_be32(&sdram->cr03, 0x01010000); - out_be32(&sdram->cr04, 0x00010101); - out_be32(&sdram->cr06, 0x00010100); - out_be32(&sdram->cr07, 0x00000001); - out_be32(&sdram->cr08, 0x01000001); - out_be32(&sdram->cr09, 0x00000100); - out_be32(&sdram->cr10, 0x00010001); - out_be32(&sdram->cr11, 0x00000200); - out_be32(&sdram->cr12, 0x01000002); - out_be32(&sdram->cr13, 0x00000000); - out_be32(&sdram->cr14, 0x00000100); - out_be32(&sdram->cr15, 0x02000100); - out_be32(&sdram->cr16, 0x02000407); - out_be32(&sdram->cr17, 0x02030007); - out_be32(&sdram->cr18, 0x02000100); - out_be32(&sdram->cr19, 0x0A030203); - out_be32(&sdram->cr20, 0x00020708); - out_be32(&sdram->cr21, 0x00050008); - out_be32(&sdram->cr22, 0x04030002); - out_be32(&sdram->cr23, 0x00000004); - out_be32(&sdram->cr24, 0x020A0000); - out_be32(&sdram->cr25, 0x0C00000E); - out_be32(&sdram->cr26, 0x00002004); - out_be32(&sdram->cr28, 0x00100010); - out_be32(&sdram->cr29, 0x00100010); - out_be32(&sdram->cr31, 0x07990000); - out_be32(&sdram->cr40, 0x00000000); - out_be32(&sdram->cr41, 0x00C80064); - out_be32(&sdram->cr42, 0x44520002); - out_be32(&sdram->cr43, 0x00C80023); - out_be32(&sdram->cr45, 0x0000C350); - out_be32(&sdram->cr56, 0x04000000); - out_be32(&sdram->cr57, 0x03000304); - out_be32(&sdram->cr58, 0x40040000); - out_be32(&sdram->cr59, 0xC0004004); - out_be32(&sdram->cr60, 0x0642C000); - out_be32(&sdram->cr61, 0x00000642); - asm("tpf"); - - out_be32(&sdram->cr09, 0x01000100); - - udelay(100); -#endif - gd->ram_size = dramsize; - - return 0; -}; - -int testdram(void) -{ - return 0; -} diff --git a/board/freescale/m54418twr/sbf_dram_init.S b/board/freescale/m54418twr/sbf_dram_init.S deleted file mode 100644 index 5a70fb91873c..000000000000 --- a/board/freescale/m54418twr/sbf_dram_init.S +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Board-specific sbf ddr/sdram init. - * - * (C) Copyright 2017 Angelo Dureghello angelo@sysam.it - */ - -.global sbf_dram_init -.text - -sbf_dram_init: - move.l #0xFC04002D, %a1 - move.b #46, (%a1) /* DDR */ - - /* slew settings */ - move.l #0xEC094060, %a1 - move.b #0, (%a1) - - /* use vco instead of cpu*2 clock for ddr clock */ - move.l #0xEC09001A, %a1 - move.w #0xE01D, (%a1) - - /* DDR settings */ - move.l #0xFC0B8180, %a1 - move.l #0x00000000, (%a1) - move.l #0x40000000, (%a1) - - move.l #0xFC0B81AC, %a1 - move.l #0x01030203, (%a1) - - move.l #0xFC0B8000, %a1 - move.l #0x01010101, (%a1)+ /* 0x00 */ - move.l #0x00000101, (%a1)+ /* 0x04 */ - move.l #0x01010100, (%a1)+ /* 0x08 */ - move.l #0x01010000, (%a1)+ /* 0x0C */ - move.l #0x00010101, (%a1)+ /* 0x10 */ - move.l #0xFC0B8018, %a1 - move.l #0x00010100, (%a1)+ /* 0x18 */ - move.l #0x00000001, (%a1)+ /* 0x1C */ - move.l #0x01000001, (%a1)+ /* 0x20 */ - move.l #0x00000100, (%a1)+ /* 0x24 */ - move.l #0x00010001, (%a1)+ /* 0x28 */ - move.l #0x00000200, (%a1)+ /* 0x2C */ - move.l #0x01000002, (%a1)+ /* 0x30 */ - move.l #0x00000000, (%a1)+ /* 0x34 */ - move.l #0x00000100, (%a1)+ /* 0x38 */ - move.l #0x02000100, (%a1)+ /* 0x3C */ - move.l #0x02000407, (%a1)+ /* 0x40 */ - move.l #0x02030007, (%a1)+ /* 0x44 */ - move.l #0x02000100, (%a1)+ /* 0x48 */ - move.l #0x0A030203, (%a1)+ /* 0x4C */ - move.l #0x00020708, (%a1)+ /* 0x50 */ - move.l #0x00050008, (%a1)+ /* 0x54 */ - move.l #0x04030002, (%a1)+ /* 0x58 */ - move.l #0x00000004, (%a1)+ /* 0x5C */ - move.l #0x020A0000, (%a1)+ /* 0x60 */ - move.l #0x0C00000E, (%a1)+ /* 0x64 */ - move.l #0x00002004, (%a1)+ /* 0x68 */ - move.l #0x00000000, (%a1)+ /* 0x6C */ - move.l #0x00100010, (%a1)+ /* 0x70 */ - move.l #0x00100010, (%a1)+ /* 0x74 */ - move.l #0x00000000, (%a1)+ /* 0x78 */ - move.l #0x07990000, (%a1)+ /* 0x7C */ - move.l #0xFC0B80A0, %a1 - move.l #0x00000000, (%a1)+ /* 0xA0 */ - move.l #0x00C80064, (%a1)+ /* 0xA4 */ - move.l #0x44520002, (%a1)+ /* 0xA8 */ - move.l #0x00C80023, (%a1)+ /* 0xAC */ - move.l #0xFC0B80B4, %a1 - move.l #0x0000C350, (%a1) /* 0xB4 */ - move.l #0xFC0B80E0, %a1 - move.l #0x04000000, (%a1)+ /* 0xE0 */ - move.l #0x03000304, (%a1)+ /* 0xE4 */ - move.l #0x40040000, (%a1)+ /* 0xE8 */ - move.l #0xC0004004, (%a1)+ /* 0xEC */ - move.l #0x0642C000, (%a1)+ /* 0xF0 */ - move.l #0x00000642, (%a1)+ /* 0xF4 */ - move.l #0xFC0B8024, %a1 - tpf - move.l #0x01000100, (%a1) /* 0x24 */ - - move.l #0x2000, %d1 - bsr asm_delay - - rts diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig deleted file mode 100644 index 6aa4c2fa2625..000000000000 --- a/configs/M54418TWR_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x47E00000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="M54418TWR" -CONFIG_TARGET_M54418TWR=y -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000" -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="-> " -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_USE_ENV_SPI_CS=y -CONFIG_ENV_SPI_CS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig deleted file mode 100644 index 7273ee02d717..000000000000 --- a/configs/M54418TWR_nand_mii_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x47E00000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_mii" -CONFIG_TARGET_M54418TWR=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000" -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="-> " -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig deleted file mode 100644 index 90df8f4af3c6..000000000000 --- a/configs/M54418TWR_nand_rmii_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x47E00000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii" -CONFIG_TARGET_M54418TWR=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000" -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="-> " -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig deleted file mode 100644 index d7b0f2d9d2ca..000000000000 --- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x47E00000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii_lowfreq" -CONFIG_TARGET_M54418TWR=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000" -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="-> " -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig deleted file mode 100644 index 556bbefd6ba6..000000000000 --- a/configs/M54418TWR_serial_mii_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x47E00000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_mii" -CONFIG_TARGET_M54418TWR=y -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000" -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="-> " -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_USE_ENV_SPI_CS=y -CONFIG_ENV_SPI_CS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig deleted file mode 100644 index 19b1aa6a02ad..000000000000 --- a/configs/M54418TWR_serial_rmii_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x47E00000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_rmii" -CONFIG_TARGET_M54418TWR=y -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000" -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="-> " -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_USE_ENV_SPI_CS=y -CONFIG_ENV_SPI_CS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/doc/README.m54418twr b/doc/README.m54418twr deleted file mode 100644 index 0ca74aa114c4..000000000000 --- a/doc/README.m54418twr +++ /dev/null @@ -1,245 +0,0 @@ -Freescale MCF54418TWR ColdFire Development Board -================================================ - -TsiChung Liew(Tsi-Chung.Liew@freescale.com) -Created Mar 22, 2012 -=========================================== - - -Changed files: -============== - -- board/freescale/m54418twr/m54418twr.c Dram setup -- board/freescale/m54418twr/Makefile Makefile -- board/freescale/m54418twr/config.mk config make -- board/freescale/m54418twr/u-boot.lds Linker description -- board/freescale/m54418twr/sbf_dram_init.S - DDR/SDRAM initialization - -- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code -- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs -- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support -- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock -- arch/m68k/cpu/mcf5445x/Makefile Makefile -- arch/m68k/cpu/mcf5445x/config.mk config make -- arch/m68k/cpu/mcf5445x/start.S start up assembly code - -- doc/README.m54418twr This readme file - -- drivers/net/mcffec.c ColdFire common FEC driver -- drivers/net/mcfmii.c ColdFire common MII driver -- drivers/serial/mcfuart.c ColdFire common UART driver - -- arch/m68k/include/asm/bitops.h Bit operation function export -- arch/m68k/include/asm/byteorder.h Byte order functions -- arch/m68k/include/asm/fec.h FEC structure and definition -- arch/m68k/include/asm/global_data.h Global data structure -- arch/m68k/include/asm/immap.h ColdFire specific header file and driver macros -- arch/m68k/include/asm/immap_5441x.h mcf5441x specific header file -- arch/m68k/include/asm/io.h io functions -- arch/m68k/include/asm/m5441x.h mcf5441x specific header file -- arch/m68k/include/asm/posix_types.h Posix -- arch/m68k/include/asm/processor.h header file -- arch/m68k/include/asm/ptrace.h Exception structure -- arch/m68k/include/asm/rtc.h Realtime clock header file -- arch/m68k/include/asm/string.h String function export -- arch/m68k/include/asm/timer.h Timer structure and definition -- arch/m68k/include/asm/types.h Data types definition -- arch/m68k/include/asm/uart.h Uart structure and definition -- arch/m68k/include/asm/u-boot.h u-boot structure - -- include/configs/M54418TWR.h Board specific configuration file - -- arch/m68k/lib/board.c board init function -- arch/m68k/lib/cache.c -- arch/m68k/lib/interrupts.c Coldfire common interrupt functions -- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) -- arch/m68k/lib/traps.c Exception init code - -1 MCF5441x specific Options/Settings -==================================== -1.1 pre-loader is no longer suppoer in thie coldfire family - -1.2 Configuration settings for M54418TWR Development Board -CONFIG_MCF5441x -- define for all MCF5441x CPUs -CONFIG_M54418 -- define for all Freescale MCF54418 CPUs - -CONFIG_MCFUART -- define to use common CF Uart driver -CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 -CONFIG_BAUDRATE -- define UART baudrate - -CONFIG_MCFFEC -- define to use common CF FEC driver -CONFIG_MII -- enable to use MII driver -CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery -CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer -CONFIG_SYS_FAULT_ECHO_LINK_DOWN -- -CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration -CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration -CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register -CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register -MCFFEC_TOUT_LOOP -- set FEC timeout loop -CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot - -CONFIG_MCFTMR -- define to use DMA timer - -CONFIG_SYS_IMMR -- define for MBAR offset - -CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc - -CONFIG_SYS_MBAR -- define MBAR offset - -CONFIG_MONITOR_IS_IN_RAM -- Not support - -CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM - -CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register -CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register -CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register - -CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base - -2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL -=========================================== -2.1. System memory map: - MRAM: 0x00000000-0x0003FFFF (256KB) - DDR: 0x40000000-0x47FFFFFF (128MB) - SRAM: 0x80000000-0x8000FFFF (64KB) - IP: 0xE0000000-0xFFFFFFFF (512MB) - -3. COMPILATION -============== -3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF version) -from codesourcery.com was used. Download it from: -http://www.codesourcery.com/gnu_toolchains/coldfire/download.html - -3.2 Compilation - export CROSS_COMPILE=cross-compile-prefix - cd u-boot - make distclean - make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock - make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock - make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock - make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input clock - make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock - make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock - make - -4. SCREEN DUMP -============== -4.1 M54418TWR Development board - Boot from NAND flash (NOTE: May not show exactly the same) - -U-Boot 2012.10-00209-g12ae1d8-dirty (Oct 18 2012 - 15:54:54) - -CPU: Freescale MCF54418 (Mask:a3 Version:1) - CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz - INP CLK 50 MHz VCO CLK 500 MHz -Board: Freescale MCF54418 Tower System -SPI: ready -DRAM: 128 MiB -NAND: 256 MiB -In: serial -Out: serial -Err: serial -Net: FEC0, FEC1 --> pri -baudrate=115200 -bootargs=root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(k -ernel)ro,-(jffs2) console=ttyS0,115200 -bootdelay=2 -eth1addr=00:e0:0c:bc:e5:61 -ethact=FEC0 -ethaddr=00:e0:0c:bc:e5:60 -fileaddr=40010000 -filesize=27354 -gatewayip=192.168.1.1 -hostname=M54418TWR -inpclk=50000000 -ipaddr=192.168.1.2 -load=tftp ${loadaddr} ${u-boot}; -loadaddr=0x40010000 -mem=129024k -netdev=eth0 -netmask=255.255.255.0 -prog=nand device 0;nand erase 0 40000;nb_update ${loadaddr} ${filesize};save -serverip=192.168.1.1 -stderr=serial -stdin=serial -stdout=serial -u-boot=u-boot.bin -upd=run load; run prog - -Environment size: 653/131068 bytes --> bdinfo -memstart = 0x40000000 -memsize = 0x08000000 -flashstart = 0x00000000 -flashsize = 0x00000000 -flashoffset = 0x00000000 -sramstart = 0x80000000 -sramsize = 0x00010000 -mbar = 0xFC000000 -cpufreq = 250 MHz -busfreq = 125 MHz -flbfreq = 125 MHz -inpfreq = 50 MHz -vcofreq = 500 MHz -ethaddr = 00:e0:0c:bc:e5:60 -eth1addr = 00:e0:0c:bc:e5:61 -ip_addr = 192.168.1.2 -baudrate = 115200 bps --> help -? - alias for 'help' -base - print or set address offset -bdinfo - print Board Info structure -boot - boot default, i.e., run 'bootcmd' -bootd - boot default, i.e., run 'bootcmd' -bootelf - Boot from an ELF image in memory -bootm - boot application image from memory -bootp - boot image via network using BOOTP/TFTP protocol -bootvx - Boot vxWorks from an ELF image -cmp - memory compare -coninfo - print console devices and information -cp - memory copy -crc32 - checksum calculation -dcache - enable or disable data cache -dhcp - boot image via network using DHCP/TFTP protocol -echo - echo args to console -editenv - edit environment variable -env - environment handling commands -exit - exit script -false - do nothing, unsuccessfully -go - start application at address 'addr' -help - print command description/usage -icache - enable or disable instruction cache -iminfo - print header information for application image -imxtract- extract a part of a multi-image -itest - return true/false on integer compare -loop - infinite loop on address range -md - memory display -mdio - MDIO utility commands -mii - MII utility commands -mm - memory modify (auto-incrementing address) -mtest - simple RAM read/write test -mw - memory write (fill) -nand - NAND sub-system -nb_update- Nand boot update program -nboot - boot from NAND device -nfs - boot image via network using NFS protocol -nm - memory modify (constant address) -ping - send ICMP ECHO_REQUEST to network host -printenv- print environment variables -reginfo - print register information -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -sf - SPI flash sub-system -showvar - print local hushshell variables -sleep - delay execution for some time -source - run script from memory -sspi - SPI utility command -test - minimal test like /bin/sh -tftpboot- boot image via network using TFTP protocol -true - do nothing, successfully -version - print monitor, compiler and linker version diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h deleted file mode 100644 index 5447f84ca163..000000000000 --- a/include/configs/M54418TWR.h +++ /dev/null @@ -1,283 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF54418 TWR board. - * - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M54418TWR_H -#define _M54418TWR_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) -#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } - -#define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*) - -#undef CONFIG_WATCHDOG - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * NAND FLASH - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_JFFS2_NAND -#define CONFIG_NAND_FSL_NFC -#define CONFIG_SYS_NAND_BASE 0xFC0FC000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE -#define CONFIG_SYS_NAND_SELECT_DEVICE -#endif - -/* Network configuration */ -#ifdef CONFIG_MCFFEC -#define CONFIG_MII_INIT 1 -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_SYS_RX_ETH_BUFFER 2 -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_SYS_TX_ETH_BUFFER 2 -#define CONFIG_HAS_ETH1 - -#define CONFIG_ETHPRIME "FEC0" -#define CONFIG_IPADDR 192.168.1.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 - -#define CONFIG_SYS_FEC_BUF_USE_SRAM -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -#ifndef CONFIG_SYS_DISCOVER_PHY -#define FECDUPLEX FULL -#define FECSPEED _100BASET -#define LINKSTATUS 1 -#else -#define LINKSTATUS 0 -#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#endif -#endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#define CONFIG_HOSTNAME "M54418TWR" - -#if defined(CONFIG_CF_SBF) -/* ST Micro serial flash */ -#define CONFIG_SYS_LOAD_ADDR2 0x40010007 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "sbfhdr=sbfhdr.bin\0" \ - "uboot=u-boot.bin\0" \ - "load=tftp ${loadaddr} ${sbfhdr};" \ - "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ - "upd=run load; run prog\0" \ - "prog=sf probe 0:1 1000000 3;" \ - "sf erase 0 40000;" \ - "sf write ${loadaddr} 0 40000;" \ - "save\0" \ - "" -#elif defined(CONFIG_SYS_NAND_BOOT) -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr} ${u-boot};\0" \ - "upd=run load; run prog\0" \ - "prog=nand device 0;" \ - "nand erase 0 40000;" \ - "nb_update ${loadaddr} ${filesize};" \ - "save\0" \ - "" -#else -#define CONFIG_SYS_UBOOT_END 0x3FFFF -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=40010000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off mram" " ;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ - "save\0" \ - "" -#endif - -/* Realtime clock */ -#undef CONFIG_MCFRTC -#define CONFIG_RTC_MCFRRTC -#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 - -/* Timer */ -#define CONFIG_MCFTMR - -/* I2c */ -#undef CONFIG_SYS_FSL_I2C -#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -/* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SPEED 80000 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -/* DSPI and Serial Flash */ -#define CONFIG_CF_DSPI -#define CONFIG_SERIAL_FLASH -#define CONFIG_SYS_SBFHDR_SIZE 0x7 - -/* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK - -#define CONFIG_PRAM 2048 /* 2048 KB */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) - -#define CONFIG_SYS_MBAR 0xFC000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -/* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ - -#define CONFIG_SYS_DRAM_TEST - -#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) -#define CONFIG_SERIAL_BOOT -#endif - -#if defined(CONFIG_SERIAL_BOOT) -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) -#else -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif - -#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) -/* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -/* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ - (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ - -/* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE - -#ifdef CONFIG_SYS_FLASH_CFI - -/* Max size that the board might have */ -#define CONFIG_SYS_FLASH_SIZE 0x1000000 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -/* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 270 -/* "Real" (hardware) sectors protection */ -#define CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } -#else -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 270 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 0 -#endif - -/* - * This is setting for JFFS2 support in u-boot. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ -#ifdef CONFIG_CMD_JFFS2 -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_OFFSET (0x800000) - -#endif - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ - CF_CACR_ICINVA | CF_CACR_EUSP) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ - CF_CACR_DEC | CF_CACR_DDCM_P | \ - CF_CACR_DCINVA) & ~CF_CACR_ICINVA) - -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 12) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -/* - * CS0 - NOR Flash 16MB - * CS1 - Available - * CS2 - Available - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ - - /* Flash */ -#define CONFIG_SYS_CS0_BASE 0x00000000 -#define CONFIG_SYS_CS0_MASK 0x000F0101 -#define CONFIG_SYS_CS0_CTRL 0x00001D60 - -#endif /* _M54418TWR_H */

This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is also the last in family remove the related support as well.

Cc: Angelo Durgehello angelo.dureghello@timesys.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/m68k/Kconfig | 15 - arch/m68k/Makefile | 2 - arch/m68k/cpu/mcf5445x/cpu_init.c | 111 --- arch/m68k/cpu/mcf5445x/dspi.c | 43 -- arch/m68k/cpu/mcf5445x/speed.c | 128 ---- arch/m68k/cpu/mcf5445x/start.S | 7 - arch/m68k/dts/M54451EVB.dts | 33 - arch/m68k/dts/M54451EVB_stmicro.dts | 33 - arch/m68k/dts/Makefile | 2 - arch/m68k/dts/mcf5445x.dtsi | 68 -- arch/m68k/include/asm/cache.h | 4 +- arch/m68k/include/asm/immap.h | 33 - arch/m68k/include/asm/immap_5445x.h | 335 -------- arch/m68k/include/asm/m5445x.h | 888 ---------------------- board/freescale/m54451evb/Kconfig | 15 - board/freescale/m54451evb/MAINTAINERS | 7 - board/freescale/m54451evb/Makefile | 7 - board/freescale/m54451evb/m54451evb.c | 98 --- board/freescale/m54451evb/sbf_dram_init.S | 96 --- configs/M54451EVB_defconfig | 40 - configs/M54451EVB_stmicro_defconfig | 42 - drivers/net/mcffec.c | 6 - include/configs/M54451EVB.h | 242 ------ 23 files changed, 1 insertion(+), 2254 deletions(-) delete mode 100644 arch/m68k/dts/M54451EVB.dts delete mode 100644 arch/m68k/dts/M54451EVB_stmicro.dts delete mode 100644 arch/m68k/dts/mcf5445x.dtsi delete mode 100644 arch/m68k/include/asm/immap_5445x.h delete mode 100644 arch/m68k/include/asm/m5445x.h delete mode 100644 board/freescale/m54451evb/Kconfig delete mode 100644 board/freescale/m54451evb/MAINTAINERS delete mode 100644 board/freescale/m54451evb/Makefile delete mode 100644 board/freescale/m54451evb/m54451evb.c delete mode 100644 board/freescale/m54451evb/sbf_dram_init.S delete mode 100644 configs/M54451EVB_defconfig delete mode 100644 configs/M54451EVB_stmicro_defconfig delete mode 100644 include/configs/M54451EVB.h

diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index c48b8a543d9a..2d4714184149 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -53,12 +53,6 @@ config MCF5441x select DM_SERIAL bool

-config MCF5445x - select OF_CONTROL - select DM - select DM_SERIAL - bool - config MCF5227x select OF_CONTROL select DM @@ -119,10 +113,6 @@ config M54418 bool select MCF5441x

-config M54451 - bool - select MCF5445x - config M52277 bool select MCF5227x @@ -187,10 +177,6 @@ config TARGET_M5373EVB bool "Support M5373EVB" select M5373

-config TARGET_M54451EVB - bool "Support M54451EVB" - select M54451 - config TARGET_AMCORE bool "Support AMCORE" select M5307 @@ -215,7 +201,6 @@ source "board/freescale/m5282evb/Kconfig" source "board/freescale/m53017evb/Kconfig" source "board/freescale/m5329evb/Kconfig" source "board/freescale/m5373evb/Kconfig" -source "board/freescale/m54451evb/Kconfig" source "board/sysam/amcore/Kconfig" source "board/sysam/stmark2/Kconfig"

diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index 86b36e1a40e7..63f18109a577 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -18,13 +18,11 @@ cpuflags-$(CONFIG_M5307) := -mcpu=5307 cpuflags-$(CONFIG_MCF5301x) := -mcpu=53015 -fPIC cpuflags-$(CONFIG_MCF532x) := -mcpu=5329 -fPIC cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC -cpuflags-$(CONFIG_MCF5445x) := -mcpu=54455 -fPIC

PLATFORM_CPPFLAGS += $(cpuflags-y)

ldflags-$(CONFIG_MCF5441x) := --got=single -ldflags-$(CONFIG_MCF5445x) := --got=single

ifneq (,$(findstring -linux-,$(shell $(CC) --version))) ifneq (,$(findstring GOT,$(shell $(LD) --help))) diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 9deab51d07e8..9b3f9f0fe133 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -73,13 +73,6 @@ void cfspi_port_conf(void) { gpio_t *gpio = (gpio_t *)MMAP_GPIO;

-#ifdef CONFIG_MCF5445x - out_8(&gpio->par_dspi, - GPIO_PAR_DSPI_SIN_SIN | - GPIO_PAR_DSPI_SOUT_SOUT | - GPIO_PAR_DSPI_SCK_SCK); -#endif - #ifdef CONFIG_MCF5441x pm_t *pm = (pm_t *)MMAP_PM;

@@ -212,36 +205,6 @@ void cpu_init_f(void) #endif #endif /* CONFIG_MCF5441x */

-#ifdef CONFIG_MCF5445x - scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - - out_be32(&scm1->mpr, 0x77777777); - out_be32(&scm1->pacra, 0); - out_be32(&scm1->pacrb, 0); - out_be32(&scm1->pacrc, 0); - out_be32(&scm1->pacrd, 0); - out_be32(&scm1->pacre, 0); - out_be32(&scm1->pacrf, 0); - out_be32(&scm1->pacrg, 0); - - /* FlexBus */ - out_8(&gpio->par_be, - GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | - GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0); - out_8(&gpio->par_fbctl, - GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | - GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS); - -#ifdef CONFIG_CF_SPI - cfspi_port_conf(); -#endif - -#ifdef CONFIG_SYS_FSL_I2C - out_be16(&gpio->par_feci2c, - GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); -#endif -#endif /* CONFIG_MCF5445x */ - /* FlexBus Chipselect */ init_fbcs();

@@ -365,40 +328,6 @@ void uart_port_conf(int port) GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD); break; #endif -#ifdef CONFIG_MCF5445x - case 0: - clrbits_8(&gpio->par_uart, - GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); - setbits_8(&gpio->par_uart, - GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); - break; - case 1: -#ifdef CONFIG_SYS_UART1_PRI_GPIO - clrbits_8(&gpio->par_uart, - GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); - setbits_8(&gpio->par_uart, - GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); -#elif defined(CONFIG_SYS_UART1_ALT1_GPIO) - clrbits_be16(&gpio->par_ssi, - ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK)); - setbits_be16(&gpio->par_ssi, - GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD); -#endif - break; - case 2: -#if defined(CONFIG_SYS_UART2_ALT1_GPIO) - clrbits_8(&gpio->par_timer, - ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK)); - setbits_8(&gpio->par_timer, - GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD); -#elif defined(CONFIG_SYS_UART2_ALT2_GPIO) - clrbits_8(&gpio->par_timer, - ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK)); - setbits_8(&gpio->par_timer, - GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); -#endif - break; -#endif /* CONFIG_MCF5445x */ } }

@@ -411,46 +340,6 @@ int fecpin_setclear(fec_info_t *info, int setclear) if (fec_get_base_addr(0, &fec0_base)) return -1;

-#ifdef CONFIG_MCF5445x - if (setclear) { -#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY - if (info->iobase == fec0_base) - setbits_be16(&gpio->par_feci2c, - GPIO_PAR_FECI2C_MDC0_MDC0 | - GPIO_PAR_FECI2C_MDIO0_MDIO0); - else - setbits_be16(&gpio->par_feci2c, - GPIO_PAR_FECI2C_MDC1_MDC1 | - GPIO_PAR_FECI2C_MDIO1_MDIO1); -#else - setbits_be16(&gpio->par_feci2c, - GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); -#endif - - if (info->iobase == fec0_base) - setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO); - else - setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA); - } else { - clrbits_be16(&gpio->par_feci2c, - GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); - - if (info->iobase == fec0_base) { -#ifdef CONFIG_SYS_FEC_FULL_MII - setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII); -#else - clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK); -#endif - } else { -#ifdef CONFIG_SYS_FEC_FULL_MII - setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII); -#else - clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK); -#endif - } - } -#endif /* CONFIG_MCF5445x */ - #ifdef CONFIG_MCF5441x if (setclear) { out_8(&gpio->par_fec, 0x03); diff --git a/arch/m68k/cpu/mcf5445x/dspi.c b/arch/m68k/cpu/mcf5445x/dspi.c index b0e2f2cb01ca..456af171a4e2 100644 --- a/arch/m68k/cpu/mcf5445x/dspi.c +++ b/arch/m68k/cpu/mcf5445x/dspi.c @@ -15,30 +15,6 @@ void dspi_chip_select(int cs) { struct gpio *gpio = (struct gpio *)MMAP_GPIO;

-#ifdef CONFIG_MCF5445x - switch (cs) { - case 0: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); - setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); - break; - case 1: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); - setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); - break; - case 2: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); - setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); - break; - case 3: - clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); - setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3); - break; - case 5: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); - setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); - break; - } -#endif #ifdef CONFIG_MCF5441x switch (cs) { case 0: @@ -61,25 +37,6 @@ void dspi_chip_unselect(int cs) { struct gpio *gpio = (struct gpio *)MMAP_GPIO;

-#ifdef CONFIG_MCF5445x - switch (cs) { - case 0: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); - break; - case 1: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); - break; - case 2: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); - break; - case 3: - clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); - break; - case 5: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); - break; - } -#endif #ifdef CONFIG_MCF5441x if (cs == 1) clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index 4809bb49d1cd..eb73da68c6ba 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -42,11 +42,6 @@ void clock_enter_limp(int lpdiv) /* Round divider down to nearest power of two */ for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;

-#ifdef CONFIG_MCF5445x - /* Apply the divider to the system clock */ - clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); -#endif - /* Enable Limp Mode */ setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); } @@ -127,135 +122,12 @@ void setup_5441x_clocks(void) } #endif

-#ifdef CONFIG_MCF5445x -void setup_5445x_clocks(void) -{ - ccm_t *ccm = (ccm_t *)MMAP_CCM; - pll_t *pll = (pll_t *)MMAP_PLL; - int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 }; - int pllmult_pci[] = { 12, 6, 16, 8 }; - int vco = 0, temp, fbtemp, pcrvalue; - int *pPllmult = NULL; - u16 fbpll_mask; -#ifdef CONFIG_PCI - int bPci; -#endif - - u8 bootmode; - - /* To determine PCI is present or not */ - if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || - ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { - pPllmult = &pllmult_pci[0]; - fbpll_mask = 3; /* 11b */ -#ifdef CONFIG_PCI - bPci = 1; -#endif - } else { - pPllmult = &pllmult_nopci[0]; - fbpll_mask = 7; /* 111b */ -#ifdef CONFIG_PCI - gd->pci_clk = 0; - bPci = 0; -#endif - } - -#ifdef CONFIG_M54451EVB - /* No external logic to read the bootmode, hard coded from built */ -#ifdef CONFIG_CF_SBF - bootmode = 3; -#else - bootmode = 2; - - /* default value is 16 mul, set to 20 mul */ - pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000; - out_be32(&pll->pcr, pcrvalue); - while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK) - ; -#endif -#endif - - if (bootmode == 0) { - /* RCON mode */ - vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC; - - if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { - /* invaild range, re-set in PCR */ - int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; - int i, j, bus; - - j = (in_be32(&pll->pcr) & 0xFF000000) >> 24; - for (i = j; i < 0xFF; i++) { - vco = i * CONFIG_SYS_INPUT_CLKSRC; - if (vco >= CLOCK_PLL_FVCO_MIN) { - bus = vco / temp; - if (bus <= CLOCK_PLL_FSYS_MIN - MHZ) - continue; - else - break; - } - } - pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF; - fbtemp = ((i - 1) << 8) | ((i - 1) << 12); - pcrvalue |= ((i << 24) | fbtemp); - - out_be32(&pll->pcr, pcrvalue); - } - gd->arch.vco_clk = vco; /* Vco clock */ - } else if (bootmode == 2) { - /* Normal mode */ - vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; - if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { - /* Default value */ - pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); - pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24; - out_be32(&pll->pcr, pcrvalue); - vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; - } - gd->arch.vco_clk = vco; /* Vco clock */ - } else if (bootmode == 3) { - /* serial mode */ - vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; - gd->arch.vco_clk = vco; /* Vco clock */ - } - - if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { - /* Limp mode */ - } else { - gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */ - - temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; - gd->cpu_clk = vco / temp; /* cpu clock */ - - temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; - gd->bus_clk = vco / temp; /* bus clock */ - - temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1; - gd->arch.flb_clk = vco / temp; /* FlexBus clock */ - -#ifdef CONFIG_PCI - if (bPci) { - temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1; - gd->pci_clk = vco / temp; /* PCI clock */ - } -#endif - } - -#ifdef CONFIG_SYS_I2C_FSL - gd->arch.i2c1_clk = gd->bus_clk; -#endif -} -#endif - /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ int get_clocks(void) { #ifdef CONFIG_MCF5441x setup_5441x_clocks(); #endif -#ifdef CONFIG_MCF5445x - setup_5445x_clocks(); -#endif

#ifdef CONFIG_SYS_FSL_I2C gd->arch.i2c1_clk = gd->bus_clk; diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index 80eb287151e2..7007d78c83fa 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -202,10 +202,6 @@ asm_dspi_init: move.b #0x80, (%a2) #endif

-#ifdef CONFIG_MCF5445x - move.l #0xFC0A4063, %a0 - move.b #0x7F, (%a0) -#endif /* Configure DSPI module */ move.l #0xFC05C000, %a0 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */ @@ -214,9 +210,6 @@ asm_dspi_init: #ifdef CONFIG_MCF5441x move.l #0x3E000016, (%a0) #endif -#ifdef CONFIG_MCF5445x - move.l #0x3E000011, (%a0) -#endif

move.l #0xFC05C034, %a2 /* dtfr */ move.l #0xFC05C03B, %a3 /* drfr */ diff --git a/arch/m68k/dts/M54451EVB.dts b/arch/m68k/dts/M54451EVB.dts deleted file mode 100644 index b81d37a938e4..000000000000 --- a/arch/m68k/dts/M54451EVB.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5445x.dtsi" - -/ { - model = "Freescale M54451EVB"; - compatible = "fsl,M54451EVB"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; diff --git a/arch/m68k/dts/M54451EVB_stmicro.dts b/arch/m68k/dts/M54451EVB_stmicro.dts deleted file mode 100644 index 6645b5806583..000000000000 --- a/arch/m68k/dts/M54451EVB_stmicro.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5445x.dtsi" - -/ { - model = "Freescale M54451EVB_stmicro"; - compatible = "fsl,M54451EVB"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile index 829edb8dbc27..49618e64fef6 100644 --- a/arch/m68k/dts/Makefile +++ b/arch/m68k/dts/Makefile @@ -17,8 +17,6 @@ dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb -dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \ - M54451EVB_stmicro.dtb dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb

diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi deleted file mode 100644 index b7ecc99c098b..000000000000 --- a/arch/m68k/dts/mcf5445x.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/ { - compatible = "fsl,mcf5445x"; - - aliases { - serial0 = &uart0; - spi0 = &dspi0; - fec0 = &fec0; - fec1 = &fec1; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - uart0: uart@fc060000 { - compatible = "fsl,mcf-uart"; - reg = <0xfc060000 0x40>; - status = "disabled"; - }; - - uart1: uart@fc064000 { - compatible = "fsl,mcf-uart"; - reg = <0xfc064000 0x40>; - status = "disabled"; - }; - - uart2: uart@fc068000 { - compatible = "fsl,mcf-uart"; - reg = <0xfc068000 0x40>; - status = "disabled"; - }; - - dspi0: dspi@fc05c000 { - compatible = "fsl,mcf-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfc05c000 0x100>; - spi-max-frequency = <50000000>; - num-cs = <4>; - spi-mode = <0>; - status = "disabled"; - }; - - fec0: ethernet@fc030000 { - compatible = "fsl,mcf-fec"; - reg = <0xfc030000 0x4000>; - mii-base = <0>; - max-speed = <100>; - timeout-loop = <50000>; - status = "disabled"; - }; - - fec1: ethernet@fc034000 { - compatible = "fsl,mcf-fec"; - reg = <0xfc034000 0x4000>; - mii-base = <1>; - max-speed = <100>; - timeout-loop = <50000>; - status = "disabled"; - }; - }; -}; diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index fabec0ae92e3..1c04d6df7c51 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -19,9 +19,7 @@ #define CONFIG_CF_V3 #endif

-#if defined(CONFIG_MCF5445x) -#define CONFIG_CF_V4 -#elif defined(CONFIG_MCF5441x) +#if defined(CONFIG_MCF5441x) #define CONFIG_CF_V4E /* Four Extra ACRn */ #endif

diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 07d9745b1438..81837a7c161b 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -330,39 +330,6 @@

#endif /* CONFIG_M54418 */

-#if defined(CONFIG_M54451) -#include <asm/immap_5445x.h> -#include <asm/m5445x.h> - -#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) - -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) - -#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (6) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) - -#ifdef CONFIG_PCI -#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) -#define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) -#define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE) -#endif -#endif /* CONFIG_M54451 */ - #ifdef CONFIG_M547x #include <asm/immap_547x_8x.h> #include <asm/m547x_8x.h> diff --git a/arch/m68k/include/asm/immap_5445x.h b/arch/m68k/include/asm/immap_5445x.h deleted file mode 100644 index 3111d00d3ee7..000000000000 --- a/arch/m68k/include/asm/immap_5445x.h +++ /dev/null @@ -1,335 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * MCF5445x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#ifndef __IMMAP_5445X__ -#define __IMMAP_5445X__ - -/* Module Base Addresses */ -#define MMAP_SCM1 0xFC000000 -#define MMAP_XBS 0xFC004000 -#define MMAP_FBCS 0xFC008000 -#define MMAP_FEC0 0xFC030000 -#define MMAP_FEC1 0xFC034000 -#define MMAP_RTC 0xFC03C000 -#define MMAP_SCM2 0xFC040000 -#define MMAP_EDMA 0xFC044000 -#define MMAP_INTC0 0xFC048000 -#define MMAP_INTC1 0xFC04C000 -#define MMAP_IACK 0xFC054000 -#define MMAP_I2C 0xFC058000 -#define MMAP_DSPI 0xFC05C000 -#define MMAP_UART0 0xFC060000 -#define MMAP_UART1 0xFC064000 -#define MMAP_UART2 0xFC068000 -#define MMAP_DTMR0 0xFC070000 -#define MMAP_DTMR1 0xFC074000 -#define MMAP_DTMR2 0xFC078000 -#define MMAP_DTMR3 0xFC07C000 -#define MMAP_PIT0 0xFC080000 -#define MMAP_PIT1 0xFC084000 -#define MMAP_PIT2 0xFC088000 -#define MMAP_PIT3 0xFC08C000 -#define MMAP_EPORT 0xFC094000 -#define MMAP_WTM 0xFC098000 -#define MMAP_SBF 0xFC0A0000 -#define MMAP_RCM 0xFC0A0000 -#define MMAP_CCM 0xFC0A0000 -#define MMAP_GPIO 0xFC0A4000 -#define MMAP_PCI 0xFC0A8000 -#define MMAP_PCIARB 0xFC0AC000 -#define MMAP_RNG 0xFC0B4000 -#define MMAP_SDRAM 0xFC0B8000 -#define MMAP_SSI 0xFC0BC000 -#define MMAP_PLL 0xFC0C4000 -#define MMAP_ATA 0x90000000 -#define MMAP_USBHW 0xFC0B0000 -#define MMAP_USBCAPS 0xFC0B0100 -#define MMAP_USBEHCI 0xFC0B0140 -#define MMAP_USBOTG 0xFC0B01A0 - -#include <asm/coldfire/ata.h> -#include <asm/coldfire/crossbar.h> -#include <asm/coldfire/dspi.h> -#include <asm/coldfire/edma.h> -#include <asm/coldfire/eport.h> -#include <asm/coldfire/flexbus.h> -#include <asm/coldfire/intctrl.h> -#include <asm/coldfire/ssi.h> - -/* Watchdog Timer Modules (WTM) */ -typedef struct wtm { - u16 wcr; - u16 wmr; - u16 wcntr; - u16 wsr; -} wtm_t; - -/* Serial Boot Facility (SBF) */ -typedef struct sbf { - u8 resv0[0x18]; - u16 sbfsr; /* Serial Boot Facility Status Register */ - u8 resv1[0x6]; - u16 sbfcr; /* Serial Boot Facility Control Register */ -} sbf_t; - -/* Reset Controller Module (RCM) */ -typedef struct rcm { - u8 rcr; - u8 rsr; -} rcm_t; - -/* Chip Configuration Module (CCM) */ -typedef struct ccm { - u8 ccm_resv0[0x4]; - u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */ - u8 resv1[0x2]; - u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */ - u16 cir; /* Chip Identification Register (Read-only) */ - u8 resv2[0x4]; - u16 misccr; /* Miscellaneous Control Register */ - u16 cdr; /* Clock Divider Register */ - u16 uocsr; /* USB On-the-Go Controller Status Register */ -} ccm_t; - -/* General Purpose I/O Module (GPIO) */ -typedef struct gpio { - u8 podr_fec0h; /* FEC0 High Port Output Data Register */ - u8 podr_fec0l; /* FEC0 Low Port Output Data Register */ - u8 podr_ssi; /* SSI Port Output Data Register */ - u8 podr_fbctl; /* Flexbus Control Port Output Data Register */ - u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */ - u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */ - u8 podr_dma; /* DMA Port Output Data Register */ - u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */ - u8 resv0[0x1]; - u8 podr_uart; /* UART Port Output Data Register */ - u8 podr_dspi; /* DSPI Port Output Data Register */ - u8 podr_timer; /* Timer Port Output Data Register */ - u8 podr_pci; /* PCI Port Output Data Register */ - u8 podr_usb; /* USB Port Output Data Register */ - u8 podr_atah; /* ATA High Port Output Data Register */ - u8 podr_atal; /* ATA Low Port Output Data Register */ - u8 podr_fec1h; /* FEC1 High Port Output Data Register */ - u8 podr_fec1l; /* FEC1 Low Port Output Data Register */ - u8 resv1[0x2]; - u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */ - u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */ - u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */ - u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */ - u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */ - u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */ - u8 pddr_ssi; /* SSI Port Data Direction Register */ - u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */ - u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */ - u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */ - u8 pddr_dma; /* DMA Port Data Direction Register */ - u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */ - u8 resv2[0x1]; - u8 pddr_uart; /* UART Port Data Direction Register */ - u8 pddr_dspi; /* DSPI Port Data Direction Register */ - u8 pddr_timer; /* Timer Port Data Direction Register */ - u8 pddr_pci; /* PCI Port Data Direction Register */ - u8 pddr_usb; /* USB Port Data Direction Register */ - u8 pddr_atah; /* ATA High Port Data Direction Register */ - u8 pddr_atal; /* ATA Low Port Data Direction Register */ - u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */ - u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */ - u8 resv3[0x2]; - u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */ - u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */ - u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */ - u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */ - u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */ - u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */ - u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */ - u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */ - u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */ - u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */ - u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */ - u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */ - u8 resv4[0x1]; - u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */ - u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */ - u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */ - u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */ - u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */ - u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */ - u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */ - u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */ - u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */ - u8 resv5[0x2]; - u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */ - u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */ - u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */ - u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */ - u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */ - u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */ - u8 pclrr_ssi; /* SSI Port Clear Output Data Register */ - u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */ - u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */ - u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */ - u8 pclrr_dma; /* DMA Port Clear Output Data Register */ - u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */ - u8 resv6[0x1]; - u8 pclrr_uart; /* UART Port Clear Output Data Register */ - u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */ - u8 pclrr_timer; /* Timer Port Clear Output Data Register */ - u8 pclrr_pci; /* PCI Port Clear Output Data Register */ - u8 pclrr_usb; /* USB Port Clear Output Data Register */ - u8 pclrr_atah; /* ATA High Port Clear Output Data Register */ - u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */ - u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */ - u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */ - u8 resv7[0x2]; - u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */ - u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */ - u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */ - u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */ - u8 par_fec; /* FEC Pin Assignment Register */ - u8 par_dma; /* DMA Pin Assignment Register */ - u8 par_fbctl; /* Flexbus Control Pin Assignment Register */ - u8 par_dspi; /* DSPI Pin Assignment Register */ - u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */ - u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */ - u8 par_timer; /* Time Pin Assignment Register */ - u8 par_usb; /* USB Pin Assignment Register */ - u8 resv8[0x1]; - u8 par_uart; /* UART Pin Assignment Register */ - u16 par_feci2c; /* FEC / I2C Pin Assignment Register */ - u16 par_ssi; /* SSI Pin Assignment Register */ - u16 par_ata; /* ATA Pin Assignment Register */ - u8 par_irq; /* IRQ Pin Assignment Register */ - u8 resv9[0x1]; - u16 par_pci; /* PCI Pin Assignment Register */ - u8 mscr_sdram; /* SDRAM Mode Select Control Register */ - u8 mscr_pci; /* PCI Mode Select Control Register */ - u8 resv10[0x2]; - u8 dscr_i2c; /* I2C Drive Strength Control Register */ - u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */ - u8 dscr_fec; /* FEC Drive Strength Control Register */ - u8 dscr_uart; /* UART Drive Strength Control Register */ - u8 dscr_dspi; /* DSPI Drive Strength Control Register */ - u8 dscr_timer; /* TIMER Drive Strength Control Register */ - u8 dscr_ssi; /* SSI Drive Strength Control Register */ - u8 dscr_dma; /* DMA Drive Strength Control Register */ - u8 dscr_debug; /* DEBUG Drive Strength Control Register */ - u8 dscr_reset; /* RESET Drive Strength Control Register */ - u8 dscr_irq; /* IRQ Drive Strength Control Register */ - u8 dscr_usb; /* USB Drive Strength Control Register */ - u8 dscr_ata; /* ATA Drive Strength Control Register */ -} gpio_t; - -/* SDRAM Controller (SDRAMC) */ -typedef struct sdramc { - u32 sdmr; /* SDRAM Mode/Extended Mode Register */ - u32 sdcr; /* SDRAM Control Register */ - u32 sdcfg1; /* SDRAM Configuration Register 1 */ - u32 sdcfg2; /* SDRAM Chip Select Register */ - u8 resv0[0x100]; - u32 sdcs0; /* SDRAM Mode/Extended Mode Register */ - u32 sdcs1; /* SDRAM Mode/Extended Mode Register */ -} sdramc_t; - -/* Phase Locked Loop (PLL) */ -typedef struct pll { - u32 pcr; /* PLL Control Register */ - u32 psr; /* PLL Status Register */ -} pll_t; - -typedef struct pci { - u32 idr; /* 0x00 Device Id / Vendor Id Register */ - u32 scr; /* 0x04 Status / command Register */ - u32 ccrir; /* 0x08 Class Code / Revision Id Register */ - u32 cr1; /* 0x0c Configuration 1 Register */ - u32 bar0; /* 0x10 Base address register 0 Register */ - u32 bar1; /* 0x14 Base address register 1 Register */ - u32 bar2; /* 0x18 Base address register 2 Register */ - u32 bar3; /* 0x1c Base address register 3 Register */ - u32 bar4; /* 0x20 Base address register 4 Register */ - u32 bar5; /* 0x24 Base address register 5 Register */ - u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */ - u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */ - u32 erbar; /* 0x30 Expansion ROM Base Address Register */ - u32 cpr; /* 0x34 Capabilities Pointer Register */ - u32 rsvd1; /* 0x38 */ - u32 cr2; /* 0x3c Configuration Register 2 */ - u32 rsvd2[8]; /* 0x40 - 0x5f */ - - /* General control / status registers */ - u32 gscr; /* 0x60 Global Status / Control Register */ - u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */ - u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */ - u32 tcr1; /* 0x6c Target Control 1 Register */ - u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */ - u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */ - u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */ - u32 rsvd3; /* 0x7c */ - u32 iwcr; /* 0x80 Initiator Window Configuration Register */ - u32 icr; /* 0x84 Initiator Control Register */ - u32 isr; /* 0x88 Initiator Status Register */ - u32 tcr2; /* 0x8c Target Control 2 Register */ - u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */ - u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */ - u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */ - u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */ - u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */ - u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */ - u32 intr; /* 0xa8 Interrupt Register */ - u32 rsvd4[19]; /* 0xac - 0xf7 */ - u32 car; /* 0xf8 Configuration Address Register */ -} pci_t; - -typedef struct pci_arbiter { - /* Pci Arbiter Registers */ - union { - u32 acr; /* Arbiter Control Register */ - u32 asr; /* Arbiter Status Register */ - }; -} pciarb_t; - -/* Register read/write struct */ -typedef struct scm1 { - u32 mpr; /* 0x00 Master Privilege Register */ - u32 rsvd1[7]; - u32 pacra; /* 0x20 Peripheral Access Control Register A */ - u32 pacrb; /* 0x24 Peripheral Access Control Register B */ - u32 pacrc; /* 0x28 Peripheral Access Control Register C */ - u32 pacrd; /* 0x2C Peripheral Access Control Register D */ - u32 rsvd2[4]; - u32 pacre; /* 0x40 Peripheral Access Control Register E */ - u32 pacrf; /* 0x44 Peripheral Access Control Register F */ - u32 pacrg; /* 0x48 Peripheral Access Control Register G */ -} scm1_t; - -typedef struct scm2 { - u8 rsvd1[19]; /* 0x00 - 0x12 */ - u8 wcr; /* 0x13 */ - u16 rsvd2; /* 0x14 - 0x15 */ - u16 cwcr; /* 0x16 */ - u8 rsvd3[3]; /* 0x18 - 0x1A */ - u8 cwsr; /* 0x1B */ - u8 rsvd4[3]; /* 0x1C - 0x1E */ - u8 scmisr; /* 0x1F */ - u32 rsvd5; /* 0x20 - 0x23 */ - u8 bcr; /* 0x24 */ - u8 rsvd6[74]; /* 0x25 - 0x6F */ - u32 cfadr; /* 0x70 */ - u8 rsvd7; /* 0x74 */ - u8 cfier; /* 0x75 */ - u8 cfloc; /* 0x76 */ - u8 cfatr; /* 0x77 */ - u32 rsvd8; /* 0x78 - 0x7B */ - u32 cfdtr; /* 0x7C */ -} scm2_t; - -typedef struct rtcex { - u32 rsvd1[3]; - u32 gocu; - u32 gocl; -} rtcex_t; -#endif /* __IMMAP_5445X__ */ diff --git a/arch/m68k/include/asm/m5445x.h b/arch/m68k/include/asm/m5445x.h deleted file mode 100644 index 498c2255f662..000000000000 --- a/arch/m68k/include/asm/m5445x.h +++ /dev/null @@ -1,888 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * MCF5445x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#ifndef __MCF5445X__ -#define __MCF5445X__ - -/********************************************************************* -* Interrupt Controller (INTC) -*********************************************************************/ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT2 (2) -#define INT0_LO_EPORT3 (3) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT5 (5) -#define INT0_LO_EPORT6 (6) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_EDMA_00 (8) -#define INT0_LO_EDMA_01 (9) -#define INT0_LO_EDMA_02 (10) -#define INT0_LO_EDMA_03 (11) -#define INT0_LO_EDMA_04 (12) -#define INT0_LO_EDMA_05 (13) -#define INT0_LO_EDMA_06 (14) -#define INT0_LO_EDMA_07 (15) -#define INT0_LO_EDMA_08 (16) -#define INT0_LO_EDMA_09 (17) -#define INT0_LO_EDMA_10 (18) -#define INT0_LO_EDMA_11 (19) -#define INT0_LO_EDMA_12 (20) -#define INT0_LO_EDMA_13 (21) -#define INT0_LO_EDMA_14 (22) -#define INT0_LO_EDMA_15 (23) -#define INT0_LO_EDMA_ERR (24) -#define INT0_LO_SCM (25) -#define INT0_LO_UART0 (26) -#define INT0_LO_UART1 (27) -#define INT0_LO_UART2 (28) -#define INT0_LO_RSVD1 (29) -#define INT0_LO_I2C (30) -#define INT0_LO_QSPI (31) -#define INT0_HI_DTMR0 (32) -#define INT0_HI_DTMR1 (33) -#define INT0_HI_DTMR2 (34) -#define INT0_HI_DTMR3 (35) -#define INT0_HI_FEC0_TXF (36) -#define INT0_HI_FEC0_TXB (37) -#define INT0_HI_FEC0_UN (38) -#define INT0_HI_FEC0_RL (39) -#define INT0_HI_FEC0_RXF (40) -#define INT0_HI_FEC0_RXB (41) -#define INT0_HI_FEC0_MII (42) -#define INT0_HI_FEC0_LC (43) -#define INT0_HI_FEC0_HBERR (44) -#define INT0_HI_FEC0_GRA (45) -#define INT0_HI_FEC0_EBERR (46) -#define INT0_HI_FEC0_BABT (47) -#define INT0_HI_FEC0_BABR (48) -#define INT0_HI_FEC1_TXF (49) -#define INT0_HI_FEC1_TXB (50) -#define INT0_HI_FEC1_UN (51) -#define INT0_HI_FEC1_RL (52) -#define INT0_HI_FEC1_RXF (53) -#define INT0_HI_FEC1_RXB (54) -#define INT0_HI_FEC1_MII (55) -#define INT0_HI_FEC1_LC (56) -#define INT0_HI_FEC1_HBERR (57) -#define INT0_HI_FEC1_GRA (58) -#define INT0_HI_FEC1_EBERR (59) -#define INT0_HI_FEC1_BABT (60) -#define INT0_HI_FEC1_BABR (61) -#define INT0_HI_SCMIR (62) -#define INT0_HI_RTC_ISR (63) - -#define INT1_HI_DSPI_EOQF (33) -#define INT1_HI_DSPI_TFFF (34) -#define INT1_HI_DSPI_TCF (35) -#define INT1_HI_DSPI_TFUF (36) -#define INT1_HI_DSPI_RFDF (37) -#define INT1_HI_DSPI_RFOF (38) -#define INT1_HI_DSPI_RFOF_TFUF (39) -#define INT1_HI_RNG_EI (40) -#define INT1_HI_PIT0_PIF (43) -#define INT1_HI_PIT1_PIF (44) -#define INT1_HI_PIT2_PIF (45) -#define INT1_HI_PIT3_PIF (46) -#define INT1_HI_USBOTG_USBSTS (47) -#define INT1_HI_SSI_ISR (49) -#define INT1_HI_CCM_UOCSR (53) -#define INT1_HI_ATA_ISR (54) -#define INT1_HI_PCI_SCR (55) -#define INT1_HI_PCI_ASR (56) -#define INT1_HI_PLL_LOCKS (57) - -/********************************************************************* -* Watchdog Timer Modules (WTM) -*********************************************************************/ - -/* Bit definitions and macros for WCR */ -#define WTM_WCR_EN (0x0001) -#define WTM_WCR_HALTED (0x0002) -#define WTM_WCR_DOZE (0x0004) -#define WTM_WCR_WAIT (0x0008) - -/********************************************************************* -* Serial Boot Facility (SBF) -*********************************************************************/ - -/* Bit definitions and macros for SBFCR */ -#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */ -#define SBF_SBFCR_FR (0x0010) /* Fast read */ - -/********************************************************************* -* Reset Controller Module (RCM) -*********************************************************************/ - -/* Bit definitions and macros for RCR */ -#define RCM_RCR_FRCRSTOUT (0x40) -#define RCM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for RSR */ -#define RCM_RSR_LOL (0x01) -#define RCM_RSR_WDR_CORE (0x02) -#define RCM_RSR_EXT (0x04) -#define RCM_RSR_POR (0x08) -#define RCM_RSR_SOFT (0x20) - -/********************************************************************* -* Chip Configuration Module (CCM) -*********************************************************************/ - -/* Bit definitions and macros for CCR_360 */ -#define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */ -#define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ -#define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */ -#define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */ -#define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ -#define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */ -#define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */ -#define CCM_CCR_360_FBCONFIG_MASK (0x00E0) -#define CCM_CCR_360_PLLMULT2_MASK (0x0003) -#define CCM_CCR_360_PLLMULT3_MASK (0x0007) -#define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000) -#define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020) -#define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040) -#define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060) -#define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080) -#define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0) -#define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0) -#define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0) -#define CCM_CCR_360_PLLMULT2_12X (0x0000) -#define CCM_CCR_360_PLLMULT2_6X (0x0001) -#define CCM_CCR_360_PLLMULT2_16X (0x0002) -#define CCM_CCR_360_PLLMULT2_8X (0x0003) -#define CCM_CCR_360_PLLMULT3_20X (0x0000) -#define CCM_CCR_360_PLLMULT3_10X (0x0001) -#define CCM_CCR_360_PLLMULT3_24X (0x0002) -#define CCM_CCR_360_PLLMULT3_18X (0x0003) -#define CCM_CCR_360_PLLMULT3_12X (0x0004) -#define CCM_CCR_360_PLLMULT3_6X (0x0005) -#define CCM_CCR_360_PLLMULT3_16X (0x0006) -#define CCM_CCR_360_PLLMULT3_8X (0x0007) - -/* Bit definitions and macros for CCR_256 */ -#define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */ -#define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */ -#define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */ -#define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ -#define CCM_CCR_256_FBCONFIG_MASK (0x00E0) -#define CCM_CCR_256_FBCONFIG_NM_32 (0x0000) -#define CCM_CCR_256_FBCONFIG_NM_8 (0x0020) -#define CCM_CCR_256_FBCONFIG_NM_16 (0x0040) -#define CCM_CCR_256_FBCONFIG_M_32 (0x0080) -#define CCM_CCR_256_FBCONFIG_M_8 (0x00A0) -#define CCM_CCR_256_FBCONFIG_M_16 (0x00C0) -#define CCM_CCR_256_PLLMULT3_MASK (0x0007) -#define CCM_CCR_256_PLLMULT3_20X (0x0000) -#define CCM_CCR_256_PLLMULT3_10X (0x0001) -#define CCM_CCR_256_PLLMULT3_24X (0x0002) -#define CCM_CCR_256_PLLMULT3_18X (0x0003) -#define CCM_CCR_256_PLLMULT3_12X (0x0004) -#define CCM_CCR_256_PLLMULT3_6X (0x0005) -#define CCM_CCR_256_PLLMULT3_16X (0x0006) -#define CCM_CCR_256_PLLMULT3_8X (0x0007) - -/* Bit definitions and macros for RCON_360 */ -#define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ -#define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ -#define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */ -#define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */ -#define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ - -/* Bit definitions and macros for RCON_256 */ -#define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */ -#define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */ -#define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */ -#define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ - -/* Bit definitions and macros for CIR */ -#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ -#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ -#define CCM_CIR_PIN_MASK (0xFFC0) -#define CCM_CIR_PRN_MASK (0x003F) -#define CCM_CIR_PIN_MCF54450 (0x4F<<6) -#define CCM_CIR_PIN_MCF54451 (0x4D<<6) -#define CCM_CIR_PIN_MCF54452 (0x4B<<6) -#define CCM_CIR_PIN_MCF54453 (0x49<<6) -#define CCM_CIR_PIN_MCF54454 (0x4A<<6) -#define CCM_CIR_PIN_MCF54455 (0x48<<6) - -/* Bit definitions and macros for MISCCR */ -#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ -#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */ -#define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */ -#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ -#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ -#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ -#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ -#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */ -#define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */ -#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ -#define CCM_MISCCR_BMT_65536 (0) -#define CCM_MISCCR_BMT_32768 (1) -#define CCM_MISCCR_BMT_16384 (2) -#define CCM_MISCCR_BMT_8192 (3) -#define CCM_MISCCR_BMT_4096 (4) -#define CCM_MISCCR_BMT_2048 (5) -#define CCM_MISCCR_BMT_1024 (6) -#define CCM_MISCCR_BMT_512 (7) -#define CCM_MISCCR_SSIPUS_UP (1) -#define CCM_MISCCR_SSIPUS_DOWN (0) -#define CCM_MISCCR_TIMDMA_TIM (1) -#define CCM_MISCCR_TIMDMA_SSI (0) -#define CCM_MISCCR_SSISRC_CLKIN (0) -#define CCM_MISCCR_SSISRC_PLL (1) -#define CCM_MISCCR_USBOC_ACTHI (0) -#define CCM_MISCCR_USBOV_ACTLO (1) -#define CCM_MISCCR_USBSRC_CLKIN (0) -#define CCM_MISCCR_USBSRC_PLL (1) - -/* Bit definitions and macros for CDR */ -#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */ -#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */ - -/* Bit definitions and macros for UOCSR */ -#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */ -#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */ -#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ -#define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */ -#define CCM_UOCSR_SEND (0x0010) /* Session end */ -#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ -#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ -#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ -#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */ -#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */ -#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */ -#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */ -#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */ - -/********************************************************************* -* General Purpose I/O Module (GPIO) -*********************************************************************/ - -/* Bit definitions and macros for PAR_FEC */ -#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) -#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) -#define GPIO_PAR_FEC_FEC1_UNMASK (0x8F) -#define GPIO_PAR_FEC_FEC1_MII (0x70) -#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) -#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) -#define GPIO_PAR_FEC_FEC1_ATA (0x10) -#define GPIO_PAR_FEC_FEC1_GPIO (0x00) -#define GPIO_PAR_FEC_FEC0_UNMASK (0xF8) -#define GPIO_PAR_FEC_FEC0_MII (0x07) -#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) -#define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) -#define GPIO_PAR_FEC_FEC0_ULPI (0x01) -#define GPIO_PAR_FEC_FEC0_GPIO (0x00) - -/* Bit definitions and macros for PAR_DMA */ -#define GPIO_PAR_DMA_DREQ0 (0x01) -#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) -#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) -#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) -#define GPIO_PAR_DMA_DACK1_UNMASK (0x3F) -#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0) -#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) -#define GPIO_PAR_DMA_DACK1_GPIO (0x00) -#define GPIO_PAR_DMA_DREQ1_UNMASK (0xCF) -#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) -#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) -#define GPIO_PAR_DMA_DREQ1_GPIO (0x00) -#define GPIO_PAR_DMA_DACK0_UNMASK (0xF3) -#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) -#define GPIO_PAR_DMA_DACK0_PCS3 (0x08) -#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) -#define GPIO_PAR_DMA_DACK0_GPIO (0x00) -#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) -#define GPIO_PAR_DMA_DREQ0_GPIO (0x00) - -/* Bit definitions and macros for PAR_FBCTL */ -#define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) -#define GPIO_PAR_FBCTL_RW (0x20) -#define GPIO_PAR_FBCTL_TA (0x40) -#define GPIO_PAR_FBCTL_OE (0x80) -#define GPIO_PAR_FBCTL_OE_OE (0x80) -#define GPIO_PAR_FBCTL_OE_GPIO (0x00) -#define GPIO_PAR_FBCTL_TA_TA (0x40) -#define GPIO_PAR_FBCTL_TA_GPIO (0x00) -#define GPIO_PAR_FBCTL_RW_RW (0x20) -#define GPIO_PAR_FBCTL_RW_GPIO (0x00) -#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) -#define GPIO_PAR_FBCTL_TS_TS (0x18) -#define GPIO_PAR_FBCTL_TS_ALE (0x10) -#define GPIO_PAR_FBCTL_TS_TBST (0x08) -#define GPIO_PAR_FBCTL_TS_GPIO (0x80) - -/* Bit definitions and macros for PAR_DSPI */ -#define GPIO_PAR_DSPI_SCK (0x01) -#define GPIO_PAR_DSPI_SOUT (0x02) -#define GPIO_PAR_DSPI_SIN (0x04) -#define GPIO_PAR_DSPI_PCS0 (0x08) -#define GPIO_PAR_DSPI_PCS1 (0x10) -#define GPIO_PAR_DSPI_PCS2 (0x20) -#define GPIO_PAR_DSPI_PCS5 (0x40) -#define GPIO_PAR_DSPI_PCS5_PCS5 (0x40) -#define GPIO_PAR_DSPI_PCS5_GPIO (0x00) -#define GPIO_PAR_DSPI_PCS2_PCS2 (0x20) -#define GPIO_PAR_DSPI_PCS2_GPIO (0x00) -#define GPIO_PAR_DSPI_PCS1_PCS1 (0x10) -#define GPIO_PAR_DSPI_PCS1_GPIO (0x00) -#define GPIO_PAR_DSPI_PCS0_PCS0 (0x08) -#define GPIO_PAR_DSPI_PCS0_GPIO (0x00) -#define GPIO_PAR_DSPI_SIN_SIN (0x04) -#define GPIO_PAR_DSPI_SIN_GPIO (0x00) -#define GPIO_PAR_DSPI_SOUT_SOUT (0x02) -#define GPIO_PAR_DSPI_SOUT_GPIO (0x00) -#define GPIO_PAR_DSPI_SCK_SCK (0x01) -#define GPIO_PAR_DSPI_SCK_GPIO (0x00) - -/* Bit definitions and macros for PAR_BE */ -#define GPIO_PAR_BE_BS0 (0x01) -#define GPIO_PAR_BE_BS1 (0x04) -#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) -#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) -#define GPIO_PAR_BE_BE3_UNMASK (0x3F) -#define GPIO_PAR_BE_BE3_BE3 (0xC0) -#define GPIO_PAR_BE_BE3_TSIZ1 (0x80) -#define GPIO_PAR_BE_BE3_GPIO (0x00) -#define GPIO_PAR_BE_BE2_UNMASK (0xCF) -#define GPIO_PAR_BE_BE2_BE2 (0x30) -#define GPIO_PAR_BE_BE2_TSIZ0 (0x20) -#define GPIO_PAR_BE_BE2_GPIO (0x00) -#define GPIO_PAR_BE_BE1_BE1 (0x04) -#define GPIO_PAR_BE_BE1_GPIO (0x00) -#define GPIO_PAR_BE_BE0_BE0 (0x01) -#define GPIO_PAR_BE_BE0_GPIO (0x00) - -/* Bit definitions and macros for PAR_CS */ -#define GPIO_PAR_CS_CS1 (0x02) -#define GPIO_PAR_CS_CS2 (0x04) -#define GPIO_PAR_CS_CS3 (0x08) -#define GPIO_PAR_CS_CS3_CS3 (0x08) -#define GPIO_PAR_CS_CS3_GPIO (0x00) -#define GPIO_PAR_CS_CS2_CS2 (0x04) -#define GPIO_PAR_CS_CS2_GPIO (0x00) -#define GPIO_PAR_CS_CS1_CS1 (0x02) -#define GPIO_PAR_CS_CS1_GPIO (0x00) - -/* Bit definitions and macros for PAR_TIMER */ -#define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) -#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) -#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) -#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) -#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) -#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) -#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) -#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40) -#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) -#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) -#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) -#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10) -#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) -#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) -#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) -#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04) -#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) -#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) -#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) -#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01) -#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) - -/* Bit definitions and macros for PAR_USB */ -#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) -#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) -#define GPIO_PAR_USB_VBUSEN_UNMASK (0xF3) -#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) -#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) -#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) -#define GPIO_PAR_USB_VBUSEN_GPIO (0x00) -#define GPIO_PAR_USB_VBUSOC_UNMASK (0xFC) -#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) -#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) -#define GPIO_PAR_USB_VBUSOC_GPIO (0x00) - -/* Bit definitions and macros for PAR_UART */ -#define GPIO_PAR_UART_U0TXD (0x01) -#define GPIO_PAR_UART_U0RXD (0x02) -#define GPIO_PAR_UART_U0RTS (0x04) -#define GPIO_PAR_UART_U0CTS (0x08) -#define GPIO_PAR_UART_U1TXD (0x10) -#define GPIO_PAR_UART_U1RXD (0x20) -#define GPIO_PAR_UART_U1RTS (0x40) -#define GPIO_PAR_UART_U1CTS (0x80) -#define GPIO_PAR_UART_U1CTS_U1CTS (0x80) -#define GPIO_PAR_UART_U1CTS_GPIO (0x00) -#define GPIO_PAR_UART_U1RTS_U1RTS (0x40) -#define GPIO_PAR_UART_U1RTS_GPIO (0x00) -#define GPIO_PAR_UART_U1RXD_U1RXD (0x20) -#define GPIO_PAR_UART_U1RXD_GPIO (0x00) -#define GPIO_PAR_UART_U1TXD_U1TXD (0x10) -#define GPIO_PAR_UART_U1TXD_GPIO (0x00) -#define GPIO_PAR_UART_U0CTS_U0CTS (0x08) -#define GPIO_PAR_UART_U0CTS_GPIO (0x00) -#define GPIO_PAR_UART_U0RTS_U0RTS (0x04) -#define GPIO_PAR_UART_U0RTS_GPIO (0x00) -#define GPIO_PAR_UART_U0RXD_U0RXD (0x02) -#define GPIO_PAR_UART_U0RXD_GPIO (0x00) -#define GPIO_PAR_UART_U0TXD_U0TXD (0x01) -#define GPIO_PAR_UART_U0TXD_GPIO (0x00) - -/* Bit definitions and macros for PAR_FECI2C */ -#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) -#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) -#define GPIO_PAR_FECI2C_MDIO0 (0x0010) -#define GPIO_PAR_FECI2C_MDC0 (0x0040) -#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) -#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) -#define GPIO_PAR_FECI2C_MDC1_UNMASK (0xF3FF) -#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) -#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) -#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) -#define GPIO_PAR_FECI2C_MDIO1_UNMASK (0xFCFF) -#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) -#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) -#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) -#define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040) -#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) -#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) -#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) -#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFFF3) -#define GPIO_PAR_FECI2C_SCL_SCL (0x000C) -#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) -#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000) -#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFFFC) -#define GPIO_PAR_FECI2C_SDA_SDA (0x0003) -#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) -#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000) - -/* Bit definitions and macros for PAR_SSI */ -#define GPIO_PAR_SSI_MCLK (0x0001) -#define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) -#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) -#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) -#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) -#define GPIO_PAR_SSI_BCLK_UNMASK (0xFCFF) -#define GPIO_PAR_SSI_BCLK_BCLK (0x0300) -#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200) -#define GPIO_PAR_SSI_BCLK_GPIO (0x0000) -#define GPIO_PAR_SSI_FS_UNMASK (0xFF3F) -#define GPIO_PAR_SSI_FS_FS (0x00C0) -#define GPIO_PAR_SSI_FS_U1RTS (0x0080) -#define GPIO_PAR_SSI_FS_GPIO (0x0000) -#define GPIO_PAR_SSI_SRXD_UNMASK (0xFFCF) -#define GPIO_PAR_SSI_SRXD_SRXD (0x0030) -#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020) -#define GPIO_PAR_SSI_SRXD_GPIO (0x0000) -#define GPIO_PAR_SSI_STXD_UNMASK (0xFFF3) -#define GPIO_PAR_SSI_STXD_STXD (0x000C) -#define GPIO_PAR_SSI_STXD_U1TXD (0x0008) -#define GPIO_PAR_SSI_STXD_GPIO (0x0000) -#define GPIO_PAR_SSI_MCLK_MCLK (0x0001) -#define GPIO_PAR_SSI_MCLK_GPIO (0x0000) - -/* Bit definitions and macros for PAR_ATA */ -#define GPIO_PAR_ATA_IORDY (0x0001) -#define GPIO_PAR_ATA_DMARQ (0x0002) -#define GPIO_PAR_ATA_RESET (0x0004) -#define GPIO_PAR_ATA_DA0 (0x0020) -#define GPIO_PAR_ATA_DA1 (0x0040) -#define GPIO_PAR_ATA_DA2 (0x0080) -#define GPIO_PAR_ATA_CS0 (0x0100) -#define GPIO_PAR_ATA_CS1 (0x0200) -#define GPIO_PAR_ATA_BUFEN (0x0400) -#define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400) -#define GPIO_PAR_ATA_BUFEN_GPIO (0x0000) -#define GPIO_PAR_ATA_CS1_CS1 (0x0200) -#define GPIO_PAR_ATA_CS1_GPIO (0x0000) -#define GPIO_PAR_ATA_CS0_CS0 (0x0100) -#define GPIO_PAR_ATA_CS0_GPIO (0x0000) -#define GPIO_PAR_ATA_DA2_DA2 (0x0080) -#define GPIO_PAR_ATA_DA2_GPIO (0x0000) -#define GPIO_PAR_ATA_DA1_DA1 (0x0040) -#define GPIO_PAR_ATA_DA1_GPIO (0x0000) -#define GPIO_PAR_ATA_DA0_DA0 (0x0020) -#define GPIO_PAR_ATA_DA0_GPIO (0x0000) -#define GPIO_PAR_ATA_RESET_RESET (0x0004) -#define GPIO_PAR_ATA_RESET_GPIO (0x0000) -#define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002) -#define GPIO_PAR_ATA_DMARQ_GPIO (0x0000) -#define GPIO_PAR_ATA_IORDY_IORDY (0x0001) -#define GPIO_PAR_ATA_IORDY_GPIO (0x0000) - -/* Bit definitions and macros for PAR_IRQ */ -#define GPIO_PAR_IRQ_IRQ1 (0x02) -#define GPIO_PAR_IRQ_IRQ4 (0x10) -#define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10) -#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) -#define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02) -#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) - -/* Bit definitions and macros for PAR_PCI */ -#define GPIO_PAR_PCI_REQ0 (0x0001) -#define GPIO_PAR_PCI_REQ1 (0x0004) -#define GPIO_PAR_PCI_REQ2 (0x0010) -#define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) -#define GPIO_PAR_PCI_GNT0 (0x0100) -#define GPIO_PAR_PCI_GNT1 (0x0400) -#define GPIO_PAR_PCI_GNT2 (0x1000) -#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) -#define GPIO_PAR_PCI_GNT3_UNMASK (0x3FFF) -#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000) -#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) -#define GPIO_PAR_PCI_GNT3_GPIO (0x0000) -#define GPIO_PAR_PCI_GNT2_GNT2 (0x1000) -#define GPIO_PAR_PCI_GNT2_GPIO (0x0000) -#define GPIO_PAR_PCI_GNT1_GNT1 (0x0400) -#define GPIO_PAR_PCI_GNT1_GPIO (0x0000) -#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100) -#define GPIO_PAR_PCI_GNT0_GPIO (0x0000) -#define GPIO_PAR_PCI_REQ3_UNMASK (0xFF3F) -#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) -#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) -#define GPIO_PAR_PCI_REQ3_GPIO (0x0000) -#define GPIO_PAR_PCI_REQ2_REQ2 (0x0010) -#define GPIO_PAR_PCI_REQ2_GPIO (0x0000) -#define GPIO_PAR_PCI_REQ1_REQ1 (0x0040) -#define GPIO_PAR_PCI_REQ1_GPIO (0x0000) -#define GPIO_PAR_PCI_REQ0_REQ0 (0x0001) -#define GPIO_PAR_PCI_REQ0_GPIO (0x0000) - -/* Bit definitions and macros for MSCR_SDRAM */ -#define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) -#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) -#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) -#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) -#define GPIO_MSCR_SDRAM_SDDATA_UNMASK (0x3F) -#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) -#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) -#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) -#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDDQS_UNMASK (0xCF) -#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) -#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) -#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) -#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) -#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) -#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) -#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) -#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) -#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) -#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) -#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) -#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00) - -/* Bit definitions and macros for MSCR_PCI */ -#define GPIO_MSCR_PCI_PCI (0x01) -#define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01) -#define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00) - -/* Bit definitions and macros for DSCR_I2C */ -#define GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) -#define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03) -#define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02) -#define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01) -#define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_FLEXBUS */ -#define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) -#define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) -#define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) -#define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) -#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0) -#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80) -#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40) -#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00) -#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30) -#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20) -#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10) -#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00) -#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C) -#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08) -#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04) -#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00) -#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03) -#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02) -#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01) -#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_FEC */ -#define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) -#define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) -#define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C) -#define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08) -#define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04) -#define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00) -#define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03) -#define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02) -#define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01) -#define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_UART */ -#define GPIO_DSCR_UART_UART0(x) (((x)&0x03)) -#define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) -#define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C) -#define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08) -#define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04) -#define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00) -#define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03) -#define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02) -#define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01) -#define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_DSPI */ -#define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) -#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03) -#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02) -#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01) -#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_TIMER */ -#define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) -#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03) -#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02) -#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01) -#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_SSI */ -#define GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) -#define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03) -#define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02) -#define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01) -#define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_DMA */ -#define GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) -#define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03) -#define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02) -#define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01) -#define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_DEBUG */ -#define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) -#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03) -#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02) -#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01) -#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_RESET */ -#define GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) -#define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03) -#define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02) -#define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01) -#define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_IRQ */ -#define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) -#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03) -#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02) -#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01) -#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_USB */ -#define GPIO_DSCR_USB_USB(x) (((x)&0x03)) -#define GPIO_DSCR_USB_USB_LOAD_50PF (0x03) -#define GPIO_DSCR_USB_USB_LOAD_30PF (0x02) -#define GPIO_DSCR_USB_USB_LOAD_20PF (0x01) -#define GPIO_DSCR_USB_USB_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_ATA */ -#define GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) -#define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03) -#define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02) -#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01) -#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00) - -/********************************************************************* -* SDRAM Controller (SDRAMC) -*********************************************************************/ - -/* Bit definitions and macros for SDMR */ -#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ -#define SDRAMC_SDMR_CMD (0x00010000) /* Command */ -#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ -#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ -#define SDRAMC_SDMR_BK_LMR (0x00000000) -#define SDRAMC_SDMR_BK_LEMR (0x40000000) - -/* Bit definitions and macros for SDCR */ -#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ -#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ -#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ -#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ -#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ -#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ -#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ -#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ -#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ -#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ -#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ -#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ -#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ -#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) - -/* Bit definitions and macros for SDCFG1 */ -#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ -#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ -#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ -#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ -#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ -#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ -#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ - -/* Bit definitions and macros for SDCFG2 */ -#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ -#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ -#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ -#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ - -/* Bit definitions and macros for SDCS group */ -#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ -#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ -#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) -#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) -#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) -#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) -#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) -#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) -#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) -#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) -#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) -#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) -#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) -#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) -#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) -#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) -#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) - -/********************************************************************* -* Phase Locked Loop (PLL) -*********************************************************************/ - -/* Bit definitions and macros for PCR */ -#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ -#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */ -#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */ -#define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */ -#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ -#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ -#define PLL_PCR_PFDR_MASK (0x000F0000) -#define PLL_PCR_OUTDIV5_MASK (0x000F0000) -#define PLL_PCR_OUTDIV4_MASK (0x0000F000) -#define PLL_PCR_OUTDIV3_MASK (0x00000F00) -#define PLL_PCR_OUTDIV2_MASK (0x000000F0) -#define PLL_PCR_OUTDIV1_MASK (0x0000000F) - -/* Bit definitions and macros for PSR */ -#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ -#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ -#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ -#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ - -/********************************************************************* -* PCI -*********************************************************************/ - -/* Bit definitions and macros for SCR */ -#define PCI_SCR_PE (0x80000000) /* Parity Error detected */ -#define PCI_SCR_SE (0x40000000) /* System error signalled */ -#define PCI_SCR_MA (0x20000000) /* Master aboart received */ -#define PCI_SCR_TR (0x10000000) /* Target abort received */ -#define PCI_SCR_TS (0x08000000) /* Target abort signalled */ -#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */ -#define PCI_SCR_DP (0x01000000) /* Master data parity err */ -#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */ -#define PCI_SCR_R (0x00400000) /* Reserved */ -#define PCI_SCR_66M (0x00200000) /* 66Mhz */ -#define PCI_SCR_C (0x00100000) /* Capabilities list */ -#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */ -#define PCI_SCR_S (0x00000100) /* SERR enable */ -#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */ -#define PCI_SCR_PER (0x00000040) /* Parity error response */ -#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */ -#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */ -#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */ -#define PCI_SCR_B (0x00000004) /* Bus master enable */ -#define PCI_SCR_M (0x00000002) /* Memory access control */ -#define PCI_SCR_IO (0x00000001) /* I/O access control */ - -#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */ -#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */ -#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */ -#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */ - -#define PCI_BAR_BAR0(x) (x & 0xFFFC0000) -#define PCI_BAR_BAR1(x) (x & 0xFFF00000) -#define PCI_BAR_BAR2(x) (x & 0xFFC00000) -#define PCI_BAR_BAR3(x) (x & 0xFF000000) -#define PCI_BAR_BAR4(x) (x & 0xF8000000) -#define PCI_BAR_BAR5(x) (x & 0xE0000000) -#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */ -#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */ -#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */ - -#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */ -#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */ -#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */ -#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */ - -#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */ -#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */ -#define PCI_GSCR_SE (0x10000000) /* SERR detected */ -#define PCI_GSCR_ER (0x08000000) /* Error response detected */ -#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */ -#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */ -#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */ -#define PCI_GSCR_PR (0x00000001) /* PCI reset */ - -#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */ -#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */ -#define PCI_TCR1_P (0x00010000) /* Prefetch reads */ -#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */ - -#define PCI_TCR2_B5E (0x00002000) /* */ -#define PCI_TCR2_B4E (0x00001000) /* */ -#define PCI_TCR2_B3E (0x00000800) /* */ -#define PCI_TCR2_B2E (0x00000400) /* */ -#define PCI_TCR2_B1E (0x00000200) /* */ -#define PCI_TCR2_B0E (0x00000100) /* */ -#define PCI_TCR2_CR (0x00000001) /* */ - -#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20) -#define PCI_TBATR_EN (0x00000001) /* Enable */ - -#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */ -#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */ -#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */ -#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */ -#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */ -#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */ -#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */ -#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */ -#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */ -#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */ -#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */ -#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */ -#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */ -#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */ -#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */ - -#define PCI_ICR_REE (0x04000000) /* Retry error enable */ -#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */ -#define PCI_ICR_TAE (0x01000000) /* Target abort enable */ -#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF) - -/********************************************************************/ - -#endif /* __MCF5445X__ */ diff --git a/board/freescale/m54451evb/Kconfig b/board/freescale/m54451evb/Kconfig deleted file mode 100644 index f460e51c9bac..000000000000 --- a/board/freescale/m54451evb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M54451EVB - -config SYS_CPU - default "mcf5445x" - -config SYS_BOARD - default "m54451evb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M54451EVB" - -endif diff --git a/board/freescale/m54451evb/MAINTAINERS b/board/freescale/m54451evb/MAINTAINERS deleted file mode 100644 index 52a268108094..000000000000 --- a/board/freescale/m54451evb/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -M54451EVB BOARD -#M: - -S: Maintained -F: board/freescale/m54451evb/ -F: include/configs/M54451EVB.h -F: configs/M54451EVB_defconfig -F: configs/M54451EVB_stmicro_defconfig diff --git a/board/freescale/m54451evb/Makefile b/board/freescale/m54451evb/Makefile deleted file mode 100644 index 8c2c6a9eb72c..000000000000 --- a/board/freescale/m54451evb/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m54451evb.o -extra-y += sbf_dram_init.o diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c deleted file mode 100644 index a4ddc69166b3..000000000000 --- a/board/freescale/m54451evb/m54451evb.c +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include <common.h> -#include <init.h> -#include <spi.h> -#include <asm/global_data.h> -#include <asm/immap.h> -#include <asm/io.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - /* - * need to to: - * Check serial flash size. if 2mb evb, else 8mb demo - */ - puts("Board: "); - puts("Freescale M54451 EVB\n"); - return 0; -}; - -int dram_init(void) -{ - u32 dramsize; -#ifdef CONFIG_CF_SBF - /* - * Serial Boot: The dram is already initialized in start.S - * only require to return DRAM size - */ - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; -#else - sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); - gpio_t *gpio = (gpio_t *)(MMAP_GPIO); - u32 i; - - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; - - if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) && - (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2)) - return dramsize; - - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - - out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH); - - out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); - - out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); - - udelay(200); - - /* Issue PALL */ - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); - __asm__("nop"); - - /* Perform two refresh cycles */ - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); - __asm__("nop"); - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); - __asm__("nop"); - - /* Issue LEMR */ - out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); - __asm__("nop"); - out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); - __asm__("nop"); - - out_be32(&sdram->sdcr, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000); - - udelay(100); -#endif - gd->ram_size = dramsize; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m54451evb/sbf_dram_init.S b/board/freescale/m54451evb/sbf_dram_init.S deleted file mode 100644 index ee08cd1ecb03..000000000000 --- a/board/freescale/m54451evb/sbf_dram_init.S +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Board-specific sbf ddr/sdram init. - * - * (C) Copyright 2017 Angelo Dureghello angelo@sysam.it - */ - - #include <config.h> - -.global sbf_dram_init -.text - -sbf_dram_init: - /* Dram Initialization a1, a2, and d0 */ - /* mscr sdram */ - move.l #0xFC0A4074, %a1 - move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) - nop - - /* SDRAM Chip 0 and 1 */ - move.l #0xFC0B8110, %a1 - move.l #0xFC0B8114, %a2 - - /* calculate the size */ - move.l #0x13, %d1 - move.l #(CONFIG_SYS_SDRAM_SIZE), %d2 -#ifdef CONFIG_SYS_SDRAM_BASE1 - lsr.l #1, %d2 -#endif - -dramsz_loop: - lsr.l #1, %d2 - add.l #1, %d1 - cmp.l #1, %d2 - bne dramsz_loop -#ifdef CONFIG_SYS_NAND_BOOT - beq asm_nand_chk_status -#endif - /* SDRAM Chip 0 and 1 */ - move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) - or.l %d1, (%a1) -#ifdef CONFIG_SYS_SDRAM_BASE1 - move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2) - or.l %d1, (%a2) -#endif - nop - - /* dram cfg1 and cfg2 */ - move.l #0xFC0B8008, %a1 - move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1) - nop - move.l #0xFC0B800C, %a2 - move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2) - nop - - move.l #0xFC0B8000, %a1 /* Mode */ - move.l #0xFC0B8004, %a2 /* Ctrl */ - - /* Issue PALL */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) - nop - - move.l #1000, %d1 - bsr asm_delay - - /* Issue PALL */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) - nop - - /* Perform two refresh cycles */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0 - nop - move.l %d0, (%a2) - move.l %d0, (%a2) - nop - - /* Issue LEMR */ - move.l #(CONFIG_SYS_SDRAM_MODE), (%a1) - nop - move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1) - - move.l #500, %d1 - bsr asm_delay - - move.l #(CONFIG_SYS_SDRAM_CTRL), %d1 - and.l #0x7FFFFFFF, %d1 - - or.l #0x10000C00, %d1 - - move.l %d1, (%a2) - nop - - move.l #2000, %d1 - bsr asm_delay - - rts diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig deleted file mode 100644 index a3583e5c5bab..000000000000 --- a/configs/M54451EVB_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x0 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="M54451EVB" -CONFIG_TARGET_M54451EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000" -CONFIG_BOOTDELAY=1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="-> " -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0x40000 -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig deleted file mode 100644 index 5f5e6a55f6fa..000000000000 --- a/configs/M54451EVB_stmicro_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x47E00000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x20000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="M54451EVB_stmicro" -CONFIG_TARGET_M54451EVB=y -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000" -CONFIG_BOOTDELAY=1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_USE_ENV_SPI_CS=y -CONFIG_ENV_SPI_CS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_DM_ETH=y -CONFIG_MCFFEC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 43bb761483e3..cef9eecac214 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -105,17 +105,11 @@ static void set_fec_duplex_speed(volatile fec_t *fecp, int dup_spd) }

if ((dup_spd & 0xFFFF) == _100BASET) { -#ifdef CONFIG_MCF5445x - fecp->rcr &= ~0x200; /* disabled 10T base */ -#endif #ifdef MII_DEBUG printf("100Mbps\n"); #endif bd->bi_ethspeed = 100; } else { -#ifdef CONFIG_MCF5445x - fecp->rcr |= 0x200; /* enabled 10T base */ -#endif #ifdef MII_DEBUG printf("10Mbps\n"); #endif diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h deleted file mode 100644 index f5bafb70e77e..000000000000 --- a/include/configs/M54451EVB.h +++ /dev/null @@ -1,242 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF54451 EVB board. - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M54451EVB_H -#define _M54451EVB_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_M54451EVB /* M54451EVB board */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*) - -#undef CONFIG_WATCHDOG - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Network configuration */ -#ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_ETHPRIME "FEC0" -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 - -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#define CONFIG_HOSTNAME "M54451EVB" -#ifdef CONFIG_SYS_STMICRO_BOOT -/* ST Micro serial flash */ -#define CONFIG_SYS_LOAD_ADDR2 0x40010007 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "sbfhdr=sbfhdr.bin\0" \ - "uboot=u-boot.bin\0" \ - "load=tftp ${loadaddr} ${sbfhdr};" \ - "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ - "upd=run load; run prog\0" \ - "prog=sf probe 0:1 1000000 3;" \ - "sf erase 0 30000;" \ - "sf write ${loadaddr} 0 30000;" \ - "save\0" \ - "" -#else -#define CONFIG_SYS_UBOOT_END 0x3FFFF -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=40010000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ - "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ - "save\0" \ - "" -#endif - -/* Realtime clock */ -#define CONFIG_MCFRTC -#undef RTC_DEBUG -#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) - -/* Timer */ -#define CONFIG_MCFTMR - -/* I2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -/* DSPI and Serial Flash */ -#define CONFIG_CF_DSPI -#define CONFIG_SERIAL_FLASH -#define CONFIG_SYS_SBFHDR_SIZE 0x7 - -/* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK - -#define CONFIG_PRAM 2048 /* 2048 KB */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) - -#define CONFIG_SYS_MBAR 0xFC000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x33633F30 -#define CONFIG_SYS_SDRAM_CFG2 0x57670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 -#define CONFIG_SYS_SDRAM_EMOD 0x80810000 -#define CONFIG_SYS_SDRAM_MODE 0x008D0000 -#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 - -#ifdef CONFIG_CF_SBF -# define CONFIG_SERIAL_BOOT -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) -#else -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -/* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* Configuration for environment - * Environment is not embedded in u-boot. First time runing may have env - * crc error warning if there is no correct environment on the flash. - */ - -/* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE - -#ifdef CONFIG_SYS_FLASH_CFI - -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -# define CONFIG_SYS_FLASH_CHECKSUM -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } - -#endif - -/* - * This is setting for JFFS2 support in u-boot. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ -#ifdef CONFIG_CMD_JFFS2 -# define CONFIG_JFFS2_DEV "nor0" -# define CONFIG_JFFS2_PART_SIZE 0x01000000 -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) -#endif - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ - CF_CACR_ICINVA | CF_CACR_EUSP) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ - CF_CACR_DEC | CF_CACR_DDCM_P | \ - CF_CACR_DCINVA) & ~CF_CACR_ICINVA) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -/* - * CS0 - NOR Flash 16MB - * CS1 - Available - * CS2 - Available - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ - - /* Flash */ -#define CONFIG_SYS_CS0_BASE 0x00000000 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00004D80 - -#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE - -#endif /* _M54451EVB_H */

This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is also the last in family remove the related support as well.

Cc: Angelo Durgehello angelo.dureghello@timesys.com Cc: TsiChung Liew Tsi-Chung.Liew@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/m68k/Kconfig | 9 - arch/m68k/dts/M52277EVB.dts | 25 -- arch/m68k/dts/M52277EVB_stmicro.dts | 22 -- arch/m68k/dts/Makefile | 2 - arch/m68k/dts/mcf5227x.dtsi | 48 --- arch/m68k/include/asm/cache.h | 2 +- arch/m68k/include/asm/immap.h | 28 -- arch/m68k/include/asm/immap_5227x.h | 237 ----------- arch/m68k/include/asm/m5227x.h | 546 -------------------------- board/freescale/m52277evb/Kconfig | 15 - board/freescale/m52277evb/MAINTAINERS | 7 - board/freescale/m52277evb/Makefile | 6 - board/freescale/m52277evb/README | 228 ----------- board/freescale/m52277evb/m52277evb.c | 94 ----- configs/M52277EVB_defconfig | 34 -- configs/M52277EVB_stmicro_defconfig | 36 -- include/configs/M52277EVB.h | 243 ------------ 17 files changed, 1 insertion(+), 1581 deletions(-) delete mode 100644 arch/m68k/dts/M52277EVB.dts delete mode 100644 arch/m68k/dts/M52277EVB_stmicro.dts delete mode 100644 arch/m68k/dts/mcf5227x.dtsi delete mode 100644 arch/m68k/include/asm/immap_5227x.h delete mode 100644 arch/m68k/include/asm/m5227x.h delete mode 100644 board/freescale/m52277evb/Kconfig delete mode 100644 board/freescale/m52277evb/MAINTAINERS delete mode 100644 board/freescale/m52277evb/Makefile delete mode 100644 board/freescale/m52277evb/README delete mode 100644 board/freescale/m52277evb/m52277evb.c delete mode 100644 configs/M52277EVB_defconfig delete mode 100644 configs/M52277EVB_stmicro_defconfig delete mode 100644 include/configs/M52277EVB.h

diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 2d4714184149..1ab37cc9fc3d 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -113,18 +113,10 @@ config M54418 bool select MCF5441x

-config M52277 - bool - select MCF5227x - choice prompt "Target select" optional

-config TARGET_M52277EVB - bool "Support M52277EVB" - select M52277 - config TARGET_M5235EVB bool "Support M5235EVB" select M5235 @@ -191,7 +183,6 @@ source "board/BuS/eb_cpu5282/Kconfig" source "board/astro/mcf5373l/Kconfig" source "board/cobra5272/Kconfig" source "board/freescale/m5208evbe/Kconfig" -source "board/freescale/m52277evb/Kconfig" source "board/freescale/m5235evb/Kconfig" source "board/freescale/m5249evb/Kconfig" source "board/freescale/m5253demo/Kconfig" diff --git a/arch/m68k/dts/M52277EVB.dts b/arch/m68k/dts/M52277EVB.dts deleted file mode 100644 index a2210c88115f..000000000000 --- a/arch/m68k/dts/M52277EVB.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5227x.dtsi" - -/ { - model = "Freescale M52277EVB"; - compatible = "fsl,M52277EVB"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&dspi0 { - status = "okay"; -}; diff --git a/arch/m68k/dts/M52277EVB_stmicro.dts b/arch/m68k/dts/M52277EVB_stmicro.dts deleted file mode 100644 index 5fd3ca5efd8e..000000000000 --- a/arch/m68k/dts/M52277EVB_stmicro.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/dts-v1/; -/include/ "mcf5227x.dtsi" - -/ { - model = "Freescale M52277_stmicro"; - compatible = "fsl,M52277_stmicro"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile index 49618e64fef6..fdd435bc345e 100644 --- a/arch/m68k/dts/Makefile +++ b/arch/m68k/dts/Makefile @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+

-dtb-$(CONFIG_TARGET_M52277EVB) += M52277EVB.dtb \ - M52277EVB_stmicro.dtb dtb-$(CONFIG_TARGET_M5235EVB) += M5235EVB.dtb \ M5235EVB_Flash32.dtb dtb-$(CONFIG_TARGET_COBRA5272) += cobra5272.dtb diff --git a/arch/m68k/dts/mcf5227x.dtsi b/arch/m68k/dts/mcf5227x.dtsi deleted file mode 100644 index 8c95edddb650..000000000000 --- a/arch/m68k/dts/mcf5227x.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it - */ - -/ { - compatible = "fsl,mcf5227x"; - - aliases { - serial0 = &uart0; - spi0 = &dspi0; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - uart0: uart@fc060000 { - compatible = "fsl,mcf-uart"; - reg = <0xfc060000 0x40>; - status = "disabled"; - }; - - uart1: uart@fc064000 { - compatible = "fsl,mcf-uart"; - reg = <0xfc064000 0x40>; - status = "disabled"; - }; - - uart2: uart@fc068000 { - compatible = "fsl,mcf-uart"; - reg = <0xfc068000 0x40>; - status = "disabled"; - }; - - dspi0: dspi@fc05c000 { - compatible = "fsl,mcf-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfc05c000 0x100>; - spi-max-frequency = <50000000>; - num-cs = <4>; - spi-mode = <0>; - status = "disabled"; - }; - }; -}; diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 1c04d6df7c51..ceb462f438f2 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -10,7 +10,7 @@ #define __CACHE_H

#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ - defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x) + defined(CONFIG_MCF52x2) #define CONFIG_CF_V2 #endif

diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 81837a7c161b..02aa95aaf262 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -32,34 +32,6 @@ #define CONFIG_SYS_NUM_IRQS (128) #endif /* CONFIG_M520x */

-#ifdef CONFIG_M52277 -#include <asm/immap_5227x.h> -#include <asm/m5227x.h> - -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) - -#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) - -#ifdef CONFIG_LCD -#define CONFIG_SYS_LCD_BASE (MMAP_LCD) -#endif - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (6) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) -#endif /* CONFIG_M52277 */ - #ifdef CONFIG_M5235 #include <asm/immap_5235.h> #include <asm/m5235.h> diff --git a/arch/m68k/include/asm/immap_5227x.h b/arch/m68k/include/asm/immap_5227x.h deleted file mode 100644 index 710d6f5c0ddf..000000000000 --- a/arch/m68k/include/asm/immap_5227x.h +++ /dev/null @@ -1,237 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * MCF5227x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#ifndef __IMMAP_5227X__ -#define __IMMAP_5227X__ - -/* Module Base Addresses */ -#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_CAN (CONFIG_SYS_MBAR + 0x00020000) -#define MMAP_RTC (CONFIG_SYS_MBAR + 0x0003C000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040010) -#define MMAP_SCM3 (CONFIG_SYS_MBAR + 0x00040070) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000) -#define MMAP_IACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_PWM (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00094000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_ADC (CONFIG_SYS_MBAR + 0x000A8000) -#define MMAP_LCD (CONFIG_SYS_MBAR + 0x000AC000) -#define MMAP_LCD_BGLUT (CONFIG_SYS_MBAR + 0x000AC800) -#define MMAP_LCD_GWLUT (CONFIG_SYS_MBAR + 0x000ACC00) -#define MMAP_USBHW (CONFIG_SYS_MBAR + 0x000B0000) -#define MMAP_USBCAPS (CONFIG_SYS_MBAR + 0x000B0100) -#define MMAP_USBEHCI (CONFIG_SYS_MBAR + 0x000B0140) -#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B01A0) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000) -#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) - -#include <asm/coldfire/crossbar.h> -#include <asm/coldfire/dspi.h> -#include <asm/coldfire/edma.h> -#include <asm/coldfire/eport.h> -#include <asm/coldfire/flexbus.h> -#include <asm/coldfire/flexcan.h> -#include <asm/coldfire/intctrl.h> -#include <asm/coldfire/lcd.h> -#include <asm/coldfire/pwm.h> -#include <asm/coldfire/ssi.h> - -/* Reset Controller Module (RCM) */ -typedef struct rcm { - u8 rcr; - u8 rsr; -} rcm_t; - -/* Chip Configuration Module (CCM) */ -typedef struct ccm { - u16 ccr; /* Chip Configuration (Rd-only) */ - u16 resv1; - u16 rcon; /* Reset Configuration (Rd-only) */ - u16 cir; /* Chip Identification (Rd-only) */ - u32 resv2; - u16 misccr; /* Miscellaneous Control */ - u16 cdr; /* Clock Divider */ - u16 uocsr; /* USB On-the-Go Controller Status */ - u16 resv4; - u16 sbfsr; /* Serial Boot Status */ - u16 sbfcr; /* Serial Boot Control */ -} ccm_t; - -typedef struct canex_ctrl { - can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ - u32 res0[0x700]; /* 0x100 */ - can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */ -} canex_t; - -/* General Purpose I/O Module (GPIO) */ -typedef struct gpio { - /* Port Output Data Registers */ - u8 podr_be; /* 0x00 */ - u8 podr_cs; /* 0x01 */ - u8 podr_fbctl; /* 0x02 */ - u8 podr_i2c; /* 0x03 */ - u8 rsvd1; /* 0x04 */ - u8 podr_uart; /* 0x05 */ - u8 podr_dspi; /* 0x06 */ - u8 podr_timer; /* 0x07 */ - u8 podr_lcdctl; /* 0x08 */ - u8 podr_lcddatah; /* 0x09 */ - u8 podr_lcddatam; /* 0x0A */ - u8 podr_lcddatal; /* 0x0B */ - - /* Port Data Direction Registers */ - u8 pddr_be; /* 0x0C */ - u8 pddr_cs; /* 0x0D */ - u8 pddr_fbctl; /* 0x0E */ - u8 pddr_i2c; /* 0x0F */ - u8 rsvd2; /* 0x10 */ - u8 pddr_uart; /* 0x11 */ - u8 pddr_dspi; /* 0x12 */ - u8 pddr_timer; /* 0x13 */ - u8 pddr_lcdctl; /* 0x14 */ - u8 pddr_lcddatah; /* 0x15 */ - u8 pddr_lcddatam; /* 0x16 */ - u8 pddr_lcddatal; /* 0x17 */ - - /* Port Pin Data/Set Data Registers */ - u8 ppdsdr_be; /* 0x18 */ - u8 ppdsdr_cs; /* 0x19 */ - u8 ppdsdr_fbctl; /* 0x1A */ - u8 ppdsdr_i2c; /* 0x1B */ - u8 rsvd3; /* 0x1C */ - u8 ppdsdr_uart; /* 0x1D */ - u8 ppdsdr_dspi; /* 0x1E */ - u8 ppdsdr_timer; /* 0x1F */ - u8 ppdsdr_lcdctl; /* 0x20 */ - u8 ppdsdr_lcddatah; /* 0x21 */ - u8 ppdsdr_lcddatam; /* 0x22 */ - u8 ppdsdr_lcddatal; /* 0x23 */ - - /* Port Clear Output Data Registers */ - u8 pclrr_be; /* 0x24 */ - u8 pclrr_cs; /* 0x25 */ - u8 pclrr_fbctl; /* 0x26 */ - u8 pclrr_i2c; /* 0x27 */ - u8 rsvd4; /* 0x28 */ - u8 pclrr_uart; /* 0x29 */ - u8 pclrr_dspi; /* 0x2A */ - u8 pclrr_timer; /* 0x2B */ - u8 pclrr_lcdctl; /* 0x2C */ - u8 pclrr_lcddatah; /* 0x2D */ - u8 pclrr_lcddatam; /* 0x2E */ - u8 pclrr_lcddatal; /* 0x2F */ - - /* Pin Assignment Registers */ - u8 par_be; /* 0x30 */ - u8 par_cs; /* 0x31 */ - u8 par_fbctl; /* 0x32 */ - u8 par_i2c; /* 0x33 */ - u16 par_uart; /* 0x34 */ - u8 par_dspi; /* 0x36 */ - u8 par_timer; /* 0x37 */ - u8 par_lcdctl; /* 0x38 */ - u8 par_irq; /* 0x39 */ - u16 rsvd6; /* 0x3A - 0x3B */ - u32 par_lcdh; /* 0x3C */ - u32 par_lcdl; /* 0x40 */ - - /* Mode select control registers */ - u8 mscr_fb; /* 0x44 */ - u8 mscr_sdram; /* 0x45 */ - - u16 rsvd7; /* 0x46 - 0x47 */ - u8 dscr_dspi; /* 0x48 */ - u8 dscr_timer; /* 0x49 */ - u8 dscr_i2c; /* 0x4A */ - u8 dscr_lcd; /* 0x4B */ - u8 dscr_debug; /* 0x4C */ - u8 dscr_clkrst; /* 0x4D */ - u8 dscr_irq; /* 0x4E */ - u8 dscr_uart; /* 0x4F */ -} gpio_t; - -/* SDRAM Controller (SDRAMC) */ -typedef struct sdramc { - u32 sdmr; /* Mode/Extended Mode */ - u32 sdcr; /* Control */ - u32 sdcfg1; /* Configuration 1 */ - u32 sdcfg2; /* Chip Select */ - u8 resv0[0x100]; - u32 sdcs0; /* Mode/Extended Mode */ - u32 sdcs1; /* Mode/Extended Mode */ -} sdramc_t; - -/* Phase Locked Loop (PLL) */ -typedef struct pll { - u32 pcr; /* PLL Control */ - u32 psr; /* PLL Status */ -} pll_t; - -/* System Control Module register */ -typedef struct scm1 { - u32 mpr; /* 0x00 Master Privilege */ - u32 rsvd1[7]; - u32 pacra; /* 0x20 */ - u32 pacrb; /* 0x24 */ - u32 pacrc; /* 0x28 */ - u32 pacrd; /* 0x2C */ - u32 rsvd2[4]; - u32 pacre; /* 0x40 */ - u32 pacrf; /* 0x44 */ - u32 pacrg; /* 0x48 */ - u32 rsvd3; - u32 pacri; /* 0x50 */ -} scm1_t; - -typedef struct scm2_ctrl { - u8 res1[3]; /* 0x00 - 0x02 */ - u8 wcr; /* 0x03 wakeup control */ - u16 res2; /* 0x04 - 0x05 */ - u16 cwcr; /* 0x06 Core Watchdog Control */ - u8 res3[3]; /* 0x08 - 0x0A */ - u8 cwsr; /* 0x0B Core Watchdog Service */ - u8 res4[2]; /* 0x0C - 0x0D */ - u8 scmisr; /* 0x0F Interrupt Status */ - u32 res5; /* 0x20 */ - u32 bcr; /* 0x24 Burst Configuration */ -} scm2_t; - -typedef struct scm3_ctrl { - u32 cfadr; /* 0x00 Core Fault Address */ - u8 res7; /* 0x04 */ - u8 cfier; /* 0x05 Core Fault Interrupt Enable */ - u8 cfloc; /* 0x06 Core Fault Location */ - u8 cfatr; /* 0x07 Core Fault Attributes */ - u32 cfdtr; /* 0x08 Core Fault Data */ -} scm3_t; - -typedef struct rtcex { - u32 rsvd1[3]; - u32 gocu; - u32 gocl; -} rtcex_t; -#endif /* __IMMAP_5227X__ */ diff --git a/arch/m68k/include/asm/m5227x.h b/arch/m68k/include/asm/m5227x.h deleted file mode 100644 index 67c16e0b90f3..000000000000 --- a/arch/m68k/include/asm/m5227x.h +++ /dev/null @@ -1,546 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * MCF5227x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#ifndef __MCF5227X__ -#define __MCF5227X__ - -/* Interrupt Controller (INTC) */ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_EDMA_00 (8) -#define INT0_LO_EDMA_01 (9) -#define INT0_LO_EDMA_02 (10) -#define INT0_LO_EDMA_03 (11) -#define INT0_LO_EDMA_04 (12) -#define INT0_LO_EDMA_05 (13) -#define INT0_LO_EDMA_06 (14) -#define INT0_LO_EDMA_07 (15) -#define INT0_LO_EDMA_08 (16) -#define INT0_LO_EDMA_09 (17) -#define INT0_LO_EDMA_10 (18) -#define INT0_LO_EDMA_11 (19) -#define INT0_LO_EDMA_12 (20) -#define INT0_LO_EDMA_13 (21) -#define INT0_LO_EDMA_14 (22) -#define INT0_LO_EDMA_15 (23) -#define INT0_LO_EDMA_ERR (24) -#define INT0_LO_SCM_CWIC (25) -#define INT0_LO_UART0 (26) -#define INT0_LO_UART1 (27) -#define INT0_LO_UART2 (28) -#define INT0_LO_I2C (30) -#define INT0_LO_DSPI (31) -#define INT0_HI_DTMR0 (32) -#define INT0_HI_DTMR1 (33) -#define INT0_HI_DTMR2 (34) -#define INT0_HI_DTMR3 (35) -#define INT0_HI_SCMIR (62) -#define INT0_HI_RTC_ISR (63) - -#define INT1_HI_CAN_BOFFINT (1) -#define INT1_HI_CAN_ERRINT (3) -#define INT1_HI_CAN_BUF0I (4) -#define INT1_HI_CAN_BUF1I (5) -#define INT1_HI_CAN_BUF2I (6) -#define INT1_HI_CAN_BUF3I (7) -#define INT1_HI_CAN_BUF4I (8) -#define INT1_HI_CAN_BUF5I (9) -#define INT1_HI_CAN_BUF6I (10) -#define INT1_HI_CAN_BUF7I (11) -#define INT1_HI_CAN_BUF8I (12) -#define INT1_HI_CAN_BUF9I (13) -#define INT1_HI_CAN_BUF10I (14) -#define INT1_HI_CAN_BUF11I (15) -#define INT1_HI_CAN_BUF12I (16) -#define INT1_HI_CAN_BUF13I (17) -#define INT1_HI_CAN_BUF14I (18) -#define INT1_HI_CAN_BUF15I (19) -#define INT1_HI_PIT0_PIF (43) -#define INT1_HI_PIT1_PIF (44) -#define INT1_HI_USBOTG_STS (47) -#define INT1_HI_SSI_ISR (49) -#define INT1_HI_PWM_INT (50) -#define INT1_HI_LCDC_ISR (51) -#define INT1_HI_CCM_UOCSR (53) -#define INT1_HI_DSPI_EOQF (54) -#define INT1_HI_DSPI_TFFF (55) -#define INT1_HI_DSPI_TCF (56) -#define INT1_HI_DSPI_TFUF (57) -#define INT1_HI_DSPI_RFDF (58) -#define INT1_HI_DSPI_RFOF (59) -#define INT1_HI_DSPI_RFOF_TFUF (60) -#define INT1_HI_TOUCH_ADC (61) -#define INT1_HI_PLL_LOCKS (62) - -/********************************************************************* -* Reset Controller Module (RCM) -*********************************************************************/ - -/* Bit definitions and macros for RCR */ -#define RCM_RCR_FRCRSTOUT (0x40) -#define RCM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for RSR */ -#define RCM_RSR_LOL (0x01) -#define RCM_RSR_WDR_CORE (0x02) -#define RCM_RSR_EXT (0x04) -#define RCM_RSR_POR (0x08) -#define RCM_RSR_SOFT (0x20) - -/********************************************************************* -* Chip Configuration Module (CCM) -*********************************************************************/ - -/* Bit definitions and macros for CCR */ -#define CCM_CCR_DRAMSEL (0x0100) -#define CCM_CCR_CSC_UNMASK (0xFF3F) -#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0) -#define CCM_CCR_CSC_FBCS5_A22 (0x0080) -#define CCM_CCR_CSC_FB_A23_A22 (0x0040) -#define CCM_CCR_LIMP (0x0020) -#define CCM_CCR_LOAD (0x0010) -#define CCM_CCR_BOOTPS_UNMASK (0xFFF3) -#define CCM_CCR_BOOTPS_PS16 (0x0008) -#define CCM_CCR_BOOTPS_PS8 (0x0004) -#define CCM_CCR_BOOTPS_PS32 (0x0000) -#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002) - -/* Bit definitions and macros for RCON */ -#define CCM_RCON_CSC_UNMASK (0xFF3F) -#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0) -#define CCM_RCON_CSC_FBCS5_A22 (0x0080) -#define CCM_RCON_CSC_FB_A23_A22 (0x0040) -#define CCM_RCON_LIMP (0x0020) -#define CCM_RCON_LOAD (0x0010) -#define CCM_RCON_BOOTPS_UNMASK (0xFFF3) -#define CCM_RCON_BOOTPS_PS16 (0x0008) -#define CCM_RCON_BOOTPS_PS8 (0x0004) -#define CCM_RCON_BOOTPS_PS32 (0x0000) -#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002) - -/* Bit definitions and macros for CIR */ -#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) -#define CCM_CIR_PRN(x) ((x) & 0x003F) -#define CCM_CIR_PIN_MCF52277 (0x0000) - -/* Bit definitions and macros for MISCCR */ -#define CCM_MISCCR_RTCSRC (0x4000) -#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */ -#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ - -#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */ -#define CCM_MISCCR_BMT_65536 (0) -#define CCM_MISCCR_BMT_32768 (1) -#define CCM_MISCCR_BMT_16384 (2) -#define CCM_MISCCR_BMT_8192 (3) -#define CCM_MISCCR_BMT_4096 (4) -#define CCM_MISCCR_BMT_2048 (5) -#define CCM_MISCCR_BMT_1024 (6) -#define CCM_MISCCR_BMT_512 (7) - -#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ -#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ -#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ -#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ -#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */ -#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */ -#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ - -/* Bit definitions and macros for CDR */ -#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12) -#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */ -#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */ - -/* Bit definitions and macros for UOCSR */ -#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */ -#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */ -#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */ -#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */ -#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */ -#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ -#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ -#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ -#define CCM_UOCSR_SEND (0x0010) /* Session end */ -#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ -#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */ -#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */ - -/********************************************************************* -* General Purpose I/O Module (GPIO) -*********************************************************************/ -/* Bit definitions and macros for PAR_BE */ -#define GPIO_PAR_BE_UNMASK (0x0F) -#define GPIO_PAR_BE_BE3_BE3 (0x08) -#define GPIO_PAR_BE_BE3_GPIO (0x00) -#define GPIO_PAR_BE_BE2_BE2 (0x04) -#define GPIO_PAR_BE_BE2_GPIO (0x00) -#define GPIO_PAR_BE_BE1_BE1 (0x02) -#define GPIO_PAR_BE_BE1_GPIO (0x00) -#define GPIO_PAR_BE_BE0_BE0 (0x01) -#define GPIO_PAR_BE_BE0_GPIO (0x00) - -/* Bit definitions and macros for PAR_CS */ -#define GPIO_PAR_CS_CS3 (0x10) -#define GPIO_PAR_CS_CS2 (0x08) -#define GPIO_PAR_CS_CS1_FBCS1 (0x06) -#define GPIO_PAR_CS_CS1_SDCS1 (0x04) -#define GPIO_PAR_CS_CS1_GPIO (0x00) -#define GPIO_PAR_CS_CS0 (0x01) - -/* Bit definitions and macros for PAR_FBCTL */ -#define GPIO_PAR_FBCTL_OE (0x80) -#define GPIO_PAR_FBCTL_TA (0x40) -#define GPIO_PAR_FBCTL_RW (0x20) -#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) -#define GPIO_PAR_FBCTL_TS_FBTS (0x18) -#define GPIO_PAR_FBCTL_TS_DMAACK (0x10) -#define GPIO_PAR_FBCTL_TS_GPIO (0x00) - -/* Bit definitions and macros for PAR_FECI2C */ -#define GPIO_PAR_I2C_SCL_UNMASK (0xF3) -#define GPIO_PAR_I2C_SCL_SCL (0x0C) -#define GPIO_PAR_I2C_SCL_CANTXD (0x08) -#define GPIO_PAR_I2C_SCL_U2TXD (0x04) -#define GPIO_PAR_I2C_SCL_GPIO (0x00) - -#define GPIO_PAR_I2C_SDA_UNMASK (0xFC) -#define GPIO_PAR_I2C_SDA_SDA (0x03) -#define GPIO_PAR_I2C_SDA_CANRXD (0x02) -#define GPIO_PAR_I2C_SDA_U2RXD (0x01) -#define GPIO_PAR_I2C_SDA_GPIO (0x00) - -/* Bit definitions and macros for PAR_UART */ -#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF) -#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000) -#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000) -#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000) -#define GPIO_PAR_UART_U1CTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF) -#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000) -#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000) -#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000) -#define GPIO_PAR_UART_U1RTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF) -#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) -#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800) -#define GPIO_PAR_UART_U1RXD_GPIO (0x0000) - -#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF) -#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) -#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200) -#define GPIO_PAR_UART_U1TXD_GPIO (0x0000) - -#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F) -#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0) -#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080) -#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040) -#define GPIO_PAR_UART_U0CTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF) -#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030) -#define GPIO_PAR_UART_U0RTS_T1IN (0x0020) -#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010) -#define GPIO_PAR_UART_U0RTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3) -#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C) -#define GPIO_PAR_UART_U0RXD_CANRX (0x0008) -#define GPIO_PAR_UART_U0RXD_GPIO (0x0000) - -#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC) -#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003) -#define GPIO_PAR_UART_U0TXD_CANTX (0x0002) -#define GPIO_PAR_UART_U0TXD_GPIO (0x0000) - -/* Bit definitions and macros for PAR_DSPI */ -#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F) -#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0) -#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80) -#define GPIO_PAR_DSPI_PCS0_GPIO (0x00) -#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF) -#define GPIO_PAR_DSPI_SIN_SIN (0x30) -#define GPIO_PAR_DSPI_SIN_U2RXD (0x20) -#define GPIO_PAR_DSPI_SIN_GPIO (0x00) -#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3) -#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C) -#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08) -#define GPIO_PAR_DSPI_SOUT_GPIO (0x00) -#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC) -#define GPIO_PAR_DSPI_SCK_SCK (0x03) -#define GPIO_PAR_DSPI_SCK_U2CTS (0x02) -#define GPIO_PAR_DSPI_SCK_GPIO (0x00) - -/* Bit definitions and macros for PAR_TIMER */ -#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) -#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) -#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) -#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40) -#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) -#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) -#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) -#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10) -#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) -#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) -#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) -#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04) -#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) -#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) -#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) -#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01) -#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) - -/* Bit definitions and macros for GPIO_PAR_LCDCTL */ -#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7) -#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18) -#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10) -#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00) -#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04) -#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02) -#define GPIO_PAR_LCDCTL_LSCLK (0x01) - -/* Bit definitions and macros for PAR_IRQ */ -#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3) -#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C) -#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08) -#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) -#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC) -#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03) -#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02) -#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01) -#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) - -/* Bit definitions and macros for GPIO_PAR_LCDH */ -#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF) -#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00) -#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800) -#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF) -#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300) -#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200) -#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F) -#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0) -#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080) -#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF) -#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030) -#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020) -#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3) -#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C) -#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008) -#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC) -#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003) -#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002) -#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000) - -/* Bit definitions and macros for GPIO_PAR_LCDL */ -#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF) -#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000) -#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000) -#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF) -#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000) -#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000) -#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF) -#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000) -#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000) -#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF) -#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000) -#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000) -#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF) -#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000) -#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000) -#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF) -#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000) -#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000) -#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF) -#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000) -#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000) -#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF) -#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000) -#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000) -#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF) -#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000) -#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000) -#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF) -#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000) -#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000) -#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF) -#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00) -#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800) -#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF) -#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300) -#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200) -#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000) - -/* Bit definitions and macros for MSCR_FB */ -#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF) -#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30) -#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20) -#define GPIO_MSCR_FB_DUPPER_OD (0x10) -#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00) - -#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3) -#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C) -#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08) -#define GPIO_MSCR_FB_DLOWER_OD (0x04) -#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00) - -#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC) -#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03) -#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02) -#define GPIO_MSCR_FB_ADDRCTL_OD (0x01) -#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00) - -/* Bit definitions and macros for MSCR_SDRAM */ -#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF) -#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30) -#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20) -#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10) -#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00) - -#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) -#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C) -#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08) -#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04) -#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00) - -#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) -#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03) -#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02) -#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01) -#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00) - -/* Bit definitions and macros for Drive Strength Control */ -#define DSCR_LOAD_50PF (0x03) -#define DSCR_LOAD_30PF (0x02) -#define DSCR_LOAD_20PF (0x01) -#define DSCR_LOAD_10PF (0x00) - -/********************************************************************* -* SDRAM Controller (SDRAMC) -*********************************************************************/ - -/* Bit definitions and macros for SDMR */ -#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ -#define SDRAMC_SDMR_CMD (0x00010000) /* Command */ -#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ -#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ -#define SDRAMC_SDMR_BK_LMR (0x00000000) -#define SDRAMC_SDMR_BK_LEMR (0x40000000) - -/* Bit definitions and macros for SDCR */ -#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ -#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ -#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ -#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ -#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ -#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ -#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ -#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ -#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ -#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ -#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ -#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ -#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ -#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) - -/* Bit definitions and macros for SDCFG1 */ -#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ -#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ -#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ -#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ -#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ -#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ -#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ - -/* Bit definitions and macros for SDCFG2 */ -#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ -#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ -#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ -#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ - -/* Bit definitions and macros for SDCS group */ -#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ -#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ -#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) -#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) -#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) -#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) -#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) -#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) -#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) -#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) -#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) -#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) -#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) -#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) -#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) -#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) -#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) - -/********************************************************************* -* Phase Locked Loop (PLL) -*********************************************************************/ - -/* Bit definitions and macros for PCR */ -#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ -#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */ -#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */ -#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ -#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ -#define PLL_PCR_PFDR_MASK (0x000F0000) -#define PLL_PCR_OUTDIV5_MASK (0x000F0000) -#define PLL_PCR_OUTDIV3_MASK (0x00000F00) -#define PLL_PCR_OUTDIV2_MASK (0x000000F0) -#define PLL_PCR_OUTDIV1_MASK (0x0000000F) - -/* Bit definitions and macros for PSR */ -#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ -#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ -#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ -#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ - -/********************************************************************/ - -#endif /* __MCF5227X__ */ diff --git a/board/freescale/m52277evb/Kconfig b/board/freescale/m52277evb/Kconfig deleted file mode 100644 index c4278926a4ba..000000000000 --- a/board/freescale/m52277evb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M52277EVB - -config SYS_CPU - default "mcf5227x" - -config SYS_BOARD - default "m52277evb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M52277EVB" - -endif diff --git a/board/freescale/m52277evb/MAINTAINERS b/board/freescale/m52277evb/MAINTAINERS deleted file mode 100644 index a2a2176f6a39..000000000000 --- a/board/freescale/m52277evb/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -M52277EVB BOARD -M: TsiChung Liew Tsi-Chung.Liew@nxp.com -S: Maintained -F: board/freescale/m52277evb/ -F: include/configs/M52277EVB.h -F: configs/M52277EVB_defconfig -F: configs/M52277EVB_stmicro_defconfig diff --git a/board/freescale/m52277evb/Makefile b/board/freescale/m52277evb/Makefile deleted file mode 100644 index f98b0c937762..000000000000 --- a/board/freescale/m52277evb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m52277evb.o diff --git a/board/freescale/m52277evb/README b/board/freescale/m52277evb/README deleted file mode 100644 index 8bfd8122dd89..000000000000 --- a/board/freescale/m52277evb/README +++ /dev/null @@ -1,228 +0,0 @@ -Freescale MCF52277EVB ColdFire Development Board -================================================ - -TsiChung Liew(Tsi-Chung.Liew@freescale.com) -Created Jan 8, 2008 -=========================================== - - -Changed files: -============== - -- board/freescale/m52277evb/m52277evb.c Dram setup -- board/freescale/m52277evb/Makefile Makefile -- board/freescale/m52277evb/config.mk config make -- board/freescale/m52277evb/u-boot.lds Linker description - -- arch/m68k/cpu/mcf5227x/cpu.c cpu specific code -- arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs -- arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support -- arch/m68k/cpu/mcf5227x/speed.c system, flexbus, and cpu clock -- arch/m68k/cpu/mcf5227x/Makefile Makefile -- arch/m68k/cpu/mcf5227x/config.mk config make -- arch/m68k/cpu/mcf5227x/start.S start up assembly code - -- board/freescale/m52277evb/README This readme file - -- drivers/serial/mcfuart.c ColdFire common UART driver -- drivers/rtc/mcfrtc.c Realtime clock Driver - -- include/asm-m68k/bitops.h Bit operation function export -- include/asm-m68k/byteorder.h Byte order functions -- include/asm-m68k/crossbar.h CrossBar structure and definition -- include/asm-m68k/dspi.h DSPI structure and definition -- include/asm-m68k/edma.h eDMA structure and definition -- include/asm-m68k/flexbus.h FlexBus structure and definition -- include/asm-m68k/fsl_i2c.h I2C structure and definition -- include/asm-m68k/global_data.h Global data structure -- include/asm-m68k/immap.h ColdFire specific header file and driver macros -- include/asm-m68k/immap_5227x.h mcf5227x specific header file -- include/asm-m68k/io.h io functions -- include/asm-m68k/lcd.h LCD structure and definition -- include/asm-m68k/m5227x.h mcf5227x specific header file -- include/asm-m68k/posix_types.h Posix -- include/asm-m68k/processor.h header file -- include/asm-m68k/ptrace.h Exception structure -- include/asm-m68k/rtc.h Realtime clock header file -- include/asm-m68k/ssi.h SSI structure and definition -- include/asm-m68k/string.h String function export -- include/asm-m68k/timer.h Timer structure and definition -- include/asm-m68k/types.h Data types definition -- include/asm-m68k/uart.h Uart structure and definition -- include/asm-m68k/u-boot.h U-Boot structure - -- include/configs/M52277EVB.h Board specific configuration file - -- arch/m68k/lib/board.c board init function -- arch/m68k/lib/cache.c -- arch/m68k/lib/interrupts Coldfire common interrupt functions -- arch/m68k/lib/m68k_linux.c -- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) -- arch/m68k/lib/traps.c Exception init code - -1 MCF52277 specific Options/Settings -==================================== -1.1 pre-loader is no longer suppoer in this coldfire family - -1.2 Configuration settings for M52277EVB Development Board -CONFIG_MCF5227x -- define for all MCF5227x CPUs -CONFIG_M52277 -- define for all Freescale MCF52277 CPUs - -CONFIG_MCFUART -- define to use common CF Uart driver -CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 -CONFIG_BAUDRATE -- define UART baudrate - -CONFIG_MCFRTC -- define to use common CF RTC driver -CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h -CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency -RTC_DEBUG -- define to show RTC debug message -CONFIG_CMD_DATE -- enable to use date feature in U-Boot - -CONFIG_MCFTMR -- define to use DMA timer - -CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset -CONFIG_SYS_IMMR -- define for MBAR offset - -CONFIG_SYS_MBAR -- define MBAR offset - -CONFIG_MONITOR_IS_IN_RAM -- Not support - -CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF52277 internal SRAM - -CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register -CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register -CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register - -CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base - -CONFIG_LCD and CONFIG_CMD_USB are not supported in this current U-Boot, -update will be provided at later time - -2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL -=========================================== -2.1. System memory map: - Flash: 0x00000000-0x3FFFFFFF (1024MB) - DDR: 0x40000000-0x7FFFFFFF (1024MB) - SRAM: 0x80000000-0x8FFFFFFF (256MB) - IP: 0xF0000000-0xFFFFFFFF (256MB) - -2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and - linux kernel, you can customize it based on your system requirements: - Flash0: 0x00000000-0x00FFFFFF (16MB) - - DDR: 0x40000000-0x4FFFFFFF (64MB) - SRAM: 0x80000000-0x80007FFF (32KB) - IP: 0xFC000000-0xFC0FFFFF (64KB) - -3. COMPILATION -============== -3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or -uClinux version) from codesourcery.com was used. Download it from: -http://www.codesourcery.com/gnu_toolchains/coldfire/download.html - -3.2 Compilation - export CROSS_COMPILE=cross-compile-prefix - cd u-boot-1.x.x - make distclean - make M52277EVB_config - make - -4. SCREEN DUMP -============== -4.1 M52277EVB Development board - (NOTE: May not show exactly the same) - -U-Boot 1.3.1 (Jan 8 2008 - 12:44:08) - -CPU: Freescale MCF52277 (Mask:6c Version:0) - CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ - INP CLK 16 Mhz VCO CLK 480 Mhz -Board: Freescale 52277 EVB -I2C: ready -DRAM: 64 MB -FLASH: 16 MB -In: serial -Out: serial -Err: serial --> print -baudrate=115200 -hostname=M52277EVB -inpclk=16000000 -loadaddr=(0x40000000 + 0x10000) -load=tftp ${loadaddr) ${u-boot} -upd=run load; run prog -prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save -u-boot=u-boot.bin -stdin=serial -stdout=serial -stderr=serial -mem=65024k - -Environment size: 280/32764 bytes --> bdinfo -memstart = 0x40000000 -memsize = 0x04000000 -flashstart = 0x00000000 -flashsize = 0x01000000 -flashoffset = 0x00000000 -sramstart = 0x80000000 -sramsize = 0x00008000 -mbar = 0xFC000000 -busfreq = 80 MHz -flbfreq = 80 Mhz -inpfreq = 16 Mhz -vcofreq = 480 Mhz - -baudrate = 115200 bps --> --> help -? - alias for 'help' -base - print or set address offset -bdinfo - print Board Info structure -boot - boot default, i.e., run 'bootcmd' -bootd - boot default, i.e., run 'bootcmd' -bootelf - Boot from an ELF image in memory -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -bootvx - Boot vxWorks from an ELF image -cmp - memory compare -coninfo - print console devices and information -cp - memory copy -crc32 - checksum calculation -date - get/set/reset date & time -dcache - enable or disable data cache -echo - echo args to console -erase - erase FLASH memory -flinfo - print FLASH memory information -go - start application at address 'addr' -help - print online help -i2c - I2C sub-system -icache - enable or disable instruction cache -iminfo - print header information for application image -imls - list all images found in flash -itest - return true/false on integer compare -loadb - load binary file over serial line (kermit mode) -loads - load S-Record file over serial line -loady - load binary file over serial line (ymodem mode) -loop - infinite loop on address range -ls - list files in a directory (default /) -md - memory display -mm - memory modify (auto-incrementing) -mtest - simple RAM test -mw - memory write (fill) -nm - memory modify (constant address) -ping - send ICMP ECHO_REQUEST to network host -printenv- print environment variables -protect - enable or disable FLASH write protection -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -sleep - delay execution for some time -source - run script from memory -version - print monitor version --> diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c deleted file mode 100644 index 510af33e4c3c..000000000000 --- a/board/freescale/m52277evb/m52277evb.c +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/immap.h> -#include <asm/io.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale M52277 EVB\n"); - return 0; -}; - -int dram_init(void) -{ - u32 dramsize; - -#ifdef CONFIG_CF_SBF - /* - * Serial Boot: The dram is already initialized in start.S - * only require to return DRAM size - */ - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; -#else - sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); - gpio_t *gpio = (gpio_t *)(MMAP_GPIO); - u32 i; - - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; - - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - - out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH); - - out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); - - out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); - - /* Issue PALL */ - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); - __asm__("nop"); - - /* Issue LEMR */ - out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); - __asm__("nop"); - out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD); - __asm__("nop"); - - udelay(1000); - - /* Issue PALL */ - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); - __asm__("nop"); - - /* Perform two refresh cycles */ - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); - __asm__("nop"); - out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); - __asm__("nop"); - - out_be32(&sdram->sdcr, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); - - udelay(100); -#endif - gd->ram_size = dramsize; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig deleted file mode 100644 index bab8ac4b78d2..000000000000 --- a/configs/M52277EVB_defconfig +++ /dev/null @@ -1,34 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x0 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_SECT_SIZE=0x8000 -CONFIG_DEFAULT_DEVICE_TREE="M52277EVB" -CONFIG_TARGET_M52277EVB=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT" -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="-> " -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_JFFS2=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0x40000 -# CONFIG_NET is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig deleted file mode 100644 index 98c64ff31a66..000000000000 --- a/configs/M52277EVB_stmicro_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -CONFIG_M68K=y -CONFIG_SYS_TEXT_BASE=0x43E00000 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x30000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="M52277EVB_stmicro" -CONFIG_TARGET_M52277EVB=y -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT" -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_JFFS2=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_USE_ENV_SPI_CS=y -CONFIG_ENV_SPI_CS=2 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_NET is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CF_SPI=y diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h deleted file mode 100644 index 0428be729b23..000000000000 --- a/include/configs/M52277EVB.h +++ /dev/null @@ -1,243 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF52277 EVB board. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M52277EVB_H -#define _M52277EVB_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_WATCHDOG - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_HOSTNAME "M52277EVB" -#define CONFIG_SYS_UBOOT_END 0x3FFFF -#define CONFIG_SYS_LOAD_ADDR2 0x40010007 -#ifdef CONFIG_SYS_STMICRO_BOOT -/* ST Micro serial flash */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "uboot=u-boot.bin\0" \ - "load=loadb ${loadaddr} ${baudrate};" \ - "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ - "upd=run load; run prog\0" \ - "prog=sf probe 0:2 10000 1;" \ - "sf erase 0 30000;" \ - "sf write ${loadaddr} 0 30000;" \ - "save\0" \ - "" -#endif -#ifdef CONFIG_SYS_SPANSION_BOOT -#define CONFIG_EXTRA_ENV_SETTINGS \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "uboot=u-boot.bin\0" \ - "load=loadb ${loadaddr} ${baudrate}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ - " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ - "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ - __stringify(CONFIG_SYS_UBOOT_END) ";" \ - "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ - " ${filesize}; save\0" \ - "updsbf=run loadsbf; run progsbf\0" \ - "loadsbf=loadb ${loadaddr} ${baudrate};" \ - "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ - "progsbf=sf probe 0:2 10000 1;" \ - "sf erase 0 30000;" \ - "sf write ${loadaddr} 0 30000;" \ - "" -#endif - -/* LCD */ -#ifdef CONFIG_CMD_BMP -#define CONFIG_LCD_LOGO -#define CONFIG_SHARP_LQ035Q7DH06 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 -#define CONFIG_SYS_USB_EHCI_CPU_INIT -#endif - -/* Realtime clock */ -#define CONFIG_MCFRTC -#undef RTC_DEBUG -#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) - -/* Timer */ -#define CONFIG_MCFTMR - -/* I2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -/* DSPI and Serial Flash */ -#define CONFIG_CF_DSPI -#define CONFIG_SYS_SBFHDR_SIZE 0x7 - -/* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK - -#define CONFIG_SYS_INPUT_CLKSRC 16000000 - -#define CONFIG_PRAM 2048 /* 2048 KB */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) - -#define CONFIG_SYS_MBAR 0xFC000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x81810000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 -#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 - -#ifdef CONFIG_CF_SBF -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) -#else -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) - -/* - * Configuration for environment - * Environment is not embedded in u-boot. First time runing may have env - * crc error warning if there is no correct environment on the flash. - */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_STMICRO_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -#endif -#ifdef CONFIG_SYS_SPANSION_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -#endif - -#ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_FLASH_SPANSION_S29WS_N 1 -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -# define CONFIG_SYS_FLASH_CHECKSUM -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } -#endif - -#define LDS_BOARD_TEXT \ - arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ - arch/m68k/lib/built-in.o (.text*) - -/* - * This is setting for JFFS2 support in u-boot. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ -#ifdef CONFIG_CMD_JFFS2 -# define CONFIG_JFFS2_DEV "nor0" -# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -/* - * CS0 - NOR Flash - * CS1 - Available - * CS2 - Available - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ - -#ifdef CONFIG_CF_SBF -#define CONFIG_SYS_CS0_BASE 0x04000000 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 -#else -#define CONFIG_SYS_CS0_BASE 0x00000000 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 -#endif - -#endif /* _M52277EVB_H */

As we have now completed the DM_VIDEO and DM_SPI_FLASH migrations we can remove the checks.

Signed-off-by: Tom Rini trini@konsulko.com --- Makefile | 4 ---- 1 file changed, 4 deletions(-)

diff --git a/Makefile b/Makefile index 9fac1a02ca6e..ca2432c8ce9d 100644 --- a/Makefile +++ b/Makefile @@ -1125,10 +1125,6 @@ ifneq ($(CONFIG_DM),y) @echo >&2 "See doc/driver-model/migration.rst for more info." @echo >&2 "====================================================" endif - $(call deprecated,CONFIG_DM_VIDEO,video,v2019.07,\ - $(CONFIG_LCD)$(CONFIG_VIDEO)) - $(call deprecated,CONFIG_DM_SPI_FLASH,SPI flash,v2019.07,\ - $(CONFIG_SPI_FLASH)) $(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\ $(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG)) $(call deprecated,CONFIG_DM_ETH,Ethernet drivers,v2020.07,$(CONFIG_NET))