From: Peng Fan peng.fan@nxp.com

The ahab was missed to be compiled, so add it back.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8ulp/Kconfig | 5 +++++ arch/arm/mach-imx/imx8ulp/Makefile | 1 + 2 files changed, 6 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig index c1c1aa08c52..49ea25250a3 100644 --- a/arch/arm/mach-imx/imx8ulp/Kconfig +++ b/arch/arm/mach-imx/imx8ulp/Kconfig @@ -1,5 +1,10 @@ if ARCH_IMX8ULP

+config AHAB_BOOT + bool "Support i.MX8ULP AHAB features" + help + This option enables the support for AHAB secure boot. + config IMX8ULP bool

diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index 2c9938fcdf0..f7692cf3a78 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -5,6 +5,7 @@

obj-y += lowlevel_init.o obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o +obj-$(CONFIG_AHAB_BOOT) += ahab.o

ifeq ($(CONFIG_SPL_BUILD),y) obj-y += upower/

From: Ye Li ye.li@nxp.com

The TMU used on iMX93 is IP revision 2.1 which is different with previous revision used on iMX8MQ. So add a new FLAG V4 for this revision to distinguish the operations.

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/thermal/Kconfig | 6 +-- drivers/thermal/imx_tmu.c | 101 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+), 3 deletions(-)

diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 97d4163e8ed..681b621760d 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -27,10 +27,10 @@ config IMX_SCU_THERMAL trip is crossed

config IMX_TMU - bool "Thermal Management Unit driver for NXP i.MX8M" - depends on ARCH_IMX8M + bool "Thermal Management Unit driver for NXP i.MX8M and iMX93" + depends on ARCH_IMX8M || IMX93 help - Support for Temperature sensors on NXP i.MX8M. + Support for Temperature sensors on NXP i.MX8M and iMX93. It supports one critical trip point and one passive trip point. The boot is hold to the cool device to throttle CPUs when the passive trip is crossed diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index eb5605590fd..97efc550443 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -25,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SITES_MAX 16 #define FLAGS_VER2 0x1 #define FLAGS_VER3 0x2 +#define FLAGS_VER4 0x4

#define TMR_DISABLE 0x0 #define TMR_ME 0x80000000 @@ -76,6 +77,45 @@ struct imx_tmu_regs { u32 ttr3cr; /* Temperature Range 3 Control Register */ };

+struct imx_tmu_regs_v4 { + u32 tmr; /* Mode Register */ + u32 tsr; /* Status Register */ + u32 tmsr; /* Monitor Site Register */ + u32 tmtmir; /* Temperature measurement interval Register */ + u8 res0[0x10]; + u32 tier; /* Interrupt Enable Register */ + u32 tidr; /* Interrupt Detect Register */ + u8 res1[0x8]; + u32 tiiscr; /* Interrupt Immediate Site Capture Register */ + u32 tiascr; /* Interrupt Average Site Capture Register */ + u32 ticscr; /* Interrupt Critical Site Capture Register */ + u8 res2[0x4]; + u32 tmhtcr; /* Monitor High Temperature Capture Register */ + u32 tmltcr; /* MonitorLow Temperature Capture Register */ + u32 tmrtrcr; /* Monitor Rising Temperature Rate Capture Register */ + u32 tmftrcr; /* Monitor Falling Temperature Rate Capture Register */ + u32 tmhtitr; /* Monitor High Temperature Immediate Threshold */ + u32 tmhtatr; /* Monitor High Temperature Average Threshold */ + u32 tmhtactr; /* Monitor High Temperature Average Crit Threshold */ + u8 res3[0x4]; + u32 tmltitr; /* Monitor Low Temperature Immediate Threshold */ + u32 tmltatr; /* Monitor Low Temperature Average Threshold */ + u32 tmltactr; /* Monitor Low Temperature Average Crit Threshold */ + u8 res4[0x4]; + u32 tmrtrctr; /* Monitor Rising Temperature Rate Critical Threshold Register */ + u32 tmftrctr; /* Monitor Falling Temperature Rate Critical Threshold Register */ + u8 res5[0x8]; + u32 ttcfgr; /* Temperature Configuration Register */ + u32 tscfgr; /* Sensor Configuration Register */ + u8 res6[0x78]; + u32 tritsr0; /* Immediate Temperature Site Register */ + u32 tratsr0; /* Average Temperature Site Register */ + u8 res7[0xdf8]; + u32 tcmcfg; /* Central Module Configuration */ + u8 res8[0xc]; + u32 ttrcr[16]; /* Temperature Range Control Register */ +}; + struct imx_tmu_regs_v2 { u32 ter; /* TMU enable Register */ u32 tsr; /* Status Register */ @@ -115,6 +155,7 @@ union tmu_regs { struct imx_tmu_regs regs_v1; struct imx_tmu_regs_v2 regs_v2; struct imx_tmu_regs_v3 regs_v3; + struct imx_tmu_regs_v4 regs_v4; };

struct imx_tmu_plat { @@ -148,6 +189,9 @@ static int read_temperature(struct udevice *dev, int *temp) * only reflects the RAW uncalibrated data */ valid = ((val & 0xff) < 10 || (val & 0xff) > 125) ? 0 : 1; + } else if (drv_data & FLAGS_VER4) { + val = readl(&pdata->regs->regs_v4.tritsr0); + valid = val & 0x80000000; } else { val = readl(&pdata->regs->regs_v1.site[pdata->id].tritsr); valid = val & 0x80000000; @@ -165,6 +209,13 @@ static int read_temperature(struct udevice *dev, int *temp) return -EINVAL;

*temp *= 1000; + } else if (drv_data & FLAGS_VER4) { + *temp = (val & 0x1ff) * 1000; + if (val & 0x200) + *temp += 500; + + /* Convert Kelvin to Celsius */ + *temp -= 273000; } else { *temp = (val & 0xff) * 1000; } @@ -206,6 +257,7 @@ static const struct dm_thermal_ops imx_tmu_ops = { static int imx_tmu_calibration(struct udevice *dev) { int i, val, len, ret; + int index; u32 range[4]; const fdt32_t *calibration; struct imx_tmu_plat *pdata = dev_get_plat(dev); @@ -216,6 +268,25 @@ static int imx_tmu_calibration(struct udevice *dev) if (drv_data & (FLAGS_VER2 | FLAGS_VER3)) return 0;

+ if (drv_data & FLAGS_VER4) { + calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len); + if (!calibration || len % 8 || len > 128) { + printf("TMU: invalid calibration data.\n"); + return -ENODEV; + } + + for (i = 0; i < len; i += 8, calibration += 2) { + index = i / 8; + writel(index, &pdata->regs->regs_v4.ttcfgr); + val = fdt32_to_cpu(*calibration); + writel(val, &pdata->regs->regs_v4.tscfgr); + val = fdt32_to_cpu(*(calibration + 1)); + writel((1 << 31) | val, &pdata->regs->regs_v4.ttrcr[index]); + } + + return 0; + } + ret = dev_read_u32_array(dev, "fsl,tmu-range", range, 4); if (ret) { dev_err(dev, "TMU: missing calibration range, ret = %d.\n", ret); @@ -329,12 +400,16 @@ static void imx_tmu_mx8mp_init(struct udevice *dev) static inline void imx_tmu_mx8mp_init(struct udevice *dev) { } #endif

+static inline void imx_tmu_mx93_init(struct udevice *dev) { } + static void imx_tmu_arch_init(struct udevice *dev) { if (is_imx8mm() || is_imx8mn()) imx_tmu_mx8mm_mx8mn_init(dev); else if (is_imx8mp()) imx_tmu_mx8mp_init(dev); + else if (is_imx93()) + imx_tmu_mx93_init(dev); else dev_err(dev, "Unsupported SoC, TMU calibration not loaded!\n"); } @@ -359,6 +434,15 @@ static void imx_tmu_init(struct udevice *dev)

/* Disable interrupt, using polling instead */ writel(0x0, &pdata->regs->regs_v2.tier); + } else if (drv_data & FLAGS_VER4) { + /* Disable monitoring */ + writel(TMR_DISABLE, &pdata->regs->regs_v4.tmr); + + /* Disable interrupt, using polling instead */ + writel(TIER_DISABLE, &pdata->regs->regs_v4.tier); + + /* Set update_interval */ + writel(TMTMIR_DEFAULT, &pdata->regs->regs_v4.tmtmir); } else { /* Disable monitoring */ writel(TMR_DISABLE, &pdata->regs->regs_v1.tmr); @@ -411,6 +495,22 @@ static int imx_tmu_enable_msite(struct udevice *dev) /* Enable monitor */ reg |= TER_EN; writel(reg, &pdata->regs->regs_v2.ter); + } else if (drv_data & FLAGS_VER4) { + reg = readl(&pdata->regs->regs_v4.tcmcfg); + reg |= (1 << 30) | (1 << 28); + reg &= ~0xF000; /* set SAR clk = IPG clk /16 */ + writel(reg, &pdata->regs->regs_v4.tcmcfg); + + /* Set ALPF*/ + reg = readl(&pdata->regs->regs_v4.tmr); + reg |= TMR_ALPF; + writel(reg, &pdata->regs->regs_v4.tmr); + + writel(1, &pdata->regs->regs_v4.tmsr); + + /* Enable ME */ + reg |= TMR_ME; + writel(reg, &pdata->regs->regs_v4.tmr); } else { /* Clear the ME before setting MSITE and ALPF*/ reg = readl(&pdata->regs->regs_v1.tmr); @@ -551,6 +651,7 @@ static const struct udevice_id imx_tmu_ids[] = { { .compatible = "fsl,imx8mq-tmu", }, { .compatible = "fsl,imx8mm-tmu", .data = FLAGS_VER2, }, { .compatible = "fsl,imx8mp-tmu", .data = FLAGS_VER3, }, + { .compatible = "fsl,imx93-tmu", .data = FLAGS_VER4, }, { } };

From: Peng Fan peng.fan@nxp.com

Unknow->Unknown

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/spl_imx_romapi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 830d5d12c25..9164045115f 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -367,7 +367,7 @@ int board_return_to_bootrom(struct spl_image_info *spl_image, printf("USB boot\n"); break; default: - printf("Unknow (0x%x)\n", bstage); + printf("Unknown (0x%x)\n", bstage); }

if (is_boot_from_stream_device(boot))

From: Peng Fan peng.fan@nxp.com

Move imx8 sci header file to include/firmware/imx, then we could use build macro to reuse some i.MX8 drivers for i.MX9, such as drivers/cpu/imx8_cpu.c.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8/power-domain.h | 2 +- arch/arm/include/asm/arch-imx8/sys_proto.h | 2 +- arch/arm/mach-imx/cmd_dek.c | 2 +- arch/arm/mach-imx/imx8/ahab.c | 2 +- arch/arm/mach-imx/imx8/cpu.c | 2 +- arch/arm/mach-imx/imx8/fdt.c | 2 +- arch/arm/mach-imx/imx8/iomux.c | 2 +- arch/arm/mach-imx/imx8/misc.c | 2 +- arch/arm/mach-imx/imx8/snvs_security_sc.c | 2 +- arch/arm/mach-imx/parse-container.c | 2 +- .../imx8qm_rom7720_a1/imx8qm_rom7720_a1.c | 2 +- board/advantech/imx8qm_rom7720_a1/spl.c | 2 +- board/congatec/cgtqmx8/cgtqmx8.c | 2 +- board/freescale/imx8qm_mek/imx8qm_mek.c | 2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- board/freescale/imx8qxp_mek/spl.c | 2 +- board/siemens/capricorn/board.c | 2 +- board/toradex/apalis-imx8/apalis-imx8.c | 2 +- board/toradex/colibri-imx8x/colibri-imx8x.c | 2 +- drivers/clk/imx/clk-imx8.c | 2 +- drivers/clk/imx/clk-imx8qm.c | 2 +- drivers/clk/imx/clk-imx8qxp.c | 2 +- drivers/cpu/imx8_cpu.c | 2 +- drivers/cpu/imx9_cpu.c | 224 ++++++++++++++++++ drivers/misc/imx8/fuse.c | 2 +- drivers/misc/imx8/scu.c | 2 +- drivers/misc/imx8/scu_api.c | 2 +- drivers/pinctrl/nxp/pinctrl-scu.c | 2 +- .../power/domain/imx8-power-domain-legacy.c | 2 +- drivers/power/domain/imx8-power-domain.c | 2 +- drivers/thermal/imx_scu_thermal.c | 2 +- .../firmware/imx}/sci/rpc.h | 0 .../firmware/imx}/sci/sci.h | 14 +- .../firmware/imx}/sci/svc/misc/api.h | 0 .../firmware/imx}/sci/svc/pad/api.h | 0 .../firmware/imx}/sci/svc/pm/api.h | 0 .../firmware/imx}/sci/svc/rm/api.h | 2 +- .../firmware/imx}/sci/svc/seco/api.h | 2 +- .../firmware/imx}/sci/types.h | 0 39 files changed, 263 insertions(+), 39 deletions(-) create mode 100644 drivers/cpu/imx9_cpu.c rename {arch/arm/include/asm/arch-imx8 => include/firmware/imx}/sci/rpc.h (100%) rename {arch/arm/include/asm/arch-imx8 => include/firmware/imx}/sci/sci.h (94%) rename {arch/arm/include/asm/arch-imx8 => include/firmware/imx}/sci/svc/misc/api.h (100%) rename {arch/arm/include/asm/arch-imx8 => include/firmware/imx}/sci/svc/pad/api.h (100%) rename {arch/arm/include/asm/arch-imx8 => include/firmware/imx}/sci/svc/pm/api.h (100%) rename {arch/arm/include/asm/arch-imx8 => include/firmware/imx}/sci/svc/rm/api.h (98%) rename {arch/arm/include/asm/arch-imx8 => include/firmware/imx}/sci/svc/seco/api.h (96%) rename {arch/arm/include/asm/arch-imx8 => include/firmware/imx}/sci/types.h (100%)

diff --git a/arch/arm/include/asm/arch-imx8/power-domain.h b/arch/arm/include/asm/arch-imx8/power-domain.h index 1db86a1209b..bdb0baa9844 100644 --- a/arch/arm/include/asm/arch-imx8/power-domain.h +++ b/arch/arm/include/asm/arch-imx8/power-domain.h @@ -6,7 +6,7 @@ #ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H #define _ASM_ARCH_IMX8_POWER_DOMAIN_H

-#include <asm/arch/sci/types.h> +#include <firmware/imx/sci/types.h>

struct imx8_power_domain_plat { sc_rsrc_t resource_id; diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h index d38f606e07e..e7625c42985 100644 --- a/arch/arm/include/asm/arch-imx8/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -3,7 +3,7 @@ * Copyright 2018 NXP */

-#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/mach-imx/sys_proto.h> #include <asm/arch/power-domain.h> #include <dm/platdata.h> diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index b65bf874b83..69ed57537b3 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -17,7 +17,7 @@ #include <mapmem.h> #include <tee.h> #ifdef CONFIG_IMX_SECO_DEK_ENCAP -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/mach-imx/image.h> #endif #include <cpu_func.h> diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 5a4d39cdaad..9addb824b6d 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -9,7 +9,7 @@ #include <log.h> #include <asm/global_data.h> #include <asm/io.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/mach-imx/sys_proto.h> #include <asm/arch-imx/cpu.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index be1f4edded1..894a8c14fe9 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -19,7 +19,7 @@ #include <errno.h> #include <spl.h> #include <thermal.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/sys_proto.h> #include <asm/arch-imx/cpu.h> #include <asm/armv8/cpu.h> diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c index a132ce2e6a3..02b3ee5c111 100644 --- a/arch/arm/mach-imx/imx8/fdt.c +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -5,7 +5,7 @@

#include <common.h> #include <log.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <dm/ofnode.h> diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c index 9c3cfbf0068..e4f7651bd1d 100644 --- a/arch/arm/mach-imx/imx8/iomux.c +++ b/arch/arm/mach-imx/imx8/iomux.c @@ -8,7 +8,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/iomux.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c index de19955e2f7..0ce3036818b 100644 --- a/arch/arm/mach-imx/imx8/misc.c +++ b/arch/arm/mach-imx/imx8/misc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ #include <common.h> #include <log.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/mach-imx/sys_proto.h> #include <imx_sip.h> #include <linux/arm-smccc.h> diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c index 507b5b42314..d7b20a1fcbf 100644 --- a/arch/arm/mach-imx/imx8/snvs_security_sc.c +++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c @@ -15,7 +15,7 @@ #include <log.h> #include <stddef.h> #include <common.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch-imx8/imx8-pins.h> #include <asm/arch-imx8/snvs_security_sc.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-imx/parse-container.c b/arch/arm/mach-imx/parse-container.c index a4214d53768..f7582825d6d 100644 --- a/arch/arm/mach-imx/parse-container.c +++ b/arch/arm/mach-imx/parse-container.c @@ -9,7 +9,7 @@ #include <spl.h> #include <asm/mach-imx/image.h> #ifdef CONFIG_AHAB_BOOT -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #endif

#define SEC_SECURE_RAM_BASE 0x31800000UL diff --git a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c index ace18b2d603..206ce7d5c13 100644 --- a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c +++ b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c @@ -15,7 +15,7 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/clock.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/imx8-pins.h> #include <asm/arch/iomux.h> #include <asm/arch/sys_proto.h> diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c index 22ed6397992..b602437c35b 100644 --- a/board/advantech/imx8qm_rom7720_a1/spl.c +++ b/board/advantech/imx8qm_rom7720_a1/spl.c @@ -14,7 +14,7 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/clock.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/imx8-pins.h> #include <asm/arch/iomux.h>

diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c index c0a8a497c7b..bedd1e03308 100644 --- a/board/congatec/cgtqmx8/cgtqmx8.c +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -12,7 +12,7 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/clock.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/imx8-pins.h> #include <usb.h> #include <asm/arch/iomux.h> diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c index 682099ad9cf..d96d1d07bb1 100644 --- a/board/freescale/imx8qm_mek/imx8qm_mek.c +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -14,7 +14,7 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/clock.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/imx8-pins.h> #include <asm/arch/iomux.h> #include <asm/arch/sys_proto.h> diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c index 21cfa142f3b..516cefd2f24 100644 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -16,7 +16,7 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/clock.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/imx8-pins.h> #include <asm/arch/snvs_security_sc.h> #include <asm/arch/iomux.h> diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c index 2fa68400561..75aab1651c0 100644 --- a/board/freescale/imx8qxp_mek/spl.c +++ b/board/freescale/imx8qxp_mek/spl.c @@ -18,7 +18,7 @@ #include <dm/lists.h> #include <asm/io.h> #include <asm/gpio.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/imx8-pins.h> #include <asm/arch/iomux.h> #include <asm/arch/sys_proto.h> diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index 4a02d64aec3..a0c62e0fc4c 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -22,7 +22,7 @@ #include <asm/gpio.h> #include <asm/arch/imx8-pins.h> #include <asm/arch/iomux.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/sys_proto.h> #ifndef CONFIG_SPL #include <asm/arch-imx8/clock.h> diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 6b43b587007..aa76c486eec 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -11,8 +11,8 @@ #include <asm/arch/clock.h> #include <asm/arch/imx8-pins.h> #include <asm/arch/iomux.h> -#include <asm/arch/sci/sci.h> #include <asm/arch/snvs_security_sc.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/io.h> diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 6ed9cc4fa80..52fc7a391bb 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -11,7 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/imx8-pins.h> #include <asm/arch/iomux.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/io.h> diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c index 24bdab28aa4..ceeead34349 100644 --- a/drivers/clk/imx/clk-imx8.c +++ b/drivers/clk/imx/clk-imx8.c @@ -9,7 +9,7 @@ #include <dm.h> #include <log.h> #include <malloc.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/clock.h> #include <dt-bindings/clock/imx8qxp-clock.h> #include <dt-bindings/soc/imx_rsrc.h> diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index b874915ba6a..6c05d07c340 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -8,7 +8,7 @@ #include <clk-uclass.h> #include <dm.h> #include <log.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/clock.h> #include <dt-bindings/clock/imx8qm-clock.h> #include <dt-bindings/soc/imx_rsrc.h> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index d580b437221..8bf7e325481 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -8,7 +8,7 @@ #include <clk-uclass.h> #include <dm.h> #include <log.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/clock.h> #include <dt-bindings/clock/imx8qxp-clock.h> #include <dt-bindings/soc/imx_rsrc.h> diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index b8eb2d28006..dc060513b38 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -9,7 +9,7 @@ #include <thermal.h> #include <asm/global_data.h> #include <asm/system.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/sys_proto.h> #include <asm/arch-imx/cpu.h> #include <asm/armv8/cpu.h> diff --git a/drivers/cpu/imx9_cpu.c b/drivers/cpu/imx9_cpu.c new file mode 100644 index 00000000000..66534fe6d17 --- /dev/null +++ b/drivers/cpu/imx9_cpu.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <thermal.h> +#include <asm/global_data.h> +#include <asm/system.h> +#include <firmware/linux/imx/sci/sci.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-imx/cpu.h> +#include <asm/armv8/cpu.h> +#include <linux/bitops.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct cpu_imx_plat { + const char *name; + const char *rev; + const char *type; + u32 cpu_rsrc; + u32 cpurev; + u32 freq_mhz; + u32 mpidr; +}; + +const char *get_imx9_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX93: + return "93"; + default: + return "??"; + } +} + +const char *get_imx9_rev(u32 rev) +{ + switch (rev) { + case CHIP_REV_1_0: + return "1."; + case CHIP_REV_B: + return "B"; + case CHIP_REV_C: + return "C"; + default: + return "?"; + } +} + +static void set_core_data(struct udevice *dev) +{ + struct cpu_imx_plat *plat = dev_get_plat(dev); + + if (device_is_compatible(dev, "arm,cortex-a35")) + plat->name = "A35"; + else + plat->name = "?"; +} + +#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL) +static int cpu_imx_get_temp(struct cpu_imx_plat *plat) +{ + struct udevice *thermal_dev; + int cpu_tmp, ret; + int idx = 1; /* use "cpu-thermal0" device */ + + if (plat->cpu_rsrc == SC_R_A72) + idx = 2; /* use "cpu-thermal1" device */ + + ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev); + if (!ret) { + ret = thermal_get_temp(thermal_dev, &cpu_tmp); + if (ret) + return 0xdeadbeef; + } else { + return 0xdeadbeef; + } + + return cpu_tmp; +} +#else +static int cpu_imx_get_temp(struct cpu_imx_plat *plat) +{ + return 0; +} +#endif + +int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size) +{ + struct cpu_imx_plat *plat = dev_get_plat(dev); + int ret, temp; + + if (size < 100) + return -ENOSPC; + + ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz", + plat->type, plat->rev, plat->name, plat->freq_mhz); + + if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) { + temp = cpu_imx_get_temp(plat); + buf = buf + ret; + size = size - ret; + if (temp != 0xdeadbeef) + ret = snprintf(buf, size, " at %dC", temp); + else + ret = snprintf(buf, size, " - invalid sensor data"); + } + + snprintf(buf + ret, size - ret, "\n"); + + return 0; +} + +static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info) +{ + struct cpu_imx_plat *plat = dev_get_plat(dev); + + info->cpu_freq = plat->freq_mhz * 1000; + info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU); + return 0; +} + +static int cpu_imx_get_count(const struct udevice *dev) +{ + ofnode node; + int num = 0; + + ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { + const char *device_type; + + if (!ofnode_is_enabled(node)) + continue; + + device_type = ofnode_read_string(node, "device_type"); + if (!device_type) + continue; + + if (!strcmp(device_type, "cpu")) + num++; + } + + return num; +} + +static int cpu_imx_get_vendor(const struct udevice *dev, char *buf, int size) +{ + snprintf(buf, size, "NXP"); + return 0; +} + +static int cpu_imx_is_current(struct udevice *dev) +{ + struct cpu_imx_plat *plat = dev_get_plat(dev); + + if (plat->mpidr == (read_mpidr() & 0xffff)) + return 1; + + return 0; +} + +static const struct cpu_ops cpu_imx9_ops = { + .get_desc = cpu_imx_get_desc, + .get_info = cpu_imx_get_info, + .get_count = cpu_imx_get_count, + .get_vendor = cpu_imx_get_vendor, + .is_current = cpu_imx_is_current, +}; + +static const struct udevice_id cpu_imx9_ids[] = { + { .compatible = "arm,cortex-a35" }, + { .compatible = "arm,cortex-a53" }, + { .compatible = "arm,cortex-a72" }, + { } +}; + +static ulong imx9_get_cpu_rate(struct udevice *dev) +{ + struct cpu_imx_plat *plat = dev_get_plat(dev); + ulong rate; + int ret; + + ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU, + (sc_pm_clock_rate_t *)&rate); + if (ret) { + printf("Could not read CPU frequency: %d\n", ret); + return 0; + } + + return rate; +} + +static int imx9_cpu_probe(struct udevice *dev) +{ + struct cpu_imx_plat *plat = dev_get_plat(dev); + u32 cpurev; + + set_core_data(dev); + cpurev = get_cpu_rev(); + plat->cpurev = cpurev; + plat->rev = get_imx9_rev(cpurev & 0xFFF); + plat->type = get_imx9_type((cpurev & 0xFF000) >> 12); + plat->freq_mhz = imx9_get_cpu_rate(dev) / 1000000; + plat->mpidr = dev_read_addr(dev); + if (plat->mpidr == FDT_ADDR_T_NONE) { + printf("%s: Failed to get CPU reg property\n", __func__); + return -EINVAL; + } + + return 0; +} + +U_BOOT_DRIVER(cpu_imx9_drv) = { + .name = "imx9x_cpu", + .id = UCLASS_CPU, + .of_match = cpu_imx9_ids, + .ops = &cpu_imx9_ops, + .probe = imx9_cpu_probe, + .plat_auto = sizeof(struct cpu_imx_plat), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c index 38111c52548..b81f73f283f 100644 --- a/drivers/misc/imx8/fuse.c +++ b/drivers/misc/imx8/fuse.c @@ -7,7 +7,7 @@ #include <console.h> #include <errno.h> #include <fuse.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <linux/arm-smccc.h> diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c index 4ab5cb4bf13..798800aa758 100644 --- a/drivers/misc/imx8/scu.c +++ b/drivers/misc/imx8/scu.c @@ -13,7 +13,7 @@ #include <dm/lists.h> #include <dm/root.h> #include <dm/device-internal.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <linux/bitops.h> #include <linux/iopoll.h> #include <misc.h> diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 8f546e9b3fc..dfede7f1d5f 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -11,7 +11,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <dm.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <misc.h>

DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/pinctrl/nxp/pinctrl-scu.c b/drivers/pinctrl/nxp/pinctrl-scu.c index c032be782a1..4959834c0fc 100644 --- a/drivers/pinctrl/nxp/pinctrl-scu.c +++ b/drivers/pinctrl/nxp/pinctrl-scu.c @@ -7,7 +7,7 @@ #include <errno.h> #include <linux/bitops.h> #include <asm/io.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <misc.h>

#include "pinctrl-imx.h" diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c index bf45891bccd..37b0f95abac 100644 --- a/drivers/power/domain/imx8-power-domain-legacy.c +++ b/drivers/power/domain/imx8-power-domain-legacy.c @@ -14,7 +14,7 @@ #include <dm/device-internal.h> #include <dm/device.h> #include <dm/uclass-internal.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/drivers/power/domain/imx8-power-domain.c b/drivers/power/domain/imx8-power-domain.c index 17b5d57b19b..b45e468756b 100644 --- a/drivers/power/domain/imx8-power-domain.c +++ b/drivers/power/domain/imx8-power-domain.c @@ -10,7 +10,7 @@ #include <malloc.h> #include <power-domain-uclass.h> #include <asm/arch/power-domain.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h>

static int imx8_power_domain_on(struct power_domain *power_domain) { diff --git a/drivers/thermal/imx_scu_thermal.c b/drivers/thermal/imx_scu_thermal.c index e704bcbea86..3ec131cbc6e 100644 --- a/drivers/thermal/imx_scu_thermal.c +++ b/drivers/thermal/imx_scu_thermal.c @@ -12,7 +12,7 @@ #include <asm/global_data.h> #include <dm/device-internal.h> #include <dm/device.h> -#include <asm/arch/sci/sci.h> +#include <firmware/imx/sci/sci.h> #include <linux/delay.h> #include <linux/libfdt.h>

diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/include/firmware/imx/sci/rpc.h similarity index 100% rename from arch/arm/include/asm/arch-imx8/sci/rpc.h rename to include/firmware/imx/sci/rpc.h diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/include/firmware/imx/sci/sci.h similarity index 94% rename from arch/arm/include/asm/arch-imx8/sci/sci.h rename to include/firmware/imx/sci/sci.h index 1c29209b399..dafe892aa4d 100644 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -7,13 +7,13 @@ #define _SC_SCI_H

#include <log.h> -#include <asm/arch/sci/types.h> -#include <asm/arch/sci/svc/misc/api.h> -#include <asm/arch/sci/svc/pad/api.h> -#include <asm/arch/sci/svc/pm/api.h> -#include <asm/arch/sci/svc/rm/api.h> -#include <asm/arch/sci/svc/seco/api.h> -#include <asm/arch/sci/rpc.h> +#include <firmware/imx/sci/types.h> +#include <firmware/imx/sci/svc/misc/api.h> +#include <firmware/imx/sci/svc/pad/api.h> +#include <firmware/imx/sci/svc/pm/api.h> +#include <firmware/imx/sci/svc/rm/api.h> +#include <firmware/imx/sci/svc/seco/api.h> +#include <firmware/imx/sci/rpc.h> #include <dt-bindings/soc/imx_rsrc.h> #include <linux/errno.h>

diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/include/firmware/imx/sci/svc/misc/api.h similarity index 100% rename from arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h rename to include/firmware/imx/sci/svc/misc/api.h diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h b/include/firmware/imx/sci/svc/pad/api.h similarity index 100% rename from arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h rename to include/firmware/imx/sci/svc/pad/api.h diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h b/include/firmware/imx/sci/svc/pm/api.h similarity index 100% rename from arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h rename to include/firmware/imx/sci/svc/pm/api.h diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h b/include/firmware/imx/sci/svc/rm/api.h similarity index 98% rename from arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h rename to include/firmware/imx/sci/svc/rm/api.h index ed303881e73..163d81403c5 100644 --- a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h +++ b/include/firmware/imx/sci/svc/rm/api.h @@ -6,7 +6,7 @@ #ifndef SC_RM_API_H #define SC_RM_API_H

-#include <asm/arch/sci/types.h> +#include <firmware/imx/sci/types.h>

/* Defines for type widths */ #define SC_RM_PARTITION_W 5U /* Width of sc_rm_pt_t */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h b/include/firmware/imx/sci/svc/seco/api.h similarity index 96% rename from arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h rename to include/firmware/imx/sci/svc/seco/api.h index 3ed05842d99..6e9c302315b 100644 --- a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h +++ b/include/firmware/imx/sci/svc/seco/api.h @@ -8,7 +8,7 @@

/* Includes */

-#include <asm/arch/sci/types.h> +#include <firmware/imx/sci/types.h>

/* Defines */ #define SC_SECO_AUTH_CONTAINER 0U /* Authenticate container */ diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/include/firmware/imx/sci/types.h similarity index 100% rename from arch/arm/include/asm/arch-imx8/sci/types.h rename to include/firmware/imx/sci/types.h

From: Peng Fan peng.fan@nxp.com

Since we might reuse some drivers for other platforms, while the drivers have sci firmware api, so to avoid build failure add inline functions

Signed-off-by: Peng Fan peng.fan@nxp.com --- include/firmware/imx/sci/sci.h | 241 +++++++++++++++++++++++++++++++++ 1 file changed, 241 insertions(+)

diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index dafe892aa4d..61c8211b443 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -57,6 +57,7 @@ static inline int sc_err_to_linux(sc_err_t err) return ret; }

+#if IS_ENABLED(CONFIG_IMX8) /* PM API*/ int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_power_mode_t mode); @@ -134,5 +135,245 @@ int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data); int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data0, u32 *data1, u32 *data2, u32 *data3, u32 *data4, u8 size); +#else +/* PM API*/ +static inline int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_bool_t enable, sc_bool_t autog) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clk_parent_t parent) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address) +{ + return -EOPNOTSUPP; +} + +static inline sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + return false; +} + +static inline int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource) +{ + return -EOPNOTSUPP; +} + +/* MISC API */ +static inline int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 val) +{ + return -EOPNOTSUPP; +} + +static inline int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 *val) +{ + return -EOPNOTSUPP; +} + +static inline void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev) +{ +} + +static inline void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status) +{ +} + +static inline int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx) +{ + return -EOPNOTSUPP; +} + +static inline void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit) +{ +} + +static inline int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val) +{ + return -EOPNOTSUPP; +} + +static inline int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, + s16 *celsius, s8 *tenths) +{ + return -EOPNOTSUPP; +} + +/* RM API */ +static inline sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) +{ + return true; +} + +static inline int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start, + sc_faddr_t addr_end) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, sc_rm_pt_t pt, + sc_rm_perm_t perm) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, + sc_faddr_t *addr_end) +{ + return -EOPNOTSUPP; +} + +static inline sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource) +{ + return true; +} + +static inline int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, + sc_bool_t grant, sc_bool_t coherent) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad) +{ + return -EOPNOTSUPP; +} + +static inline sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad) +{ + return true; +} + +static inline int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_pt_t *pt) +{ + return -EOPNOTSUPP; +} + +/* PAD API */ +static inline int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val) +{ + return -EOPNOTSUPP; +} + +/* SMMU API */ +static inline int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid) +{ + return -EOPNOTSUPP; +} + +/* SECO API */ +static inline int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, u32 *uid_h) +{ + return -EOPNOTSUPP; +} + +void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) +{ +} + +static inline int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, + sc_faddr_t export_addr, u16 max_size) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, u16 msg_size, + sc_faddr_t dst_addr, u16 dst_size) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data0, u32 *data1, + u32 *data2, u32 *data3, u32 *data4, u8 size) +{ + return -EOPNOTSUPP; +} + +#endif

#endif

From: Peng Fan peng.fan@nxp.com

For local functions, use static for function.

Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/cpu/imx8_cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index dc060513b38..e7f45e60dbd 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -27,7 +27,7 @@ struct cpu_imx_plat { u32 mpidr; };

-const char *get_imx8_type(u32 imxtype) +static const char *get_imx8_type(u32 imxtype) { switch (imxtype) { case MXC_CPU_IMX8QXP: @@ -40,7 +40,7 @@ const char *get_imx8_type(u32 imxtype) } }

-const char *get_imx8_rev(u32 rev) +static const char *get_imx8_rev(u32 rev) { switch (rev) { case CHIP_REV_A: @@ -101,7 +101,7 @@ static int cpu_imx_get_temp(struct cpu_imx_plat *plat) } #endif

-int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size) +static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size) { struct cpu_imx_plat *plat = dev_get_plat(dev); int ret, temp;

From: Peng Fan peng.fan@nxp.com

Add CPU_IMX Kconfig Support imx8_cpu driver for i.MX9

Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/cpu/Kconfig | 6 +++ drivers/cpu/Makefile | 1 + drivers/cpu/imx8_cpu.c | 83 ++++++++++++++++++++++++++++-------------- 3 files changed, 62 insertions(+), 28 deletions(-)

diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig index 3bf04105e5e..1c3c810651e 100644 --- a/drivers/cpu/Kconfig +++ b/drivers/cpu/Kconfig @@ -7,6 +7,12 @@ config CPU they can work correctly in the OS. This provides a framework for finding out information about available CPUs and making changes.

+config CPU_IMX + bool "Enable i.MX CPU driver" + depends on CPU && ARM64 + help + Support CPU cores for SoCs of the i.MX series. + config CPU_MPC83XX bool "Enable MPC83xx CPU driver" depends on CPU && MPC83xx diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile index 3b38ba9c589..d4bbf6fa5e0 100644 --- a/drivers/cpu/Makefile +++ b/drivers/cpu/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o obj-$(CONFIG_ARCH_AT91) += at91_cpu.o obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o +obj-$(CONFIG_CPU_IMX) += imx8_cpu.o obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o obj-$(CONFIG_CPU_MICROBLAZE) += microblaze_cpu.o diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index e7f45e60dbd..2d3df419f1c 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -14,6 +14,7 @@ #include <asm/arch-imx/cpu.h> #include <asm/armv8/cpu.h> #include <linux/bitops.h> +#include <linux/clk-provider.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -27,30 +28,43 @@ struct cpu_imx_plat { u32 mpidr; };

-static const char *get_imx8_type(u32 imxtype) +static const char *get_imx_type_str(u32 imxtype) { switch (imxtype) { case MXC_CPU_IMX8QXP: case MXC_CPU_IMX8QXP_A0: - return "QXP"; + return "8QXP"; case MXC_CPU_IMX8QM: - return "QM"; + return "8QM"; + case MXC_CPU_IMX93: + return "93(52)";/* iMX93 Dual core with NPU */ default: return "??"; } }

-static const char *get_imx8_rev(u32 rev) +static const char *get_imx_rev_str(u32 rev) { - switch (rev) { - case CHIP_REV_A: - return "A"; - case CHIP_REV_B: - return "B"; - case CHIP_REV_C: - return "C"; - default: - return "?"; + static char revision[4]; + + if (IS_ENABLED(CONFIG_IMX8)) { + switch (rev) { + case CHIP_REV_A: + return "A"; + case CHIP_REV_B: + return "B"; + case CHIP_REV_C: + return "C"; + default: + return "?"; + } + } else { + revision[0] = '1' + (((rev & 0xf0) - CHIP_REV_1_0) >> 4); + revision[1] = '.'; + revision[2] = '0' + (rev & 0xf); + revision[3] = '\0'; + + return revision; } }

@@ -67,6 +81,8 @@ static void set_core_data(struct udevice *dev) } else if (device_is_compatible(dev, "arm,cortex-a72")) { plat->cpu_rsrc = SC_R_A72; plat->name = "A72"; + } else if (device_is_compatible(dev, "arm,cortex-a55")) { + plat->name = "A55"; } else { plat->cpu_rsrc = SC_R_A53; plat->name = "?"; @@ -109,7 +125,7 @@ static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size) if (size < 100) return -ENOSPC;

- ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz", + ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz", plat->type, plat->rev, plat->name, plat->freq_mhz);

if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) { @@ -174,7 +190,7 @@ static int cpu_imx_is_current(struct udevice *dev) return 0; }

-static const struct cpu_ops cpu_imx8_ops = { +static const struct cpu_ops cpu_imx_ops = { .get_desc = cpu_imx_get_desc, .get_info = cpu_imx_get_info, .get_count = cpu_imx_get_count, @@ -182,21 +198,32 @@ static const struct cpu_ops cpu_imx8_ops = { .is_current = cpu_imx_is_current, };

-static const struct udevice_id cpu_imx8_ids[] = { +static const struct udevice_id cpu_imx_ids[] = { { .compatible = "arm,cortex-a35" }, { .compatible = "arm,cortex-a53" }, + { .compatible = "arm,cortex-a55" }, { .compatible = "arm,cortex-a72" }, { } };

-static ulong imx8_get_cpu_rate(struct udevice *dev) +static ulong imx_get_cpu_rate(struct udevice *dev) { struct cpu_imx_plat *plat = dev_get_plat(dev); + struct clk clk; ulong rate; int ret;

- ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU, - (sc_pm_clock_rate_t *)&rate); + if (IS_ENABLED(CONFIG_IMX8)) { + ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU, + (sc_pm_clock_rate_t *)&rate); + } else { + ret = clk_get_by_index(dev, 0, &clk); + if (!ret) { + rate = clk_get_rate(&clk); + if (!rate) + ret = -EOPNOTSUPP; + } + } if (ret) { printf("Could not read CPU frequency: %d\n", ret); return 0; @@ -205,7 +232,7 @@ static ulong imx8_get_cpu_rate(struct udevice *dev) return rate; }

-static int imx8_cpu_probe(struct udevice *dev) +static int imx_cpu_probe(struct udevice *dev) { struct cpu_imx_plat *plat = dev_get_plat(dev); u32 cpurev; @@ -213,9 +240,9 @@ static int imx8_cpu_probe(struct udevice *dev) set_core_data(dev); cpurev = get_cpu_rev(); plat->cpurev = cpurev; - plat->rev = get_imx8_rev(cpurev & 0xFFF); - plat->type = get_imx8_type((cpurev & 0xFF000) >> 12); - plat->freq_mhz = imx8_get_cpu_rate(dev) / 1000000; + plat->rev = get_imx_rev_str(cpurev & 0xFFF); + plat->type = get_imx_type_str((cpurev & 0xFF000) >> 12); + plat->freq_mhz = imx_get_cpu_rate(dev) / 1000000; plat->mpidr = dev_read_addr(dev); if (plat->mpidr == FDT_ADDR_T_NONE) { printf("%s: Failed to get CPU reg property\n", __func__); @@ -225,12 +252,12 @@ static int imx8_cpu_probe(struct udevice *dev) return 0; }

-U_BOOT_DRIVER(cpu_imx8_drv) = { - .name = "imx8x_cpu", +U_BOOT_DRIVER(cpu_imx_drv) = { + .name = "imx_cpu", .id = UCLASS_CPU, - .of_match = cpu_imx8_ids, - .ops = &cpu_imx8_ops, - .probe = imx8_cpu_probe, + .of_match = cpu_imx_ids, + .ops = &cpu_imx_ops, + .probe = imx_cpu_probe, .plat_auto = sizeof(struct cpu_imx_plat), .flags = DM_FLAG_PRE_RELOC, };

From: Peng Fan peng.fan@nxp.com

Use CONFIG_DM_THERMAL to make the temperature function could be reused by i.MX8 and i.MX9

Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/cpu/imx8_cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 2d3df419f1c..4da7a99bf30 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -89,15 +89,19 @@ static void set_core_data(struct udevice *dev) } }

-#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL) +#if IS_ENABLED(CONFIG_DM_THERMAL) static int cpu_imx_get_temp(struct cpu_imx_plat *plat) { struct udevice *thermal_dev; int cpu_tmp, ret; int idx = 1; /* use "cpu-thermal0" device */

- if (plat->cpu_rsrc == SC_R_A72) - idx = 2; /* use "cpu-thermal1" device */ + if (IS_ENABLED(CONFIG_IMX8)) { + if (plat->cpu_rsrc == SC_R_A72) + idx = 2; /* use "cpu-thermal1" device */ + } else { + idx = 1; + }

ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev); if (!ret) { @@ -128,7 +132,7 @@ static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size) ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz", plat->type, plat->rev, plat->name, plat->freq_mhz);

- if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) { + if (IS_ENABLED(CONFIG_DM_THERMAL)) { temp = cpu_imx_get_temp(plat); buf = buf + ret; size = size - ret;

From: Peng Fan peng.fan@nxp.com

Support print out cpu grade temperature

Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/cpu/imx8_cpu.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)

diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 4da7a99bf30..304d5e59013 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -13,6 +13,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch-imx/cpu.h> #include <asm/armv8/cpu.h> +#include <imx_thermal.h> #include <linux/bitops.h> #include <linux/clk-provider.h>

@@ -121,10 +122,17 @@ static int cpu_imx_get_temp(struct cpu_imx_plat *plat) } #endif

+__weak u32 get_cpu_temp_grade(int *minc, int *maxc) +{ + return 0; +} + static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size) { struct cpu_imx_plat *plat = dev_get_plat(dev); + const char *grade; int ret, temp; + int minc, maxc;

if (size < 100) return -ENOSPC; @@ -132,6 +140,27 @@ static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size) ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz", plat->type, plat->rev, plat->name, plat->freq_mhz);

+ if (IS_ENABLED(CONFIG_IMX9)) { + switch (get_cpu_temp_grade(&minc, &maxc)) { + case TEMP_AUTOMOTIVE: + grade = "Automotive temperature grade "; + break; + case TEMP_INDUSTRIAL: + grade = "Industrial temperature grade "; + break; + case TEMP_EXTCOMMERCIAL: + grade = "Extended Consumer temperature grade "; + break; + default: + grade = "Consumer temperature grade "; + break; + } + + buf = buf + ret; + size = size - ret; + ret = snprintf(buf, size, "\nCPU: %s (%dC to %dC)", grade, minc, maxc); + } + if (IS_ENABLED(CONFIG_DM_THERMAL)) { temp = cpu_imx_get_temp(plat); buf = buf + ret;

From: Peng Fan peng.fan@nxp.com

The M33 systick should be 24M per reference mannual, so correct it.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 04f3116fd1c..51aa259aa05 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -700,8 +700,8 @@ int clock_init(void) ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2); /* SWO TRACE to 133M */ ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); - /* M33 systetick to 133M */ - ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 systetick to 24M */ + ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1); /* NIC to 400M */ ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2); /* NIC_APB to 133M */

From: Peng Fan peng.fan@nxp.com

Add more PLL settings for A55 and Display

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/clock.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 51aa259aa05..7d3a4c01333 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -26,6 +26,7 @@ static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR; static struct imx_intpll_rate_table imx9_intpll_tbl[] = { INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */ INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */ + INT_PLL_RATE(1500000000U, 1, 125, 2), /* 1.5Ghz */ INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */ INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */ INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */ @@ -35,8 +36,11 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = { FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */ FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */ FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */ + FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1), + FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1), FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */ FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */ + FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1), };

/* return in khz */

From: Peng Fan peng.fan@nxp.com

The freq parameter was ignored, should use it when configuring ARM PLL

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 7d3a4c01333..f6021502b3d 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -674,7 +674,7 @@ void set_arm_clk(ulong freq) { /* Increase ARM clock to 1.7Ghz */ ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); - configure_intpll(ARM_PLL_CLK, 1700000000); + configure_intpll(ARM_PLL_CLK, freq); ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); }

From: Peng Fan peng.fan@nxp.com

LPI2C_CLK_ROOT should be used instead of LPUART_CLK_ROOT for i2c

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index f6021502b3d..a0efee96e51 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -574,7 +574,7 @@ u32 imx_get_i2cclk(u32 i2c_num) if (i2c_num > 7) return -EINVAL;

- return ccm_clk_root_get_rate(LPUART1_CLK_ROOT + i2c_num); + return ccm_clk_root_get_rate(LPI2C1_CLK_ROOT + i2c_num); }

u32 get_lpuart_clk(void)

From: Peng Fan peng.fan@nxp.com

Simplify the clk root settings with an array

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx9/clock.h | 6 ++++ arch/arm/mach-imx/imx9/clock.c | 38 +++++++++++++++----------- 2 files changed, 28 insertions(+), 16 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h index 336d8613181..1169ffd74d3 100644 --- a/arch/arm/include/asm/arch-imx9/clock.h +++ b/arch/arm/include/asm/arch-imx9/clock.h @@ -205,6 +205,12 @@ struct clk_root_map { u32 mux_type; };

+struct imx_clk_setting { + u32 clk_root; + enum ccm_clk_src src; + u32 div; +}; + int clock_init(void); u32 get_clk_src_rate(enum ccm_clk_src source); u32 get_lpuart_clk(void); diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index a0efee96e51..a5f95fbcb8a 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -680,36 +680,42 @@ void set_arm_clk(ulong freq)

#endif

-int clock_init(void) -{ - int i; - +struct imx_clk_setting imx_clk_settings[] = { /* Set A55 periphal to 333M */ - ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3); + {ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3}, /* Set A55 mtr bus to 133M */ - ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); - + {ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, /* Sentinel to 200M */ - ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); + {SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2}, /* Bus_wakeup to 133M */ - ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + {BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, /* Bus_AON to 133M */ - ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + {BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, /* M33 to 200M */ - ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); + {M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2}, /* * WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for * generating MII clock at 2.5M */ - ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2); + {WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2}, /* SWO TRACE to 133M */ - ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + {SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, /* M33 systetick to 24M */ - ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1); + {M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1}, /* NIC to 400M */ - ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2); + {NIC_CLK_ROOT, SYS_PLL_PFD1, 2}, /* NIC_APB to 133M */ - ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + {NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3} +}; + +int clock_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx_clk_settings); i++) { + ccm_clk_root_cfg(imx_clk_settings[i].clk_root, + imx_clk_settings[i].src, imx_clk_settings[i].div); + }

/* allow for non-secure access */ for (i = 0; i < OSCPLL_END; i++)

From: Peng Fan peng.fan@nxp.com

OPTEE memory region is set secure access only in ATF with configuration to TRDC, and need to remove it from U-Boot, otherwise U-Boot and Kernel may crash when accessing the memory

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/soc.c | 149 ++++++++++++++++++++++++++++++++++- 1 file changed, 148 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index a16e22ea6bb..a27262492e7 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -180,13 +180,160 @@ static struct mm_region imx93_mem_map[] = {

struct mm_region *mem_map = imx93_mem_map;

+static unsigned int imx9_find_dram_entry_in_mem_map(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx93_mem_map); i++) + if (imx93_mem_map[i].phys == CFG_SYS_SDRAM_BASE) + return i; + + hang(); /* Entry not found, this must never happen. */ +} + +void enable_caches(void) +{ + /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch + * If OPTEE does not run, still update the MMU table according to dram banks structure + * to set correct dram size from board_phys_sdram_size + */ + int i = 0; + /* + * please make sure that entry initial value matches + * imx93_mem_map for DRAM1 + */ + int entry = imx9_find_dram_entry_in_mem_map(); + u64 attrs = imx93_mem_map[entry].attrs; + + while (i < CONFIG_NR_DRAM_BANKS && + entry < ARRAY_SIZE(imx93_mem_map)) { + if (gd->bd->bi_dram[i].start == 0) + break; + imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start; + imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start; + imx93_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx93_mem_map[entry].attrs = attrs; + debug("Added memory mapping (%d): %llx %llx\n", entry, + imx93_mem_map[entry].phys, imx93_mem_map[entry].size); + i++; entry++; + } + + icache_enable(); + dcache_enable(); +} + +__weak int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = PHYS_SDRAM_SIZE; + +#ifdef PHYS_SDRAM_2_SIZE + *size += PHYS_SDRAM_2_SIZE; +#endif + return 0; +} + int dram_init(void) { - gd->ram_size = PHYS_SDRAM_SIZE; + phys_size_t sdram_size; + int ret; + + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = sdram_size - rom_pointer[1]; + else + gd->ram_size = sdram_size; + + return 0; +} + +int dram_init_banksize(void) +{ + int bank = 0; + int ret; + phys_size_t sdram_size; + phys_size_t sdram_b1_size, sdram_b2_size; + + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + /* Bank 1 can't cross over 4GB space */ + if (sdram_size > 0x80000000) { + sdram_b1_size = 0x80000000; + sdram_b2_size = sdram_size - 0x80000000; + } else { + sdram_b1_size = sdram_size; + sdram_b2_size = 0; + } + + gd->bd->bi_dram[bank].start = PHYS_SDRAM; + if (rom_pointer[1]) { + phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; + phys_size_t optee_size = (size_t)rom_pointer[1]; + + gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { + if (++bank >= CONFIG_NR_DRAM_BANKS) { + puts("CONFIG_NR_DRAM_BANKS is not enough\n"); + return -1; + } + + gd->bd->bi_dram[bank].start = optee_start + optee_size; + gd->bd->bi_dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->bd->bi_dram[bank].start; + } + } else { + gd->bd->bi_dram[bank].size = sdram_b1_size; + } + + if (sdram_b2_size) { + if (++bank >= CONFIG_NR_DRAM_BANKS) { + puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); + return -1; + } + gd->bd->bi_dram[bank].start = 0x100000000UL; + gd->bd->bi_dram[bank].size = sdram_b2_size; + }

return 0; }

+phys_size_t get_effective_memsize(void) +{ + int ret; + phys_size_t sdram_size; + phys_size_t sdram_b1_size; + + ret = board_phys_sdram_size(&sdram_size); + if (!ret) { + /* Bank 1 can't cross over 4GB space */ + if (sdram_size > 0x80000000) + sdram_b1_size = 0x80000000; + else + sdram_b1_size = sdram_size; + + if (rom_pointer[1]) { + /* We will relocate u-boot to top of dram1. TEE position has two cases: + * 1. At the top of dram1, Then return the size removed optee size. + * 2. In the middle of dram1, return the size of dram1. + */ + if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size)) + return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM); + } + + return sdram_b1_size; + } else { + return PHYS_SDRAM_SIZE; + } +} + void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { mac[0] = 0x1;

From: Ye Li ye.li@nxp.com

The MAC addresses are hard coded for bring up. Change it to support reading from fuse.

Reviewed-by: Jacky Bai ping.bai@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/soc.c | 49 +++++++++++++++++++++++++++++++----- 1 file changed, 43 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index a27262492e7..e4e9eca101e 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -30,6 +30,7 @@ #include <asm/arch-imx/cpu.h> #include <asm/mach-imx/s400_api.h> #include <linux/delay.h> +#include <fuse.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -336,12 +337,48 @@ phys_size_t get_effective_memsize(void)

void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { - mac[0] = 0x1; - mac[1] = 0x2; - mac[2] = 0x3; - mac[3] = 0x4; - mac[4] = 0x5; - mac[5] = 0x6; + u32 val[2] = {}; + int ret; + + if (dev_id == 0) { + ret = fuse_read(39, 3, &val[0]); + if (ret) + goto err; + + ret = fuse_read(39, 4, &val[1]); + if (ret) + goto err; + + mac[0] = val[1] >> 8; + mac[1] = val[1]; + mac[2] = val[0] >> 24; + mac[3] = val[0] >> 16; + mac[4] = val[0] >> 8; + mac[5] = val[0]; + + } else { + ret = fuse_read(39, 5, &val[0]); + if (ret) + goto err; + + ret = fuse_read(39, 4, &val[1]); + if (ret) + goto err; + + mac[0] = val[1] >> 24; + mac[1] = val[1] >> 16; + mac[2] = val[0] >> 24; + mac[3] = val[0] >> 16; + mac[4] = val[0] >> 8; + mac[5] = val[0]; + } + + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return; +err: + memset(mac, 0, 6); + printf("%s: fuse read err: %d\n", __func__, ret); }

int print_cpuinfo(void)

From: Peng Fan peng.fan@nxp.com

select CONFIG_CPU_IMX to display cpu info

Signed-off-by: Peng Fan peng.fan@nxp.com --- configs/imx93_11x11_evk_defconfig | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 4f8777161e4..f116d52a655 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -81,6 +81,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_CPU_IMX=y CONFIG_IMX_RGPIO2P=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y

From: Peng Fan peng.fan@nxp.com

Drop unused macro

Signed-off-by: Peng Fan peng.fan@nxp.com --- include/configs/imx93_evk.h | 2 -- 1 file changed, 2 deletions(-)

diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 7b7bef3ca75..2705587a015 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -131,8 +131,6 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */

-#define CFG_SYS_FSL_USDHC_NUM 2 - /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG3_BASE_ADDR

From: Peng Fan peng.fan@nxp.com

Select thermal config to print current temperature

Signed-off-by: Peng Fan peng.fan@nxp.com --- configs/imx93_11x11_evk_defconfig | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index f116d52a655..9f376d39c03 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -112,6 +112,8 @@ CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y CONFIG_ULP_WATCHDOG=y CONFIG_LZO=y CONFIG_BZIP2=y

From: Peng Fan peng.fan@nxp.com

Support print reset cause. Since SRSR is not accessible from non-secure world, so first save it to grp0, then read it in non-secure world.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/soc.c | 59 ++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+)

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index e4e9eca101e..dcabfe34aca 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -19,6 +19,8 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/syscounter.h> #include <asm/armv8/mmu.h> +#include <dm/device.h> +#include <dm/device_compat.h> #include <dm/uclass.h> #include <env.h> #include <env_internal.h> @@ -408,6 +410,18 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif

+static void save_reset_cause(void) +{ + struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE; + u32 srsr = readl(&src->srsr); + + /* clear srsr in sec mode */ + writel(srsr, &src->srsr); + + /* Save value to GPR1 to pass to nonsecure */ + writel(srsr, &src->gpr[0]); +} + int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { @@ -417,6 +431,9 @@ int arch_cpu_init(void) clock_init();

trdc_early_init(); + + /* Save SRC SRSR to GPR1 and clear it */ + save_reset_cause(); }

return 0; @@ -650,3 +667,45 @@ int m33_prepare(void)

return 0; } + +int psci_sysreset_get_status(struct udevice *dev, char *buf, int size) +{ + static const char *reset_cause[] = { + "POR ", + "JTAG ", + "IPP USER ", + "WDOG1 ", + "WDOG2 ", + "WDOG3 ", + "WDOG4 ", + "WDOG5 ", + "TEMPSENSE ", + "CSU ", + "JTAG_SW ", + "M33_REQ ", + "M33_LOCKUP ", + "UNK ", + "UNK ", + "UNK " + }; + + struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE; + u32 srsr; + u32 i; + int res; + + srsr = readl(&src->gpr[0]); + + for (i = ARRAY_SIZE(reset_cause); i > 0; i--) { + if (srsr & (BIT(i - 1))) + break; + } + + res = snprintf(buf, size, "Reset Status: %s\n", i ? reset_cause[i - 1] : "unknown reset"); + if (res < 0) { + dev_err(dev, "Could not write reset status message (err = %d)\n", res); + return -EIO; + } + + return 0; +}

From: Peng Fan peng.fan@nxp.com

Get the chip's market segment and speed grading from fuse and print them in boot log as other i.MX series.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx9/imx-regs.h | 3 + arch/arm/mach-imx/imx9/soc.c | 81 ++++++++++++++++++++++- 2 files changed, 83 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h index 065fd1f96de..76d241eab09 100644 --- a/arch/arm/include/asm/arch-imx9/imx-regs.h +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -48,6 +48,9 @@ #define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1) #define BCTRL_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0)

+#define MARKETING_GRADING_MASK GENMASK(5, 4) +#define SPEED_GRADING_MASK GENMASK(11, 6) + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> #include <stdbool.h> diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index dcabfe34aca..363dd39fc41 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -26,12 +26,15 @@ #include <env_internal.h> #include <errno.h> #include <fdt_support.h> +#include <imx_thermal.h> #include <linux/bitops.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <thermal.h> #include <asm/setup.h> #include <asm/bootm.h> #include <asm/arch-imx/cpu.h> #include <asm/mach-imx/s400_api.h> -#include <linux/delay.h> #include <fuse.h>

DECLARE_GLOBAL_DATA_PTR; @@ -73,6 +76,82 @@ int mmc_get_env_dev(void) } #endif

+/* + * SPEED_GRADE[5:4] SPEED_GRADE[3:0] MHz + * xx 0000 2300 + * xx 0001 2200 + * xx 0010 2100 + * xx 0011 2000 + * xx 0100 1900 + * xx 0101 1800 + * xx 0110 1700 + * xx 0111 1600 + * xx 1000 1500 + * xx 1001 1400 + * xx 1010 1300 + * xx 1011 1200 + * xx 1100 1100 + * xx 1101 1000 + * xx 1110 900 + * xx 1111 800 + */ +u32 get_cpu_speed_grade_hz(void) +{ + u32 speed, max_speed; + u32 val; + + fuse_read(2, 3, &val); + val = FIELD_GET(SPEED_GRADING_MASK, val) & 0xF; + + speed = MHZ(2300) - val * MHZ(100); + + if (is_imx93()) + max_speed = MHZ(1700); + + /* In case the fuse of speed grade not programmed */ + if (speed > max_speed) + speed = max_speed; + + return speed; +} + +/* + * `00` - Consumer 0C to 95C + * `01` - Ext. Consumer -20C to 105C + * `10` - Industrial -40C to 105C + * `11` - Automotive -40C to 125C + */ +u32 get_cpu_temp_grade(int *minc, int *maxc) +{ + u32 val; + + fuse_read(2, 3, &val); + val = FIELD_GET(MARKETING_GRADING_MASK, val); + + if (minc && maxc) { + if (val == TEMP_AUTOMOTIVE) { + *minc = -40; + *maxc = 125; + } else if (val == TEMP_INDUSTRIAL) { + *minc = -40; + *maxc = 105; + } else if (val == TEMP_EXTCOMMERCIAL) { + if (is_imx93()) { + /* imx93 only has extended industrial*/ + *minc = -40; + *maxc = 125; + } else { + *minc = -20; + *maxc = 105; + } + } else { + *minc = 0; + *maxc = 95; + } + } + return val; +} + static void set_cpu_info(struct sentinel_get_info_data *info) { gd->arch.soc_rev = info->soc;

From: Peng Fan peng.fan@nxp.com

The HW_CTRL_SEL should be cleared when configuring PLL to avoid potential glitch

Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/clock.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index a5f95fbcb8a..38e4cbbcc37 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -206,6 +206,9 @@ int configure_intpll(enum ccm_clk_src pll, u32 freq) return -EPERM; }

+ /* Clear PLL HW CTRL SEL */ + setbits_le32(&reg->ctrl.reg_clr, PLL_CTRL_HW_CTRL_SEL); + /* Bypass the PLL to ref */ writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_set);

From: Peng Fan peng.fan@nxp.com

Add CONFIG_IMX9_LOW_DRIVE_MODE in imx9 clk, later we will add board support

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/Kconfig | 5 ++++ arch/arm/mach-imx/imx9/clock.c | 55 +++++++++++++++++++++++++++++++--- 2 files changed, 56 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index c06102bae07..c51f80f311a 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -5,6 +5,11 @@ config AHAB_BOOT help This option enables the support for AHAB secure boot.

+config IMX9_LOW_DRIVE_MODE + bool "Configure to i.MX9 low drive mode" + help + This option enables the settings for iMX9 low drive mode. + config IMX9 bool select HAS_CAAM diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 38e4cbbcc37..3faab0685f7 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -601,21 +601,27 @@ void init_uart_clk(u32 index)

void init_clk_usdhc(u32 index) { - /* 400 Mhz */ + u32 div; + + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + div = 3; /* 266.67 Mhz */ + else + div = 2; /* 400 Mhz */ + switch (index) { case 0: ccm_lpcg_on(CCGR_USDHC1, 0); - ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, 2); + ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, div); ccm_lpcg_on(CCGR_USDHC1, 1); break; case 1: ccm_lpcg_on(CCGR_USDHC2, 0); - ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, 2); + ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, div); ccm_lpcg_on(CCGR_USDHC2, 1); break; case 2: ccm_lpcg_on(CCGR_USDHC3, 0); - ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, 2); + ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, div); ccm_lpcg_on(CCGR_USDHC3, 1); break; default: @@ -681,8 +687,45 @@ void set_arm_clk(ulong freq) ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); }

+void set_arm_core_max_clk(void) +{ + /* Increase ARM clock to max rate according to speed grade */ + u32 speed = get_cpu_speed_grade_hz(); + + set_arm_clk(speed); +} + #endif

+#if IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE) +struct imx_clk_setting imx_clk_settings[] = { + /* Set A55 clk to 500M */ + {ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2}, + /* Set A55 periphal to 200M */ + {ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD1, 4}, + /* Set A55 mtr bus to 133M */ + {ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, + + /* Sentinel to 133M */ + {SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, + /* Bus_wakeup to 133M */ + {BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, + /* Bus_AON to 133M */ + {BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, + /* M33 to 133M */ + {M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, + /* WAKEUP_AXI to 200M */ + {WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD1, 4}, + /* SWO TRACE to 133M */ + {SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, + /* M33 systetick to 24M */ + {M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1}, + /* NIC to 250M */ + {NIC_CLK_ROOT, SYS_PLL_PFD0, 4}, + /* NIC_APB to 133M */ + {NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3} +}; +#else struct imx_clk_setting imx_clk_settings[] = { /* Set A55 periphal to 333M */ {ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3}, @@ -710,6 +753,7 @@ struct imx_clk_setting imx_clk_settings[] = { /* NIC_APB to 133M */ {NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3} }; +#endif

int clock_init(void) { @@ -720,6 +764,9 @@ int clock_init(void) imx_clk_settings[i].src, imx_clk_settings[i].div); }

+ if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + set_arm_clk(MHZ(900)); + /* allow for non-secure access */ for (i = 0; i < OSCPLL_END; i++) ccm_clk_src_tz_access(i, true, false, false);

From: Peng Fan peng.fan@nxp.com

Config the A55 alt root clock to 500MHz(LD mode frequency) by default. Normally, this clock root is only used as an intermediate clock soure for A55 core/dsu when change the ARM PLL frequency.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/clock.c | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 3faab0685f7..957f80fce2e 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -727,6 +727,12 @@ struct imx_clk_setting imx_clk_settings[] = { }; #else struct imx_clk_setting imx_clk_settings[] = { + /* + * Set A55 clk to 500M. This clock root is normally used as intermediate + * clock source for A55 core/DSU when doing ARM PLL reconfig. set it to + * 500MHz(LD mode frequency) should be ok. + */ + {ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2}, /* Set A55 periphal to 333M */ {ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3}, /* Set A55 mtr bus to 133M */

From: Peng Fan peng.fan@nxp.com

According to datasheet, iMX93 has fused parts with CORE1 or NPU or both disabled. So update code to support it, the kernel device tree runtime update will be added in future patches.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx/cpu.h | 7 +++++++ arch/arm/include/asm/mach-imx/sys_proto.h | 12 ++++++++++- arch/arm/mach-imx/imx9/soc.c | 25 ++++++++++++++++++++++- drivers/cpu/imx8_cpu.c | 14 +++++++++++++ 4 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index a666271fc11..cbd2717f97c 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -61,6 +61,13 @@ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_CPU_IMX93 0xC1 /* dummy ID */ +#define MXC_CPU_IMX9351 0xC2 /* dummy ID */ +#define MXC_CPU_IMX9332 0xC3 /* dummy ID */ +#define MXC_CPU_IMX9331 0xC4 /* dummy ID */ +#define MXC_CPU_IMX9322 0xC5 /* dummy ID */ +#define MXC_CPU_IMX9321 0xC6 /* dummy ID */ +#define MXC_CPU_IMX9312 0xC7 /* dummy ID */ +#define MXC_CPU_IMX9311 0xC8 /* dummy ID */

#define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 2eacddb51f5..85d9ca60b14 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -82,7 +82,17 @@ struct bd_info;

#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))

-#define is_imx93() (is_cpu_type(MXC_CPU_IMX93)) +#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331) || \ + is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \ + is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \ + is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311)) +#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351)) +#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332)) +#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331)) +#define is_imx9322() (is_cpu_type(MXC_CPU_IMX9322)) +#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321)) +#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312)) +#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311))

#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020)) #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050)) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 363dd39fc41..074df1e73cf 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -159,11 +159,34 @@ static void set_cpu_info(struct sentinel_get_info_data *info) memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32)); }

+static u32 get_cpu_variant_type(u32 type) +{ + /* word 19 */ + u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2)); + u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2)); + bool npu_disable = !!(val & BIT(13)); + bool core1_disable = !!(val & BIT(15)); + u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24); + + if ((val2 & pack_9x9_fused) == pack_9x9_fused) + type = MXC_CPU_IMX9322; + + if (npu_disable && core1_disable) + return type + 3; + else if (npu_disable) + return type + 2; + else if (core1_disable) + return type + 1; + + return type; +} + u32 get_cpu_rev(void) { u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;

- return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev); + return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) | + (CHIP_REV_1_0 + rev); }

#define UNLOCK_WORD 0xD928C520 /* unlock word */ diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 304d5e59013..98ff95f5ff5 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -39,6 +39,20 @@ static const char *get_imx_type_str(u32 imxtype) return "8QM"; case MXC_CPU_IMX93: return "93(52)";/* iMX93 Dual core with NPU */ + case MXC_CPU_IMX9351: + return "93(51)";/* iMX93 Single core with NPU */ + case MXC_CPU_IMX9332: + return "93(32)";/* iMX93 Dual core without NPU */ + case MXC_CPU_IMX9331: + return "93(31)";/* iMX93 Single core without NPU */ + case MXC_CPU_IMX9322: + return "93(22)";/* iMX93 9x9 Dual core */ + case MXC_CPU_IMX9321: + return "93(21)";/* iMX93 9x9 Single core */ + case MXC_CPU_IMX9312: + return "93(12)";/* iMX93 9x9 Dual core without NPU */ + case MXC_CPU_IMX9311: + return "93(11)";/* iMX93 9x9 Single core without NPU */ default: return "??"; }

From: Peng Fan peng.fan@nxp.com

The end brace should be in a new line

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/soc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 074df1e73cf..f91f838e41a 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -44,7 +44,8 @@ struct rom_api *g_rom_api = (struct rom_api *)0x1980; #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { - return devno; } + return devno; +}

int mmc_get_env_dev(void) {

From: Peng Fan peng.fan@nxp.com

There is no need to save gd with using the generic rom api function, so simplify code.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/soc.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index f91f838e41a..22152172169 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -49,15 +49,12 @@ __weak int board_mmc_get_env_dev(int devno)

int mmc_get_env_dev(void) { - volatile gd_t *pgd = gd; int ret; u32 boot; u16 boot_type; u8 boot_instance;

- ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, - ((uintptr_t)&boot) ^ QUERY_BT_DEV); - set_gd(pgd); + ret = rom_api_query_boot_infor(QUERY_BT_DEV, &boot);

if (ret != ROM_API_OKAY) { puts("ROMAPI: failure at query_boot_info\n");

From: Peng Fan peng.fan@nxp.com

Add a static u-boot config for i.MX93 low drive mode support. When low drive mode is enabled, VDD_SOC is set to 0.75V. Bus clocks, A55 core clock (900Mhz), DDR clock (1866MTS), and some peripherals clocks (USDHC/FLEXSPI/PDM/DISP_PIX/CAM_PIX) must decrease to meet max frequencies in low drive mode.

Also set standby voltage for buck1

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- board/freescale/imx93_evk/MAINTAINERS | 1 + board/freescale/imx93_evk/Makefile | 4 + board/freescale/imx93_evk/lpddr4x_timing_ld.c | 1496 +++++++++++++++++ board/freescale/imx93_evk/spl.c | 26 +- configs/imx93_11x11_evk_ld_defconfig | 121 ++ 5 files changed, 1642 insertions(+), 6 deletions(-) create mode 100644 board/freescale/imx93_evk/lpddr4x_timing_ld.c create mode 100644 configs/imx93_11x11_evk_ld_defconfig

diff --git a/board/freescale/imx93_evk/MAINTAINERS b/board/freescale/imx93_evk/MAINTAINERS index 389f17ae1e4..8ca4646f20f 100644 --- a/board/freescale/imx93_evk/MAINTAINERS +++ b/board/freescale/imx93_evk/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/imx93_evk/ F: include/configs/imx93_evk.h F: configs/imx93_11x11_evk_defconfig + configs/imx93_11x11_evk_ld_defconfig diff --git a/board/freescale/imx93_evk/Makefile b/board/freescale/imx93_evk/Makefile index 575f8e94604..17956d24bf7 100644 --- a/board/freescale/imx93_evk/Makefile +++ b/board/freescale/imx93_evk/Makefile @@ -8,5 +8,9 @@ obj-y += imx93_evk.o

ifdef CONFIG_SPL_BUILD obj-y += spl.o +ifdef CONFIG_IMX9_LOW_DRIVE_MODE +obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing_ld.o +else obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o endif +endif diff --git a/board/freescale/imx93_evk/lpddr4x_timing_ld.c b/board/freescale/imx93_evk/lpddr4x_timing_ld.c new file mode 100644 index 00000000000..f080322f112 --- /dev/null +++ b/board/freescale/imx93_evk/lpddr4x_timing_ld.c @@ -0,0 +1,1496 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Generated code from IMX_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44140001 }, + { 0x4e301000, 0x0 }, + { 0x4e300000, 0x8000ff }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000512 }, + { 0x4e300084, 0x0 }, + { 0x4e300114, 0x2 }, + { 0x4e300260, 0x0 }, + { 0x4e30017c, 0x0 }, + { 0x4e300f04, 0x80 }, + { 0x4e300104, 0xaa77000e }, + { 0x4e300108, 0x1816b1aa }, + { 0x4e30010c, 0x5101e6 }, + { 0x4e300100, 0x12552100 }, + { 0x4e300160, 0x9002 }, + { 0x4e30016c, 0x30900000 }, + { 0x4e300250, 0x14 }, + { 0x4e300254, 0xaa00aa }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + { 0x4e300300, 0x11281109 }, + { 0x4e300304, 0xaa110a }, + { 0x4e300308, 0x620071e }, + { 0x4e300170, 0x8a0a0508 }, + { 0x4e300124, 0xe3c0000 }, + { 0x4e300804, 0x1f1f1f1f }, + { 0x4e301240, 0x0 }, + { 0x4e301244, 0x0 }, + { 0x4e301248, 0x0 }, + { 0x4e30124c, 0x0 }, + { 0x4e301250, 0x0 }, + { 0x4e301254, 0x0 }, + { 0x4e301258, 0x0 }, + { 0x4e30125c, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x4 }, + { 0x100a1, 0x5 }, + { 0x100a2, 0x6 }, + { 0x100a3, 0x7 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x1 }, + { 0x100a6, 0x2 }, + { 0x100a7, 0x3 }, + { 0x110a0, 0x3 }, + { 0x110a1, 0x2 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x1 }, + { 0x110a4, 0x7 }, + { 0x110a5, 0x6 }, + { 0x110a6, 0x4 }, + { 0x110a7, 0x5 }, + { 0x1005f, 0x5ff }, + { 0x1015f, 0x5ff }, + { 0x1105f, 0x5ff }, + { 0x1115f, 0x5ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x200c5, 0xb }, + { 0x2002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x2007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x20056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x10049, 0xe00 }, + { 0x10149, 0xe00 }, + { 0x11049, 0xe00 }, + { 0x11149, 0xe00 }, + { 0x43, 0x60 }, + { 0x1043, 0x60 }, + { 0x2043, 0x60 }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x2009b, 0x2 }, + { 0x20008, 0x1d3 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x10c }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x200fa, 0x2 }, + { 0x20019, 0x1 }, + { 0x200f0, 0x0 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x20021, 0x0 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x74a }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x1bb4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1f46 }, + { 0x5401c, 0x1708 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x1bb4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1f46 }, + { 0x54022, 0x1708 }, + { 0x54024, 0x6 }, + { 0x54032, 0xb400 }, + { 0x54033, 0x321b }, + { 0x54034, 0x4600 }, + { 0x54035, 0x81f }, + { 0x54036, 0x17 }, + { 0x54037, 0x600 }, + { 0x54038, 0xb400 }, + { 0x54039, 0x321b }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x81f }, + { 0x5403c, 0x17 }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x74a }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x2080 }, + { 0x54012, 0x110 }, + { 0x54019, 0x1bb4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1f46 }, + { 0x5401c, 0x1708 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x1bb4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1f46 }, + { 0x54022, 0x1708 }, + { 0x54024, 0x6 }, + { 0x54032, 0xb400 }, + { 0x54033, 0x321b }, + { 0x54034, 0x4600 }, + { 0x54035, 0x81f }, + { 0x54036, 0x17 }, + { 0x54037, 0x600 }, + { 0x54038, 0xb400 }, + { 0x54039, 0x321b }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x81f }, + { 0x5403c, 0x17 }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x30 }, + { 0x90051, 0x65a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x45a }, + { 0x90055, 0x9 }, + { 0x90056, 0x0 }, + { 0x90057, 0x448 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x179 }, + { 0x9005c, 0x1 }, + { 0x9005d, 0x618 }, + { 0x9005e, 0x109 }, + { 0x9005f, 0x40c0 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x8 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x4040 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x0 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x48 }, + { 0x9006b, 0x40 }, + { 0x9006c, 0x633 }, + { 0x9006d, 0x149 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x658 }, + { 0x90070, 0x109 }, + { 0x90071, 0x10 }, + { 0x90072, 0x4 }, + { 0x90073, 0x18 }, + { 0x90074, 0x0 }, + { 0x90075, 0x4 }, + { 0x90076, 0x78 }, + { 0x90077, 0x549 }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0xd49 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x159 }, + { 0x9007d, 0x94a }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x159 }, + { 0x90080, 0x441 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x42 }, + { 0x90084, 0x633 }, + { 0x90085, 0x149 }, + { 0x90086, 0x1 }, + { 0x90087, 0x633 }, + { 0x90088, 0x149 }, + { 0x90089, 0x0 }, + { 0x9008a, 0xe0 }, + { 0x9008b, 0x109 }, + { 0x9008c, 0xa }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x9 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x149 }, + { 0x90092, 0x9 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x159 }, + { 0x90095, 0x18 }, + { 0x90096, 0x10 }, + { 0x90097, 0x109 }, + { 0x90098, 0x0 }, + { 0x90099, 0x3c0 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x18 }, + { 0x9009c, 0x4 }, + { 0x9009d, 0x48 }, + { 0x9009e, 0x18 }, + { 0x9009f, 0x4 }, + { 0x900a0, 0x58 }, + { 0x900a1, 0xb }, + { 0x900a2, 0x10 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x1 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x5 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x1ff8 }, + { 0x900db, 0x85a8 }, + { 0x900dc, 0x1e8 }, + { 0x900dd, 0x50 }, + { 0x900de, 0x798 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x60 }, + { 0x900e1, 0x7a0 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x8 }, + { 0x900e4, 0x8310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0x8 }, + { 0x900e7, 0xa310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0xa }, + { 0x900ea, 0x408 }, + { 0x900eb, 0x169 }, + { 0x900ec, 0x6e }, + { 0x900ed, 0x0 }, + { 0x900ee, 0x68 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x408 }, + { 0x900f1, 0x169 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x8310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0xa310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x1ff8 }, + { 0x900f9, 0x85a8 }, + { 0x900fa, 0x1e8 }, + { 0x900fb, 0x68 }, + { 0x900fc, 0x798 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x78 }, + { 0x900ff, 0x7a0 }, + { 0x90100, 0x16a }, + { 0x90101, 0x68 }, + { 0x90102, 0x790 }, + { 0x90103, 0x16a }, + { 0x90104, 0x8 }, + { 0x90105, 0x8b10 }, + { 0x90106, 0x168 }, + { 0x90107, 0x8 }, + { 0x90108, 0xab10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0xa }, + { 0x9010b, 0x408 }, + { 0x9010c, 0x169 }, + { 0x9010d, 0x58 }, + { 0x9010e, 0x0 }, + { 0x9010f, 0x68 }, + { 0x90110, 0x0 }, + { 0x90111, 0x408 }, + { 0x90112, 0x169 }, + { 0x90113, 0x0 }, + { 0x90114, 0x8b10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x1 }, + { 0x90117, 0xab10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0x1d8 }, + { 0x9011b, 0x169 }, + { 0x9011c, 0x80 }, + { 0x9011d, 0x790 }, + { 0x9011e, 0x16a }, + { 0x9011f, 0x18 }, + { 0x90120, 0x7aa }, + { 0x90121, 0x6a }, + { 0x90122, 0xa }, + { 0x90123, 0x0 }, + { 0x90124, 0x1e9 }, + { 0x90125, 0x8 }, + { 0x90126, 0x8080 }, + { 0x90127, 0x108 }, + { 0x90128, 0xf }, + { 0x90129, 0x408 }, + { 0x9012a, 0x169 }, + { 0x9012b, 0xc }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x68 }, + { 0x9012e, 0x9 }, + { 0x9012f, 0x0 }, + { 0x90130, 0x1a9 }, + { 0x90131, 0x0 }, + { 0x90132, 0x408 }, + { 0x90133, 0x169 }, + { 0x90134, 0x0 }, + { 0x90135, 0x8080 }, + { 0x90136, 0x108 }, + { 0x90137, 0x8 }, + { 0x90138, 0x7aa }, + { 0x90139, 0x6a }, + { 0x9013a, 0x0 }, + { 0x9013b, 0x8568 }, + { 0x9013c, 0x108 }, + { 0x9013d, 0xb7 }, + { 0x9013e, 0x790 }, + { 0x9013f, 0x16a }, + { 0x90140, 0x1f }, + { 0x90141, 0x0 }, + { 0x90142, 0x68 }, + { 0x90143, 0x8 }, + { 0x90144, 0x8558 }, + { 0x90145, 0x168 }, + { 0x90146, 0xf }, + { 0x90147, 0x408 }, + { 0x90148, 0x169 }, + { 0x90149, 0xd }, + { 0x9014a, 0x0 }, + { 0x9014b, 0x68 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x408 }, + { 0x9014e, 0x169 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x8558 }, + { 0x90151, 0x168 }, + { 0x90152, 0x8 }, + { 0x90153, 0x3c8 }, + { 0x90154, 0x1a9 }, + { 0x90155, 0x3 }, + { 0x90156, 0x370 }, + { 0x90157, 0x129 }, + { 0x90158, 0x20 }, + { 0x90159, 0x2aa }, + { 0x9015a, 0x9 }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x104 }, + { 0x90164, 0x8 }, + { 0x90165, 0x448 }, + { 0x90166, 0x109 }, + { 0x90167, 0xf }, + { 0x90168, 0x7c0 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x0 }, + { 0x9016b, 0xe8 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x47 }, + { 0x9016e, 0x630 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0x618 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0xe0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0x7c8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0x8140 }, + { 0x9017b, 0x10c }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x478 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x69 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x0 }, + { 0x2000b, 0x20c }, + { 0x2000c, 0x74 }, + { 0x2000d, 0x48e }, + { 0x2000e, 0x2c }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x400fd, 0xf }, + { 0x400f1, 0xe }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P0 1866mts 2D */ + .drate = 1866, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1866, }, +}; diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 1aa2977b409..352ad79cb67 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -67,10 +67,23 @@ int power_init_board(void) /* BUCKxOUT_DVS0/1 control BUCK123 output */ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);

- /* 0.9v - */ - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) { + /* 0.75v for Low drive mode + */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c); + } else { + /* 0.9v for Over drive mode + */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + } + + /* set standby voltage to 0.65v */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);

/* I2C_LT_EN*/ pmic_reg_write(dev, 0xa, 0x3); @@ -103,10 +116,11 @@ void board_init_f(ulong dummy) printf("SOC: 0x%x\n", gd->arch.soc_rev); printf("LC: 0x%x\n", gd->arch.lifecycle); } + power_init_board();

- /* 1.7GHz */ - set_arm_clk(1700000000); + if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + set_arm_clk(get_cpu_speed_grade_hz());

/* Init power of mix */ soc_power_init(); diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig new file mode 100644 index 00000000000..caf17de3b10 --- /dev/null +++ b/configs/imx93_11x11_evk_ld_defconfig @@ -0,0 +1,121 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_TARGET_IMX93_11X11_EVK=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_IMX9_LOW_DRIVE_MODE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2051e000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x2051ddd0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x83200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_CPU_IMX=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y +CONFIG_LZO=y +CONFIG_BZIP2=y

From: Ye Li ye.li@nxp.com

Currently bootaux only supports to boot M33 core from TCM. Since ATF has changed to use x2 parameter for M33 image address, update the bootaux command to use input address, so we can support boot from any possilbe address like TCM, DDR, Flexspi NOR.

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/imx_bootaux.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c index 3b6662aeb81..256e6fa1c54 100644 --- a/arch/arm/mach-imx/imx9/imx_bootaux.c +++ b/arch/arm/mach-imx/imx9/imx_bootaux.c @@ -34,17 +34,13 @@ int arch_auxiliary_core_down(u32 core_id) int arch_auxiliary_core_up(u32 core_id, ulong addr) { struct arm_smccc_res res; - u32 stack, pc;

if (!addr) return -EINVAL;

- stack = *(u32 *)addr; - pc = *(u32 *)(addr + 4); + printf("## Starting auxiliary core addr = 0x%08lX...\n", addr);

- printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n", stack, pc); - - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, addr, 0, 0, 0, 0, 0, &res);

return 0; @@ -129,5 +125,5 @@ U_BOOT_CMD( "Start auxiliary core", "<address> [<core>]\n" " - start auxiliary core [<core>] (default 0),\n" - " at address <address>\n" + " at address <address> of auxiliary core view\n" );

From: Peng Fan peng.fan@nxp.com

Sync device tree with next-20230426

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 29 - arch/arm/dts/imx93-11x11-evk.dts | 385 +++---------- arch/arm/dts/imx93-pinfunc.h | 194 ++++--- arch/arm/dts/imx93.dtsi | 572 ++++++++++++-------- include/dt-bindings/clock/imx93-clock.h | 17 +- include/dt-bindings/power/fsl,imx93-power.h | 15 + include/dt-bindings/power/imx93-power.h | 12 - 7 files changed, 552 insertions(+), 672 deletions(-) create mode 100644 include/dt-bindings/power/fsl,imx93-power.h delete mode 100644 include/dt-bindings/power/imx93-power.h

diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi index 89e64344c6d..5b465e2dbd9 100644 --- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi +++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi @@ -10,25 +10,6 @@ bootph-pre-ram; };

- aliases { - usbgadget0 = &usbg1; - usbgadget1 = &usbg2; - }; - - usbg1: usbg1 { - compatible = "fsl,imx27-usb-gadget"; - dr_mode = "peripheral"; - chipidea,usb = <&usbotg1>; - status = "okay"; - }; - - usbg2: usbg2 { - compatible = "fsl,imx27-usb-gadget"; - dr_mode = "peripheral"; - chipidea,usb = <&usbotg2>; - status = "okay"; - }; - firmware { optee { compatible = "linaro,optee-tz"; @@ -141,16 +122,6 @@ reset-deassert-us = <100000>; };

-&usbotg1 { - status = "okay"; - extcon = <&ptn5110>; -}; - -&usbotg2 { - status = "okay"; - extcon = <&ptn5110_2>; -}; - &s4muap { bootph-pre-ram; status = "okay"; diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts index b3a5a3d71e2..4322cc3e11b 100644 --- a/arch/arm/dts/imx93-11x11-evk.dts +++ b/arch/arm/dts/imx93-11x11-evk.dts @@ -1,36 +1,25 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2021 NXP + * Copyright 2022 NXP */

/dts-v1/;

#include "imx93.dtsi"

-/{ +/ { + model = "NXP i.MX93 11X11 EVK board"; + compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; + chosen { stdout-path = &lpuart1; };

- reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - audio: audio@a4120000 { - compatible = "shared-dma-pool"; - reg = <0 0xa4120000 0 0x100000>; - no-map; - }; - }; - - reg_can2_stby: regulator-can2-stby { + reg_vref_1v8: regulator-adc-vref { compatible = "regulator-fixed"; - regulator-name = "can2-stby"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>; - enable-active-low; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; };

reg_usdhc2_vmmc: regulator-usdhc2 { @@ -43,81 +32,57 @@ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; enable-active-high; }; +};

- usdhc3_pwrseq: usdhc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; - }; - - reg_vref_1v8: regulator-adc-vref { - compatible = "regulator-fixed"; - regulator-name = "vref_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; +&adc1 { + vref-supply = <&reg_vref_1v8>; + status = "okay"; +};

+&mu1 { + status = "okay"; };

-&lpi2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_lpi2c1>; - pinctrl-1 = <&pinctrl_lpi2c1>; +&mu2 { status = "okay"; +};

- ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - reg = <0x50>; - interrupt-parent = <&pcal6524>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy1>; + status = "okay";

- port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>;

- typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(5000, 20000, 3000)>; - op-sink-microwatt = <15000000>; - self-powered; + ethphy1: ethernet-phy@1 { + reg = <1>; + eee-broken-1000t; }; }; +};

- ptn5110_2: tcpc@51 { - compatible = "nxp,ptn5110"; - reg = <0x51>; - interrupt-parent = <&pcal6524>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy2>; + fsl,magic-packet; + status = "okay";

- port { - typec2_dr_sw: endpoint { - remote-endpoint = <&usb2_drd_sw>; - }; - }; + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>;

- typec2_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(5000, 20000, 3000)>; - op-sink-microwatt = <15000000>; - self-powered; + ethphy2: ethernet-phy@2 { + reg = <2>; + eee-broken-1000t; }; }; }; @@ -134,15 +99,14 @@ pmic@25 { compatible = "nxp,pca9451a"; reg = <0x25>; - pinctrl-names = "default"; interrupt-parent = <&pcal6524>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>;

regulators { buck1: BUCK1 { regulator-name = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; @@ -189,22 +153,6 @@ regulator-always-on; };

- ldo2: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - ldo4: LDO4 { regulator-name = "LDO4"; regulator-min-microvolt = <800000>; @@ -250,48 +198,6 @@ status = "okay"; };

-&lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "disabled"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - disable-over-current; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usbotg2 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - disable-over-current; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb2_drd_sw: endpoint { - remote-endpoint = <&typec2_dr_sw>; - }; - }; -}; - &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -315,116 +221,17 @@ no-mmc; };

-&usdhc3 { - status = "disabled"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <&ethphy2>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy2: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - eee-broken-1000t; - rtl821x,aldps-disable; - rtl821x,clkout-disable; - }; - }; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <&ethphy1>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - eee-broken-1000t; - rtl821x,aldps-disable; - rtl821x,clkout-disable; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi>; - status = "disabled"; - - flash0: flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - }; -}; - &iomuxc { - pinctrl-names = "default"; - status = "okay"; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX93_PAD_GPIO_IO25__CAN2_TX 0x139e - MX93_PAD_GPIO_IO27__CAN2_RX 0x139e - >; - }; - - pinctrl_flexspi: flexspigrp { + pinctrl_lpi2c2: lpi2c2grp { fsl,pins = < - MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42 - MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x42 - MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42 - MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x42 - MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42 - MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42 - MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42 - MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42 - MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x42 - MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x42 - MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x42 - MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x42 + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e >; };

- pinctrl_fec: fecgrp { + pinctrl_pcal6524: pcal6524grp { fsl,pins = < - MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e - MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e - MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e - MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe - MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e - MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e - MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e - MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e - MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e - MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe - MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e >; };

@@ -447,23 +254,22 @@ >; };

- pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e - MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e - >; - }; - - pinctrl_lpi2c2: lpi2c2grp { - fsl,pins = < - MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e - MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e - >; - }; - - pinctrl_pcal6524: pcal6524grp { + pinctrl_fec: fecgrp { fsl,pins = < - MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e >; };

@@ -474,54 +280,43 @@ >; };

- pinctrl_uart2: uart2grp { - fsl,pins = < - MX93_PAD_UART2_TXD__LPUART2_TX 0x31e - MX93_PAD_UART2_RXD__LPUART2_RX 0x31e - >; - }; - pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe - MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe >; };

pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < - MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e >; };

pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e >; };

pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe - MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; }; - -&wdog3 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h index 7f0136c70b6..4298a145f8a 100644 --- a/arch/arm/dts/imx93-pinfunc.h +++ b/arch/arm/dts/imx93-pinfunc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright 2022 NXP */ @@ -10,57 +10,57 @@ * The pin function ID is a tuple of * <mux_reg conf_reg input_reg mux_mode input_val> */ -#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03E0 0x0 0x0 +#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0 -#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x03CC 0x5 0x0 -#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0438 0x6 0x0 -#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03E4 0x0 0x0 +#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0 -#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x03D0 0x5 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0 -#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03DC 0x0 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0 #define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0 #define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0 -#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x0434 0x6 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0 -#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x043C 0x6 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0 #define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03EC 0x1 0x0 +#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0 #define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x043C 0x5 0x1 -#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03F4 0x6 0x0 +#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1 +#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0 #define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 #define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E8 0x1 0x0 +#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0 #define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0438 0x5 0x1 -#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03F0 0x6 0x0 +#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1 +#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0 #define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 #define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0 #define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x0434 0x5 0x1 -#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03FC 0x6 0x0 +#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1 +#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0 #define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0 #define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0 #define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F8 0x6 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0 #define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0 #define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0 @@ -68,23 +68,23 @@ #define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03FC 0x6 0x1 +#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1 #define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0 #define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0440 0x2 0x0 +#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0 #define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F8 0x6 0x1 +#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1 #define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0 #define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x0444 0x2 0x0 +#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0 #define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x0404 0x6 0x0 +#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0 #define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0 #define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0 @@ -92,7 +92,7 @@ #define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x0400 0x6 0x0 +#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0 #define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0 #define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0 @@ -100,7 +100,7 @@ #define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x0404 0x6 0x1 +#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1 #define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0 #define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0 @@ -108,7 +108,7 @@ #define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x0400 0x6 0x1 +#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1 #define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0 #define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0 @@ -116,7 +116,7 @@ #define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x040C 0x6 0x0 +#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0 #define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0 #define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0 @@ -124,47 +124,47 @@ #define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0408 0x6 0x0 +#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0 #define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0 #define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0448 0x2 0x0 +#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0 #define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x040C 0x6 0x1 -#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0458 0x7 0x0 +#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1 +#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0 #define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x044C 0x2 0x0 +#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0 #define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0408 0x6 0x1 +#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1 #define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0 #define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x0424 0x1 0x0 +#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0 #define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0430 0x6 0x0 +#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0 #define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0 #define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0420 0x1 0x0 +#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0 #define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x042C 0x6 0x0 +#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0 #define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0 #define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0448 0x2 0x1 +#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1 #define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x041C 0x4 0x0 +#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0 #define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0428 0x6 0x0 +#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0 #define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0 #define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0 @@ -175,7 +175,7 @@ #define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0 #define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x0454 0x1 0x0 +#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0 #define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0 @@ -183,8 +183,8 @@ #define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0 #define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0458 0x1 0x1 -#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x044C 0x2 0x1 +#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1 +#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1 #define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0 @@ -192,7 +192,7 @@ #define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0 #define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0440 0x2 0x1 +#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1 #define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0 @@ -205,58 +205,58 @@ #define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0 -#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x0454 0x7 0x1 +#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1 #define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0460 0x1 0x0 -#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x045C 0x2 0x0 +#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0 +#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0 #define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03F4 0x6 0x1 +#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1 #define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0 #define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x0464 0x1 0x0 +#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0 #define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03F0 0x6 0x1 +#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1 #define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0 #define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0468 0x1 0x0 +#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0 #define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0 #define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x046C 0x1 0x0 +#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0 #define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03DC 0x5 0x1 +#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1 #define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0 #define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0470 0x1 0x0 -#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x0444 0x2 0x1 +#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0 +#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1 #define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03E0 0x5 0x1 +#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1 #define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0 #define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x0474 0x1 0x0 +#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0 #define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1 #define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03E4 0x5 0x1 +#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1 #define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0 #define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03EC 0x1 0x1 +#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1 #define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0 #define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E8 0x1 0x1 +#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1 #define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0 #define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0 #define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0 @@ -266,20 +266,19 @@ #define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1 #define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0 #define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0 -#define MX93_PAD_CCM_CLKO3__GPIO3_IO28 0x0090 0x0240 0x03CC 0x5 0x1 +#define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0 #define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0 #define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0 -#define MX93_PAD_CCM_CLKO4__GPIO3_IO29 0x0094 0x0244 0x03D0 0x5 0x1 +#define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0 #define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0 #define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0 -#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03D4 0x2 0x0 +#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0 #define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0 #define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0 #define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_MDC__LPUART5_RTS_B 0x0098 0x0248 0x0000 0x6 0x0 #define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0 #define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0 -#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D8 0x2 0x0 +#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0 #define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0 #define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0 #define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0 @@ -302,7 +301,7 @@ #define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0 #define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0 #define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x0424 0x1 0x1 +#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1 #define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0 #define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0 #define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0 @@ -323,21 +322,21 @@ #define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0420 0x1 0x1 +#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1 #define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x041C 0x1 0x1 -#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0410 0x3 0x0 +#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1 +#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0 #define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x0414 0x3 0x0 +#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0 #define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0 #define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0 -#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0418 0x3 0x0 +#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0 #define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0 #define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0 @@ -365,7 +364,7 @@ #define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0 #define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0 #define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0430 0x1 0x1 +#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1 #define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0 #define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0 #define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0 @@ -390,24 +389,24 @@ #define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x042C 0x1 0x1 +#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1 #define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0 #define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x045C 0x1 0x1 +#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1 #define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0 #define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0428 0x1 0x1 +#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1 #define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0 #define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0 #define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0 #define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0 -#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x045C 0x2 0x2 +#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2 #define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0 #define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0 @@ -457,43 +456,42 @@ #define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0 #define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0 #define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0 -#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0418 0x2 0x1 +#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1 #define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0 #define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0 #define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0 -#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0460 0x0 0x1 +#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1 #define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0 #define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1 #define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0 -#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x0464 0x0 0x1 +#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1 #define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0 #define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0 #define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0 -#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0468 0x0 0x1 +#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1 #define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0 #define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1 #define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0 -#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x046C 0x0 0x1 +#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1 #define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0 #define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1 #define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0 -#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0470 0x0 0x1 +#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1 #define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0 #define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1 #define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0 -#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x0474 0x0 0x1 +#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1 #define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0 #define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1 #define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0 #define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0 #define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0 -#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03D4 0x2 0x1 +#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1 #define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1 #define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0 -#define MX93_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK 0x0150 0x0300 0x0000 0x6 0x0 #define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0 #define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0 -#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D8 0x2 0x1 +#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1 #define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1 #define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0 #define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0 @@ -523,34 +521,34 @@ #define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0 #define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0 #define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0 -#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0410 0x1 0x1 +#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1 #define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0 #define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1 #define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0 #define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0 #define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0 -#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x0414 0x1 0x1 +#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1 #define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1 #define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0 #define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0 -#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x0 0x0 +#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0 #define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0 #define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0 #define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0 #define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0 -#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x0 0x0 +#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0 #define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0 #define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0 #define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0 #define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0 -#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x0 0x0 +#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0 #define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0 #define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0 #define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0 #define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0 #define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0 #define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0 -#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x0 0x0 +#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0 #define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0 #define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0 #define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0 @@ -569,7 +567,7 @@ #define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0 #define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0 #define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0 -#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0450 0x4 0x0 +#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0 #define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0 #define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0 #define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0 @@ -581,14 +579,14 @@ #define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0 #define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0 #define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0 -#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0440 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2 #define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0 #define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0 #define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0 #define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0 #define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0 #define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0 -#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x0444 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2 #define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0 #define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0 #define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0 @@ -614,7 +612,7 @@ #define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0 #define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0 #define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0 -#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0450 0x1 0x1 +#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1 #define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0 #define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0 #define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0 diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi index 28026ccecc8..73ecd953ec8 100644 --- a/arch/arm/dts/imx93.dtsi +++ b/arch/arm/dts/imx93.dtsi @@ -1,15 +1,13 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2021 NXP + * Copyright 2022 NXP */

#include <dt-bindings/clock/imx93-clock.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/thermal/thermal.h> -#include <dt-bindings/power/imx93-power.h> -#include <dt-bindings/usb/pd.h> +#include <dt-bindings/power/fsl,imx93-power.h>

#include "imx93-pinfunc.h"

@@ -23,11 +21,17 @@ gpio1 = &gpio2; gpio2 = &gpio3; gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; - ethernet0 = &fec; - ethernet1 = &eqos; serial0 = &lpuart1; serial1 = &lpuart2; serial2 = &lpuart3; @@ -36,14 +40,6 @@ serial5 = &lpuart6; serial6 = &lpuart7; serial7 = &lpuart8; - i2c0 = &lpi2c1; - i2c1 = &lpi2c2; - i2c2 = &lpi2c3; - i2c3 = &lpi2c4; - i2c4 = &lpi2c5; - i2c5 = &lpi2c6; - usb0 = &usbotg1; - usb1 = &usbotg2; };

cpus { @@ -89,6 +85,11 @@ clock-output-names = "clk_ext1"; };

+ pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -129,46 +130,53 @@ #size-cells = <1>; ranges;

+ anomix_ns_gpr: syscon@44210000 { + compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; + reg = <0x44210000 0x1000>; + }; + mu1: mailbox@44230000 { compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; reg = <0x44230000 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MU1_B_GATE>; #mbox-cells = <2>; status = "disabled"; };

- anomix_ns_gpr: blk-ctrl-anomix@42420000 { - compatible = "syscon"; - reg = <0x44210000 0x1000>; - }; - system_counter: timer@44290000 { compatible = "nxp,sysctr-timer"; reg = <0x44290000 0x30000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc_24m>; clock-names = "per"; + nxp,no-divider; };

- i3c1: i3c-master@44330000 { - #address-cells = <3>; - #size-cells = <0>; - compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; - reg = <0x44330000 0x10000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_I3C1_GATE>, - <&clk IMX93_CLK_I3C1_GATE>, - <&clk IMX93_CLK_DUMMY>; - clock-names = "pclk", "fast_clk", "slow_clk"; + tpm1: pwm@44310000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44310000 0x1000>; + clocks = <&clk IMX93_CLK_TPM1_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm2: pwm@44320000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44320000 0x10000>; + clocks = <&clk IMX93_CLK_TPM2_GATE>; + #pwm-cells = <3>; status = "disabled"; };

lpi2c1: i2c@44340000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x44340000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C1_GATE>, - <&clk IMX93_CLK_LPI2C1_GATE>; + <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; status = "disabled"; }; @@ -176,9 +184,11 @@ lpi2c2: i2c@44350000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x44350000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C2_GATE>, - <&clk IMX93_CLK_LPI2C2_GATE>; + <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; status = "disabled"; }; @@ -190,7 +200,7 @@ reg = <0x44360000 0x10000>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPSPI1_GATE>, - <&clk IMX93_CLK_LPSPI1_GATE>; + <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; status = "disabled"; }; @@ -202,14 +212,13 @@ reg = <0x44370000 0x10000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPSPI2_GATE>, - <&clk IMX93_CLK_LPSPI2_GATE>; + <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; status = "disabled"; };

lpuart1: serial@44380000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", - "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x44380000 0x1000>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART1_GATE>; @@ -218,8 +227,7 @@ };

lpuart2: serial@44390000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", - "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x44390000 0x1000>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART2_GATE>; @@ -227,9 +235,40 @@ status = "disabled"; };

+ flexcan1: can@443a0000 { + compatible = "fsl,imx93-flexcan"; + reg = <0x443a0000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_CAN1_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + iomuxc: pinctrl@443c0000 { compatible = "fsl,imx93-iomuxc"; reg = <0x443c0000 0x10000>; + status = "okay"; + }; + + bbnsm: bbnsm@44440000 { + compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; + reg = <0x44440000 0x10000>; + + bbnsm_rtc: rtc { + compatible = "nxp,imx93-bbnsm-rtc"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + }; + + bbnsm_pwrkey: pwrkey { + compatible = "nxp,imx93-bbnsm-pwrkey"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + linux,code = <KEY_POWER>; + }; };

clk: clock-controller@44450000 { @@ -238,11 +277,33 @@ #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; clock-names = "osc_32k", "osc_24m", "clk_ext1"; - assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; - assigned-clock-rates = <393216000>; status = "okay"; };

+ src: system-controller@44460000 { + compatible = "fsl,imx93-src", "syscon"; + reg = <0x44460000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mediamix: power-domain@44462400 { + compatible = "fsl,imx93-src-slice"; + reg = <0x44462400 0x400>, <0x44465800 0x400>; + #power-domain-cells = <0>; + clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + }; + + mlmix: power-domain@44461800 { + compatible = "fsl,imx93-src-slice"; + reg = <0x44461800 0x400>, <0x44464800 0x400>; + #power-domain-cells = <0>; + clocks = <&clk IMX93_CLK_ML_APB>, + <&clk IMX93_CLK_ML>; + }; + }; + anatop: anatop@44480000 { compatible = "fsl,imx93-anatop", "syscon"; reg = <0x44480000 0x10000>; @@ -252,11 +313,12 @@ compatible = "nxp,imx93-adc"; reg = <0x44530000 0x10000>; interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_ADC1_GATE>; clock-names = "ipg"; + #io-channel-cells = <1>; status = "disabled"; }; }; @@ -268,8 +330,8 @@ #size-cells = <1>; ranges;

- wakeupmix_gpr: blk-ctrl-wakeupmix@42420000 { - compatible = "syscon"; + wakeupmix_gpr: syscon@42420000 { + compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; reg = <0x42420000 0x1000>; };

@@ -277,6 +339,7 @@ compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; reg = <0x42440000 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MU2_B_GATE>; #mbox-cells = <2>; status = "disabled"; }; @@ -287,39 +350,48 @@ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_WDOG3_GATE>; timeout-sec = <40>; + }; + + tpm3: pwm@424e0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424e0000 0x1000>; + clocks = <&clk IMX93_CLK_TPM3_GATE>; + #pwm-cells = <3>; status = "disabled"; };

tpm4: pwm@424f0000 { compatible = "fsl,imx7ulp-pwm"; - reg = <0x424f0000 0x1000>; + reg = <0x424f0000 0x10000>; clocks = <&clk IMX93_CLK_TPM4_GATE>; - assigned-clocks = <&clk IMX93_CLK_TPM4>; - assigned-clock-parents = <&clk IMX93_CLK_24M>; - assigned-clock-rates = <24000000>; #pwm-cells = <3>; status = "disabled"; };

- i3c2: i3c-master@42520000 { - #address-cells = <3>; - #size-cells = <0>; - compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; - reg = <0x42520000 0x10000>; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_I3C2_GATE>, - <&clk IMX93_CLK_I3C2_GATE>, - <&clk IMX93_CLK_DUMMY>; - clock-names = "pclk", "fast_clk", "slow_clk"; + tpm5: pwm@42500000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42500000 0x10000>; + clocks = <&clk IMX93_CLK_TPM5_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm6: pwm@42510000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42510000 0x10000>; + clocks = <&clk IMX93_CLK_TPM6_GATE>; + #pwm-cells = <3>; status = "disabled"; };

lpi2c3: i2c@42530000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x42530000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C3_GATE>, - <&clk IMX93_CLK_LPI2C3_GATE>; + <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; @@ -327,9 +399,11 @@ lpi2c4: i2c@42540000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x42540000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C4_GATE>, - <&clk IMX93_CLK_LPI2C4_GATE>; + <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; @@ -341,7 +415,7 @@ reg = <0x42550000 0x10000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPSPI3_GATE>, - <&clk IMX93_CLK_LPSPI3_GATE>; + <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; @@ -353,14 +427,13 @@ reg = <0x42560000 0x10000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPSPI4_GATE>, - <&clk IMX93_CLK_LPSPI4_GATE>; + <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; };

lpuart3: serial@42570000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", - "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42570000 0x1000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART3_GATE>; @@ -369,8 +442,7 @@ };

lpuart4: serial@42580000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", - "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42580000 0x1000>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART4_GATE>; @@ -379,8 +451,7 @@ };

lpuart5: serial@42590000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", - "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42590000 0x1000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART5_GATE>; @@ -389,8 +460,7 @@ };

lpuart6: serial@425a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", - "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x425a0000 0x1000>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART6_GATE>; @@ -398,22 +468,37 @@ status = "disabled"; };

- flexspi: spi@425e0000 { - #address-cells = <1>; - #size-cells = <0>; + flexcan2: can@425b0000 { + compatible = "fsl,imx93-flexcan"; + reg = <0x425b0000 0x10000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_CAN2_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + flexspi1: spi@425e0000 { compatible = "nxp,imx8mm-fspi"; reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; + #address-cells = <1>; + #size-cells = <0>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>; - clock-names = "fspi", "fspi_en"; + clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, + <&clk IMX93_CLK_FLEXSPI1_GATE>; + clock-names = "fspi_en", "fspi"; + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; status = "disabled"; };

lpuart7: serial@42690000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", - "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42690000 0x1000>; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART7_GATE>; @@ -422,8 +507,7 @@ };

lpuart8: serial@426a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", - "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x426a0000 0x1000>; interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART8_GATE>; @@ -434,9 +518,11 @@ lpi2c5: i2c@426b0000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x426b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C5_GATE>, - <&clk IMX93_CLK_LPI2C5_GATE>; + <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; @@ -444,12 +530,87 @@ lpi2c6: i2c@426c0000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x426c0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPI2C6_GATE>, - <&clk IMX93_CLK_LPI2C6_GATE>; + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c7: i2c@426d0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426d0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C7_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c8: i2c@426e0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426e0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C8_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi5: spi@426f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x426f0000 0x10000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI5_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42700000 0x10000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI6_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; status = "disabled"; }; + + lpspi7: spi@42710000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42710000 0x10000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI7_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42720000 0x10000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI8_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + };

aips3: bus@42800000 { @@ -463,8 +624,8 @@ compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; reg = <0x42850000 0x10000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>, + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC1_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <8>; @@ -477,8 +638,8 @@ compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; reg = <0x42860000 0x10000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>, + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC2_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; @@ -487,15 +648,37 @@ status = "disabled"; };

+ eqos: ethernet@428a0000 { + compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x428a0000 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, + <&clk IMX93_CLK_ENET_QOS_GATE>, + <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>, + <&clk IMX93_CLK_ENET_QOS_GATE>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; + intf_mode = <&wakeupmix_gpr 0x28>; + snps,clk-csr = <0>; + status = "disabled"; + }; + fec: ethernet@42890000 { - compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec"; + compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x42890000 0x10000>; interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_WAKEUP_AXI>, + clocks = <&clk IMX93_CLK_ENET1_GATE>, + <&clk IMX93_CLK_ENET1_GATE>, <&clk IMX93_CLK_ENET_TIMER1>, <&clk IMX93_CLK_ENET_REF>, <&clk IMX93_CLK_ENET_REF_PHY>; @@ -510,29 +693,6 @@ assigned-clock-rates = <100000000>, <250000000>, <50000000>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; - fsl,wakeup_irq = <2>; - status = "disabled"; - }; - - eqos: ethernet@428a0000 { - compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; - reg = <0x428a0000 0x10000>; - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "eth_wake_irq", "macirq"; - clocks = <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>, - <&clk IMX93_CLK_WAKEUP_AXI>; - clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; - assigned-clock-rates = <100000000>, <250000000>; - intf_mode = <&wakeupmix_gpr 0x28>; - clk_csr = <0>; status = "disabled"; };

@@ -540,8 +700,8 @@ compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; reg = <0x428b0000 0x10000>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>, + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC3_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; @@ -551,138 +711,90 @@ }; };

- gpio2: gpio@43810000 { - compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; - reg = <0x43810080 0x1000>, <0x43810040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 32 32>; - }; - - gpio3: gpio@43820000 { - compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; - reg = <0x43820080 0x1000>, <0x43820040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 64 32>; + gpio2: gpio@43810080 { + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43810080 0x1000>, <0x43810040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX93_CLK_GPIO2_GATE>, + <&clk IMX93_CLK_GPIO2_GATE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc 0 4 30>; };

- gpio4: gpio@43830000 { - compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; - reg = <0x43830080 0x1000>, <0x43830040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 96 32>; + gpio3: gpio@43820080 { + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43820080 0x1000>, <0x43820040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX93_CLK_GPIO3_GATE>, + <&clk IMX93_CLK_GPIO3_GATE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, + <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; };

- gpio1: gpio@47400000 { - compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; - reg = <0x47400080 0x1000>, <0x47400040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 0 32>; + gpio4: gpio@43830080 { + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43830080 0x1000>, <0x43830040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX93_CLK_GPIO4_GATE>, + <&clk IMX93_CLK_GPIO4_GATE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; };

- ocotp: efuse@47510000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx93-ocotp", "syscon"; - reg = <0x47510000 0x1000>; - status = "disabled"; + gpio1: gpio@47400080 { + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; + reg = <0x47400080 0x1000>, <0x47400040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX93_CLK_GPIO1_GATE>, + <&clk IMX93_CLK_GPIO1_GATE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc 0 92 16>; };

- s4muap: s4muap@47520000 { + s4muap: mailbox@47520000 { compatible = "fsl,imx93-mu-s4"; reg = <0x47520000 0x10000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "txirq", "rxirq"; + interrupt-names = "tx", "rx"; #mbox-cells = <2>; - status = "okay"; };

- sentnl_mu: sentnl-mu { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx-sentnl"; - mboxes = <&s4muap 0 0 &s4muap 1 0>; - mbox-names = "tx", "rx"; - fsl,sentnl_mu_id = <2>; - fsl,sentnl_mu_max_users = <4>; - status = "okay"; - dma-ranges = <0x80000000 0x80000000 0x20000000>; - }; - - ddr-pmu@4e300e00 { - compatible = "fsl,imx93-ddr-pmu"; - reg = <0x4e300dc0 0x200>; /* _dc0 ~ _eb8 */ - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; - clock-names = "main_clk"; - }; - - usbotg1: usb@4c100000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; - reg = <0x4c100000 0x200>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; - clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; - assigned-clock-parents = <&clk IMX93_CLK_HSIO>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - status = "disabled"; - }; - - usbmisc1: usbmisc@4c100200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x4c100200 0x200>; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; - clock-names = "main_clk"; - }; - - usbotg2: usb@4c200000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; - reg = <0x4c200000 0x200>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; - clock-names = "usb2_ctrl_root_clk"; - assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; - assigned-clock-parents = <&clk IMX93_CLK_HSIO>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; + media_blk_ctrl: system-controller@4ac10000 { + compatible = "fsl,imx93-media-blk-ctrl", "syscon"; + reg = <0x4ac10000 0x10000>; + power-domains = <&mediamix>; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_PXP_GATE>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>; + clock-names = "apb", "axi", "nic", "disp", "cam", + "pxp", "lcdif", "isi", "csi", "dsi"; + #power-domain-cells = <1>; status = "disabled"; }; - - usbmisc2: usbmisc@4c200200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x4c200200 0x200>; - }; }; }; diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h index 4ea6864b418..8e02859d8ce 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ /* - * Copyright 2021 NXP + * Copyright 2022 NXP */

#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H @@ -28,13 +28,9 @@ #define IMX93_CLK_M33_SYSTICK 19 #define IMX93_CLK_FLEXIO1 20 #define IMX93_CLK_FLEXIO2 21 -#define IMX93_CLK_LPIT1 22 -#define IMX93_CLK_LPIT2 23 #define IMX93_CLK_LPTMR1 24 #define IMX93_CLK_LPTMR2 25 -#define IMX93_CLK_TPM1 26 #define IMX93_CLK_TPM2 27 -#define IMX93_CLK_TPM3 28 #define IMX93_CLK_TPM4 29 #define IMX93_CLK_TPM5 30 #define IMX93_CLK_TPM6 31 @@ -197,7 +193,12 @@ #define IMX93_CLK_PMRO_GATE 188 #define IMX93_CLK_32K 189 #define IMX93_CLK_SAI1_IPG 190 -#define IMX93_CLK_SAI2_IPG 191 -#define IMX93_CLK_SAI3_IPG 192 -#define IMX93_CLK_END 193 +#define IMX93_CLK_SAI2_IPG 191 +#define IMX93_CLK_SAI3_IPG 192 +#define IMX93_CLK_MU1_A_GATE 193 +#define IMX93_CLK_MU1_B_GATE 194 +#define IMX93_CLK_MU2_A_GATE 195 +#define IMX93_CLK_MU2_B_GATE 196 +#define IMX93_CLK_END 197 + #endif diff --git a/include/dt-bindings/power/fsl,imx93-power.h b/include/dt-bindings/power/fsl,imx93-power.h new file mode 100644 index 00000000000..17f9f015bf7 --- /dev/null +++ b/include/dt-bindings/power/fsl,imx93-power.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DT_BINDINGS_IMX93_POWER_H__ +#define __DT_BINDINGS_IMX93_POWER_H__ + +#define IMX93_MEDIABLK_PD_MIPI_DSI 0 +#define IMX93_MEDIABLK_PD_MIPI_CSI 1 +#define IMX93_MEDIABLK_PD_PXP 2 +#define IMX93_MEDIABLK_PD_LCDIF 3 +#define IMX93_MEDIABLK_PD_ISI 4 + +#endif diff --git a/include/dt-bindings/power/imx93-power.h b/include/dt-bindings/power/imx93-power.h deleted file mode 100644 index 4e27a2e2809..00000000000 --- a/include/dt-bindings/power/imx93-power.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2021 NXP - */ - -#ifndef __DT_BINDINGS_IMX93_POWER_H__ -#define __DT_BINDINGS_IMX93_POWER_H__ - -#define IMX93_POWER_DOMAIN_MLMIX 0 -#define IMX93_POWER_DOMAIN_MEDIAMIX 1 - -#endif

From: Peng Fan peng.fan@nxp.com

Add tmu nodes and thermal zone

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/dts/imx93.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)

diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi index 73ecd953ec8..13cf32d4b27 100644 --- a/arch/arm/dts/imx93.dtsi +++ b/arch/arm/dts/imx93.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/fsl,imx93-power.h> +#include <dt-bindings/thermal/thermal.h>

#include "imx93-pinfunc.h"

@@ -116,6 +117,38 @@ interrupt-parent = <&gic>; };

+ thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -309,6 +342,21 @@ reg = <0x44480000 0x10000>; };

+ tmu: tmu@44482000 { + compatible = "fsl,imx93-tmu"; + reg = <0x44482000 0x1000>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + little-endian; + fsl,tmu-calibration = <0x0000000e 0x800000da + 0x00000029 0x800000e9 + 0x00000056 0x80000102 + 0x000000a2 0x8000012a + 0x00000116 0x80000166 + 0x00000195 0x800001a7 + 0x000001b2 0x800001b6>; + #thermal-sensor-cells = <1>; + }; + adc1: adc@44530000 { compatible = "nxp,imx93-adc"; reg = <0x44530000 0x10000>;

From: Ye Li ye.li@nxp.com

According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware.

Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values.

Signed-off-by: Ye Li ye.li@nxp.com Acked-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx9/ddr.h | 2 + drivers/ddr/imx/imx9/ddr_init.c | 122 +++++++++++++++++++++++++++ 2 files changed, 124 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h index 62e6f7dda53..8e4f946e5b0 100644 --- a/arch/arm/include/asm/arch-imx9/ddr.h +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -14,7 +14,9 @@ #define DDRMIX_BLK_CTRL_BASE 0x4E010000

#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24) +#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104) #define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110) +#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160) #define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)

#define SRC_BASE_ADDR (0x44460000) diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c index 8b8ec7f8de3..a1d953026f3 100644 --- a/drivers/ddr/imx/imx9/ddr_init.c +++ b/drivers/ddr/imx/imx9/ddr_init.c @@ -12,6 +12,13 @@ #include <asm/arch/sys_proto.h> #include <linux/delay.h>

+static unsigned int g_cdd_rr_max[4]; +static unsigned int g_cdd_rw_max[4]; +static unsigned int g_cdd_wr_max[4]; +static unsigned int g_cdd_ww_max[4]; + +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) + void ddrphy_coldreset(void) { /* dramphy_apb_n default 1 , assert -> 0, de_assert -> 1 */ @@ -74,8 +81,121 @@ void ddrc_config(struct dram_cfg_param *ddrc_config, int num) } }

+static unsigned int look_for_max(unsigned int data[], unsigned int addr_start, + unsigned int addr_end) +{ + unsigned int i, imax = 0; + + for (i = addr_start; i <= addr_end; i++) { + if (((data[i] >> 7) == 0) && data[i] > imax) + imax = data[i]; + } + + return imax; +} + void get_trained_CDD(u32 fsp) { + unsigned int i, tmp; + unsigned int cdd_cha[12], cdd_chb[12]; + unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max; + unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max; + + for (i = 0; i < 6; i++) { + tmp = dwc_ddrphy_apb_rd(0x54013 + i); + cdd_cha[i * 2] = tmp & 0xff; + cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff; + } + + for (i = 0; i < 7; i++) { + tmp = dwc_ddrphy_apb_rd(0x5402c + i); + + if (i == 0) { + cdd_chb[0] = (tmp >> 8) & 0xff; + } else if (i == 6) { + cdd_chb[11] = tmp & 0xff; + } else { + cdd_chb[i * 2 - 1] = tmp & 0xff; + cdd_chb[i * 2] = (tmp >> 8) & 0xff; + } + } + + cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1); + cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5); + cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9); + cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11); + cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1); + cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5); + cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9); + cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11); + g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max; + g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max; + g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max; + g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max; +} + +void update_umctl2_rank_space_setting(unsigned int pstat_num) +{ + u32 tmp, tmp_t; + + int wwt, rrt, wrt, rwt; + int ext_wwt, ext_rrt, ext_wrt, ext_rwt; + int max_wwt, max_rrt, max_wrt, max_rwt; + + /* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */ + tmp = readl(REG_DDR_TIMING_CFG_0); + wwt = (tmp >> 24) & 0x3; + rrt = (tmp >> 26) & 0x3; + wrt = (tmp >> 28) & 0x3; + rwt = (tmp >> 30) & 0x3; + + /* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from timing_cfg_4 */ + tmp_t = readl(REG_DDR_TIMING_CFG_4); + ext_wwt = (tmp >> 8) & 0x1; + ext_rrt = (tmp >> 10) & 0x1; + ext_wrt = (tmp >> 12) & 0x1; + ext_rwt = (tmp >> 14) & 0x3; + + wwt = (ext_wwt << 2) | wwt; + rrt = (ext_rrt << 2) | wwt; + wrt = (ext_wrt << 2) | wrt; + rwt = (ext_rwt << 2) | rwt; + + /* calculate the maximum between controller and cdd values */ + max_wwt = MAX(g_cdd_ww_max[0], wwt); + max_rrt = MAX(g_cdd_rr_max[0], rrt); + max_wrt = MAX(g_cdd_wr_max[0], wrt); + max_rwt = MAX(g_cdd_rw_max[0], rwt); + + /* verify values to see if are bigger then 7 or 15 (3 bits or 4 bits) */ + if (max_wwt > 7) + max_wwt = 7; + if (max_rrt > 7) + max_rrt = 7; + if (max_wrt > 7) + max_wrt = 7; + if (max_rwt > 15) + max_rwt = 15; + + /* recalculate timings for controller registers */ + wwt = max_wwt & 0x3; + rrt = max_rrt & 0x3; + wrt = max_wrt & 0x3; + rwt = max_rwt & 0x3; + + ext_wwt = (max_wwt & 0x4) >> 2; + ext_rrt = (max_rrt & 0x4) >> 2; + ext_wrt = (max_wrt & 0x4) >> 2; + ext_rwt = (max_rwt & 0xC) >> 2; + + /* update timing_cfg_0 and timing_cfg_4 */ + tmp = (tmp & 0x00ffffff) | (rwt << 30) | (wrt << 28) | + (rrt << 26) | (wwt << 24); + writel(tmp, REG_DDR_TIMING_CFG_0); + + tmp_t = (tmp_t & 0xFFFF2AFF) | (ext_rwt << 14) | + (ext_wrt << 12) | (ext_rrt << 10) | (ext_wwt << 8); + writel(tmp_t, REG_DDR_TIMING_CFG_4); }

int ddr_init(struct dram_timing_info *dram_timing) @@ -112,6 +232,8 @@ int ddr_init(struct dram_timing_info *dram_timing) ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); debug("DDRINFO: ddrc config done\n");

+ update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1); + #ifdef CONFIG_IMX9_DRAM_PM_COUNTER writel(0x200000, REG_DDR_DEBUG_19); #endif

From: Peng Fan peng.fan@nxp.com

As the ddr timing info will be saved at the last 16KB of the OCRAM, spl stack & bss base should be updated to avoid conflict.

Signed-off-by: Peng Fan peng.fan@nxp.com --- configs/imx93_11x11_evk_defconfig | 4 ++-- configs/imx93_11x11_evk_ld_defconfig | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index c2709f8c66c..cf240baae5b 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -15,7 +15,7 @@ CONFIG_TARGET_IMX93_11X11_EVK=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK=0x2051ddd0 +CONFIG_SPL_STACK=0x20519dd0 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 CONFIG_SPL_LOAD_IMX_CONTAINER=y @@ -30,7 +30,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2051e000 +CONFIG_SPL_BSS_START_ADDR=0x2051a000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig index caf17de3b10..ac8a23fcbf7 100644 --- a/configs/imx93_11x11_evk_ld_defconfig +++ b/configs/imx93_11x11_evk_ld_defconfig @@ -31,12 +31,12 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2051e000 +CONFIG_SPL_BSS_START_ADDR=0x2051a000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x2051ddd0 +CONFIG_SPL_STACK=0x20519dd0 CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x83200000

From: Jacky Bai ping.bai@nxp.com

change the ddr saved info to the last 16KB of the OCRAM.

Signed-off-by: Jacky Bai ping.bai@nxp.com Reviewed-by: Peng Fan peng.fan@nxp.com Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/ddr/imx/imx9/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig index 123ad173cfc..b1795eec353 100644 --- a/drivers/ddr/imx/imx9/Kconfig +++ b/drivers/ddr/imx/imx9/Kconfig @@ -22,6 +22,6 @@ config SAVED_DRAM_TIMING_BASE help after DRAM is trained, need to save the dram related timming info into memory for low power use. - default 0x204DC000 + default 0x2051C000

endmenu

From: Jacky Bai ping.bai@nxp.com

Add 625M bypass clock that may be used DRAM 625M bypass mode support.

Signed-off-by: Jacky Bai ping.bai@nxp.com Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/clock.c | 3 +++ drivers/ddr/imx/phy/ddrphy_utils.c | 3 +++ 2 files changed, 6 insertions(+)

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 957f80fce2e..a7ecccaf879 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -648,6 +648,9 @@ void dram_pll_init(ulong pll_val) void dram_enable_bypass(ulong clk_val) { switch (clk_val) { + case MHZ(625): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD2, 1); + break; case MHZ(400): ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2); break; diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index 6a8b6be42b2..fd8b4113b7b 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -148,6 +148,9 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(167)); dram_disable_bypass(); break; + case 625: + dram_enable_bypass(MHZ(625)); + break; case 400: dram_enable_bypass(MHZ(400)); break;