Hi Tom,

please pull these changes to your tree. The major part were clock issues we found for ZynqMP and Versal in some PM cases where u-boot didn't ask for enabling clocks. And that's why drivers are shared we also had to add clock enable function for Zynq to pass. There are some other fixes especially ZynqMP one for DTB selection.

I can't see any issue from gitlab CI.

Thanks, Michal

The following changes since commit fdcb93e1709ab1a2ebb562455621617c29e2099c:

Merge branch '2021-02-01-assorted-fixes' (2021-02-02 09:24:10 -0500)

are available in the Git repository at:

git@gitlab.denx.de:u-boot/custodians/u-boot-microblaze.git tags/xilinx-for-v2021.04-rc3

for you to fetch changes up to d9aa19efa8a6c20d51b7884de0a7f8dae3f835d2:

spi: zynqmp_gqspi: fix set_speed bug on multiple runs (2021-02-23 14:56:59 +0100)

---------------------------------------------------------------- Xilinx changes for v2021.04-rc3

qspi: - Support for dual/quad mode - Fix speed handling

clk: - Add clock enable function for zynq/zynqmp/versal

gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path

fpga: - Fix buffer alignment for ZynqMP

xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name

---------------------------------------------------------------- Brandon Maier (2): spi: zynqmp_gqspi: support dual and quad mode spi: zynqmp_gqspi: fix set_speed bug on multiple runs

Michael Walle (2): net: gem: unregister mdio bus if probe fails fpga: zynqpl: fix buffer alignment

Michal Simek (6): xilinx: common: Fix CONFIG_XILINX_OF_BOARD_DTB_ADDR handling for ZynqMP xilinx: Show silicon version in SPL arm64: zynqmp: Do not clear reset reason clk: zynq: Add dummy clock enable function net: gem: Fix error path in zynq_gem_probe arm64: zynqmp: Rename zc1275/zcu1275 to be aligned with DT name

T Karthik Reddy (4): clk: zynqmp: Add support to enable clocks clk: versal: Add support to enable clocks i2c: i2c_cdns: Enable i2c clock net: gem: Enable ethernet rx clock for versal

arch/arm/mach-zynqmp/include/mach/hardware.h | 4 +-- board/xilinx/common/board.c | 2 +- board/xilinx/zynq/board.c | 3 ++ board/xilinx/zynqmp/{zynqmp-zc1275-revA => zynqmp-zcu1275-revA} | 0 board/xilinx/zynqmp/{zynqmp-zc1275-revB => zynqmp-zcu1275-revB}/psu_init_gpl.c | 0 board/xilinx/zynqmp/zynqmp.c | 7 ++--- drivers/clk/clk_versal.c | 11 ++++++++ drivers/clk/clk_zynq.c | 10 +++++++ drivers/clk/clk_zynqmp.c | 49 ++++++++++++++++++++++++++++++++ drivers/fpga/zynqpl.c | 2 +- drivers/i2c/i2c-cdns.c | 7 +++++ drivers/mmc/zynq_sdhci.c | 2 +- drivers/net/zynq_gem.c | 47 +++++++++++++++++++++++-------- drivers/serial/serial_zynq.c | 2 +- drivers/spi/zynq_qspi.c | 2 +- drivers/spi/zynq_spi.c | 2 +- drivers/spi/zynqmp_gqspi.c | 189 ++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------------------------------------------------------------- drivers/watchdog/xilinx_wwdt.c | 3 +- 18 files changed, 208 insertions(+), 134 deletions(-) rename board/xilinx/zynqmp/{zynqmp-zc1275-revA => zynqmp-zcu1275-revA} (100%) rename board/xilinx/zynqmp/{zynqmp-zc1275-revB => zynqmp-zcu1275-revB}/psu_init_gpl.c (100%)