[U-Boot] [PATCH v1 0/3] imx: cpu.c, serial_mxc, dts fixes/improvements
This series addresses some shortcomings concerning reset cause in SPL, serial in DTE mode and fixes some device-tree address/size-cells warnings.
Marcel Ziswiler (1): ARM: dts: i.MX6Q, i.MX6QDL: fix address/size-cells warnings
Max Krummenacher (2): imx: serial_mxc: disable ri and dcd irq in dte mode imx: cpu.c: give access to reset cause in spl
arch/arm/dts/imx6q.dtsi | 4 ---- arch/arm/dts/imx6qdl.dtsi | 9 --------- arch/arm/mach-imx/cpu.c | 27 +++++++++++++++------------ drivers/serial/serial_mxc.c | 13 +++++++++---- 4 files changed, 24 insertions(+), 29 deletions(-)
From: Marcel Ziswiler marcel.ziswiler@toradex.com
This fixes the following warnings:
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /clocks: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/aips-bus@02100000/mipi@021e0000: unnecessary #address-cells/ #size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02400000/port@2: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02400000/port@3: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02800000/port@2: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02800000/port@3: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
---
arch/arm/dts/imx6q.dtsi | 4 ---- arch/arm/dts/imx6qdl.dtsi | 9 --------- 2 files changed, 13 deletions(-)
diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi index c30c8368ca..7f5d91d7f0 100644 --- a/arch/arm/dts/imx6q.dtsi +++ b/arch/arm/dts/imx6q.dtsi @@ -150,8 +150,6 @@ };
ipu2_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; reg = <2>;
ipu2_di0_disp0: disp0-endpoint { @@ -175,8 +173,6 @@ };
ipu2_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; reg = <3>;
ipu2_di1_hdmi: hdmi-endpoint { diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi index b13b0b2db8..476cf93445 100644 --- a/arch/arm/dts/imx6qdl.dtsi +++ b/arch/arm/dts/imx6qdl.dtsi @@ -49,9 +49,6 @@ };
clocks { - #address-cells = <1>; - #size-cells = <0>; - ckil { compatible = "fsl,imx-ckil", "fixed-clock"; #clock-cells = <0>; @@ -1125,8 +1122,6 @@ };
mipi_dsi: mipi@021e0000 { - #address-cells = <1>; - #size-cells = <0>; reg = <0x021e0000 0x4000>; status = "disabled";
@@ -1228,8 +1223,6 @@ };
ipu1_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; reg = <2>;
ipu1_di0_disp0: disp0-endpoint { @@ -1253,8 +1246,6 @@ };
ipu1_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; reg = <3>;
ipu1_di1_disp1: disp1-endpoint {
From: Marcel Ziswiler marcel.ziswiler@toradex.com This fixes the following warnings: arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /clocks: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/aips-bus@02100000/mipi@021e0000: unnecessary #address-cells/ #size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02400000/port@2: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02400000/port@3: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02800000/port@2: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02800000/port@3: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Max Krummenacher max.krummenacher@toradex.com
If the UART is used in DTE mode the RI and DCD bits in UCR3 become irq enable bits. Both are set to enabled after reset and both likely are pending.
Disable the bits to prevent an interrupt storm when Linux enables the UART interrupts.
Signed-off-by: Max Krummenacher max.krummenacher@toradex.com Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
---
drivers/serial/serial_mxc.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 7e4e6d36b8..df35ac9114 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -138,13 +138,18 @@ struct mxc_uart { u32 ts; };
-static void _mxc_serial_init(struct mxc_uart *base) +static void _mxc_serial_init(struct mxc_uart *base, int use_dte) { writel(0, &base->cr1); writel(0, &base->cr2);
while (!(readl(&base->cr2) & UCR2_SRST));
+ if (use_dte) + writel(0x404 | UCR3_ADNIMP, &base->cr3); + else + writel(0x704 | UCR3_ADNIMP, &base->cr3); + writel(0x704 | UCR3_ADNIMP, &base->cr3); writel(0x8000, &base->cr4); writel(0x2b, &base->esc); @@ -226,7 +231,7 @@ static int mxc_serial_tstc(void) */ static int mxc_serial_init(void) { - _mxc_serial_init(mxc_base); + _mxc_serial_init(mxc_base, false);
serial_setbrg();
@@ -271,7 +276,7 @@ static int mxc_serial_probe(struct udevice *dev) { struct mxc_serial_platdata *plat = dev->platdata;
- _mxc_serial_init(plat->reg); + _mxc_serial_init(plat->reg, plat->use_dte);
return 0; } @@ -367,7 +372,7 @@ static inline void _debug_uart_init(void) { struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
- _mxc_serial_init(base); + _mxc_serial_init(base, false); _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE, false); }
Hi Marcel,
On 01/02/19 16:04, Marcel Ziswiler wrote:
From: Max Krummenacher max.krummenacher@toradex.com
If the UART is used in DTE mode the RI and DCD bits in UCR3 become irq enable bits. Both are set to enabled after reset and both likely are pending.
Disable the bits to prevent an interrupt storm when Linux enables the UART interrupts.
Signed-off-by: Max Krummenacher max.krummenacher@toradex.com Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
I never seen this issue, but you fix looks plausible - I applied this to my working branch and queued for next PR.
Regards, Stefano
drivers/serial/serial_mxc.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 7e4e6d36b8..df35ac9114 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -138,13 +138,18 @@ struct mxc_uart { u32 ts; };
-static void _mxc_serial_init(struct mxc_uart *base) +static void _mxc_serial_init(struct mxc_uart *base, int use_dte) { writel(0, &base->cr1); writel(0, &base->cr2);
while (!(readl(&base->cr2) & UCR2_SRST));
- if (use_dte)
writel(0x404 | UCR3_ADNIMP, &base->cr3);- else
writel(0x704 | UCR3_ADNIMP, &base->cr3);- writel(0x704 | UCR3_ADNIMP, &base->cr3); writel(0x8000, &base->cr4); writel(0x2b, &base->esc);
@@ -226,7 +231,7 @@ static int mxc_serial_tstc(void) */ static int mxc_serial_init(void) {
- _mxc_serial_init(mxc_base);
_mxc_serial_init(mxc_base, false);
serial_setbrg();
@@ -271,7 +276,7 @@ static int mxc_serial_probe(struct udevice *dev) { struct mxc_serial_platdata *plat = dev->platdata;
- _mxc_serial_init(plat->reg);
_mxc_serial_init(plat->reg, plat->use_dte);
return 0;
} @@ -367,7 +372,7 @@ static inline void _debug_uart_init(void) { struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
- _mxc_serial_init(base);
- _mxc_serial_init(base, false); _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE, false);
}
From: Max Krummenacher max.krummenacher@toradex.com If the UART is used in DTE mode the RI and DCD bits in UCR3 become irq enable bits. Both are set to enabled after reset and both likely are pending. Disable the bits to prevent an interrupt storm when Linux enables the UART interrupts. Signed-off-by: Max Krummenacher max.krummenacher@toradex.com Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Max Krummenacher max.krummenacher@toradex.com
This makes get_imx_reset_cause() accessible in SPL, but keeps the SRSR register content intact so that U-Boot proper can evaluated the reset_cause again should this be needed.
Signed-off-by: Max Krummenacher max.krummenacher@toradex.com Acked-by: Marcel Ziswiler marcel.ziswiler@toradex.com
---
arch/arm/mach-imx/cpu.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 80d9ff48a4..6b83f92662 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -25,19 +25,27 @@ #include <fsl_esdhc.h> #endif
-#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) static u32 reset_cause = -1;
-static char *get_reset_cause(void) +u32 get_imx_reset_cause(void) { - u32 cause; struct src *src_regs = (struct src *)SRC_BASE_ADDR;
- cause = readl(&src_regs->srsr); - writel(cause, &src_regs->srsr); - reset_cause = cause; + if (reset_cause == -1) { + reset_cause = readl(&src_regs->srsr); +/* preserve the value for U-Boot proper */ +#if !defined(CONFIG_SPL_BUILD) + writel(reset_cause, &src_regs->srsr); +#endif + } + + return reset_cause; +}
- switch (cause) { +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) +static char *get_reset_cause(void) +{ + switch (get_imx_reset_cause()) { case 0x00001: case 0x00011: return "POR"; @@ -77,11 +85,6 @@ static char *get_reset_cause(void) return "unknown reset"; } } - -u32 get_imx_reset_cause(void) -{ - return reset_cause; -} #endif
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
From: Max Krummenacher max.krummenacher@toradex.com This makes get_imx_reset_cause() accessible in SPL, but keeps the SRSR register content intact so that U-Boot proper can evaluated the reset_cause again should this be needed. Signed-off-by: Max Krummenacher max.krummenacher@toradex.com Acked-by: Marcel Ziswiler marcel.ziswiler@toradex.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
participants (3)
-
Marcel Ziswiler -
sbabic＠denx.de -
Stefano Babic