[PATCH 0/5] board: ti: am62x: Add support for 1-bit inline DDRSS ECC
Hi,
This series enables the 1-bit inline DDR ECC support in the TI DDRSS bridge for AM62x. The base DDRSS ECC support was merged for k3-ddrss in a previous series for AM64x [1].
The ECC data is stored together with the data, which will reduce the total available memory with 1/9th. The k3-ddrss driver enables the ECC support and primes the full memory from the R5 SPL, so the the memory size changes must propagate from the R5 SPL to A53 SPL and then to A53 u-boot.
The patches are similar to those we have for AM64x, with one exception: "arm: mach-k3: common: Use ddr_init in spl_enable_dcache". Since we've switched the boards to DT to fetch the memory configuration, dram_init_banksize() will no longer set the total memory size in the global data. And spl_enable_dcache() uses dram_init_banksize() instead of dram_init(), which actually sets the memory base/size.
Note this doesn't enable the 1-bit ECC on any platform by default. This can be done by adding the "ti,ecc-enable" property to the memorycontroller node in k3-am6*-ddr.dtsi.
[1] https://lore.kernel.org/u-boot/20220317170346.31162-1-d-gerlach@ti.com/
The patches depend on the base AM62 support, which was recently merged in u-boot/next.
Georgi Vlaev (5): arm: mach-k3: common: Use ddr_init in spl_enable_dcache arm: dts: k3-am625-*: Mark memory with u-boot,dm-spl board: ti: am62x: Use fdt functions for ram and bank init board: ti: am62x: Account for DDR size fixups if ECC is enabled configs: am62x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfig
arch/arm/dts/k3-am625-r5-sk.dts | 1 + arch/arm/dts/k3-am625-sk-u-boot.dtsi | 4 ++ arch/arm/mach-k3/common.c | 2 +- board/ti/am62x/evm.c | 62 ++++++++++++++++++++++++---- configs/am62x_evm_r5_defconfig | 1 + 5 files changed, 61 insertions(+), 9 deletions(-)
base-commit: a87a6fcd20c0e29fe55bfbb6917c4aa1f1bbce74
The spl_enable_dcache() function calls dram_init_banksize() to get the total memory size. Normally the dram_init_banksize() setups the memory banks, while the total size is reported by ddr_init(). This worked so far for K3 since we set the gd->ram_size in dram_init_banksize() as well.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com --- arch/arm/mach-k3/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index b4b75f4e6c86..70f6444e7988 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -516,7 +516,7 @@ void spl_enable_dcache(void) #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
- dram_init_banksize(); + dram_init();
/* reserve TLB table */ gd->arch.tlb_size = PGTABLE_SIZE;
On Tue, Jun 14, 2022 at 05:45:30PM +0300, Georgi Vlaev wrote:
The spl_enable_dcache() function calls dram_init_banksize() to get the total memory size. Normally the dram_init_banksize() setups the memory banks, while the total size is reported by ddr_init(). This worked so far for K3 since we set the gd->ram_size in dram_init_banksize() as well.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Tue, Jun 14, 2022 at 05:45:30PM +0300, Georgi Vlaev wrote:
The spl_enable_dcache() function calls dram_init_banksize() to get the total memory size. Normally the dram_init_banksize() setups the memory banks, while the total size is reported by ddr_init(). This worked so far for K3 since we set the gd->ram_size in dram_init_banksize() as well.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/next, thanks!
Mark the memory node with u-boot,dm-spl so we can use it from early SPL on both R5 and A53.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com --- arch/arm/dts/k3-am625-r5-sk.dts | 1 + arch/arm/dts/k3-am625-sk-u-boot.dtsi | 4 ++++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index 2691af40a145..5aab858edd14 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -28,6 +28,7 @@ /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ u-boot,dm-spl; };
reserved-memory { diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi index e1971ecdfedb..159fa36bbe9f 100644 --- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi @@ -13,6 +13,10 @@ aliases { mmc1 = &sdhci1; }; + + memory@80000000 { + u-boot,dm-spl; + }; };
&cbass_main{
On Tue, Jun 14, 2022 at 05:45:31PM +0300, Georgi Vlaev wrote:
Mark the memory node with u-boot,dm-spl so we can use it from early SPL on both R5 and A53.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Tue, Jun 14, 2022 at 05:45:31PM +0300, Georgi Vlaev wrote:
Mark the memory node with u-boot,dm-spl so we can use it from early SPL on both R5 and A53.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/next, thanks!
Use the appropriate fdtdec_setup_mem_size_base() call in dram_init() and fdtdec_setup_bank_size() in dram_bank_init() to pull these values from DT, where they are already available, instead of hardcoding them.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com --- board/ti/am62x/evm.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 4dd5e64299bf..fb5106d1f3c8 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -23,17 +23,10 @@ int board_init(void)
int dram_init(void) { - gd->ram_size = 0x80000000; - - return 0; + return fdtdec_setup_mem_size_base(); }
int dram_init_banksize(void) { - /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; - gd->ram_size = 0x80000000; - - return 0; + return fdtdec_setup_memory_banksize(); }
On Tue, Jun 14, 2022 at 05:45:32PM +0300, Georgi Vlaev wrote:
Use the appropriate fdtdec_setup_mem_size_base() call in dram_init() and fdtdec_setup_bank_size() in dram_bank_init() to pull these values from DT, where they are already available, instead of hardcoding them.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Tue, Jun 14, 2022 at 05:45:32PM +0300, Georgi Vlaev wrote:
Use the appropriate fdtdec_setup_mem_size_base() call in dram_init() and fdtdec_setup_bank_size() in dram_bank_init() to pull these values from DT, where they are already available, instead of hardcoding them.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/next, thanks!
Call into k3-ddrss driver to fixup device tree and resize the available amount of DDR if ECC is enabled.
A second fixup is required from A53 SPL to take the fixup as done from R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes this to the OS.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com --- board/ti/am62x/evm.c | 53 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+)
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index fb5106d1f3c8..d65ee1d69606 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -9,6 +9,8 @@
#include <asm/io.h> #include <spl.h> +#include <dm/uclass.h> +#include <k3-ddrss.h> #include <fdt_support.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -30,3 +32,54 @@ int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); } + +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_K3_AM64_DDRSS) +static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) +{ + struct udevice *dev; + int ret; + + dram_init_banksize(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("Cannot get RAM device for ddr size fixup: %d\n", ret); + + ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); + if (ret) + printf("Error fixing up ddr node for ECC use! %d\n", ret); +} +#else +static void fixup_memory_node(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */ + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, + CONFIG_NR_DRAM_BANKS); + if (ret) + printf("Error fixing up memory node! %d\n", ret); +} +#endif + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ +#if defined(CONFIG_K3_AM64_DDRSS) + fixup_ddr_driver_for_ecc(spl_image); +#else + fixup_memory_node(spl_image); +#endif +} +#endif
On Tue, Jun 14, 2022 at 05:45:33PM +0300, Georgi Vlaev wrote:
Call into k3-ddrss driver to fixup device tree and resize the available amount of DDR if ECC is enabled.
A second fixup is required from A53 SPL to take the fixup as done from R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes this to the OS.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Tue, Jun 14, 2022 at 05:45:33PM +0300, Georgi Vlaev wrote:
Call into k3-ddrss driver to fixup device tree and resize the available amount of DDR if ECC is enabled.
A second fixup is required from A53 SPL to take the fixup as done from R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes this to the OS.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/next, thanks!
Add CONFIG_NR_DRAM_BANKS from am62x_evm_a53_defconfig as this is needed to calculate the size of DDR that is available.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com --- configs/am62x_evm_r5_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 2e340cd6f416..deafb92fc142 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_AM625_R5_EVM=y CONFIG_DM_GPIO=y
On Tue, Jun 14, 2022 at 05:45:34PM +0300, Georgi Vlaev wrote:
Add CONFIG_NR_DRAM_BANKS from am62x_evm_a53_defconfig as this is needed to calculate the size of DDR that is available.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Tue, Jun 14, 2022 at 05:45:34PM +0300, Georgi Vlaev wrote:
Add CONFIG_NR_DRAM_BANKS from am62x_evm_a53_defconfig as this is needed to calculate the size of DDR that is available.
Signed-off-by: Georgi Vlaev g-vlaev@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/next, thanks!
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