From: Hou Zhiqiang Zhiqiang.Hou@nxp.com

Use virtual address to access the MII block registers instead of physical address.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com --- V6: - No change.

drivers/net/fsl_mdio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index d2edd1751c..ae96ce4c7b 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -213,7 +213,7 @@ static int tsec_mdio_probe(struct udevice *dev) printf("dev_get_priv(dev %p) = NULL\n", dev); return -1; } - priv->regs = (void *)(uintptr_t)dev_read_addr(dev); + priv->regs = dev_remap_addr(dev); debug("%s priv %p @ regs %p, pdata %p\n", __func__, priv, priv->regs, pdata);

From: Hou Zhiqiang Zhiqiang.Hou@nxp.com

For the platforms on which the eTSEC driver uses DM_ETH, convert its MDIO controller code to also use DM_MDIO.

Note that for handling the TBI PHY (the MAC PCS for SGMII), we still don't register a udevice for it, since we can drive it locally and there is no point in doing otherwise.

Signed-off-by: Vladimir Oltean vladimir.oltean@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V6: - No change.

drivers/net/tsec.c | 43 ++++++++++--------------------------------- 1 file changed, 10 insertions(+), 33 deletions(-)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 5d12e4b775..9d68c6f829 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -18,6 +18,7 @@ #include <linux/bitops.h> #include <linux/delay.h> #include <linux/errno.h> +#include <miiphy.h> #include <asm/processor.h> #include <asm/io.h>

@@ -681,8 +682,12 @@ static int init_phy(struct tsec_private *priv) if (priv->interface == PHY_INTERFACE_MODE_SGMII) tsec_configure_serdes(priv);

+#ifdef CONFIG_DM_ETH + phydev = dm_eth_phy_connect(priv->dev); +#else phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, priv->interface); +#endif if (!phydev) return 0;

@@ -789,14 +794,17 @@ int tsec_standard_init(struct bd_info *bis) return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); } #else /* CONFIG_DM_ETH */ + +#ifndef CONFIG_DM_MDIO +#error "TSEC with DM_ETH also requires DM_MDIO" +#endif + int tsec_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct tsec_private *priv = dev_get_priv(dev); - struct tsec_mii_mng __iomem *ext_phyregs_mii; struct ofnode_phandle_args phandle_args; u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE; - struct fsl_pq_mdio_info mdio_info; const char *phy_mode; fdt_addr_t reg; ofnode parent; @@ -805,31 +813,6 @@ int tsec_probe(struct udevice *dev) pdata->iobase = (phys_addr_t)dev_read_addr(dev); priv->regs = dev_remap_addr(dev);

- if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, - &phandle_args)) { - printf("phy-handle does not exist under tsec %s\n", dev->name); - return -ENOENT; - } else { - int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); - - priv->phyaddr = reg; - } - - parent = ofnode_get_parent(phandle_args.node); - if (!ofnode_valid(parent)) { - printf("No parent node for PHY?\n"); - return -ENOENT; - } - - reg = ofnode_get_addr_index(parent, 0); - if (reg == FDT_ADDR_T_NONE) { - printf("No 'reg' property of MII for external PHY\n"); - return -ENOENT; - } - - ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0, - MAP_NOCACHE); - ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0, &phandle_args); if (ret == 0) { @@ -867,12 +850,6 @@ int tsec_probe(struct udevice *dev) if (priv->interface == PHY_INTERFACE_MODE_SGMII) priv->flags |= TSEC_SGMII;

- mdio_info.regs = ext_phyregs_mii; - mdio_info.name = (char *)dev->name; - ret = fsl_pq_mdio_init(NULL, &mdio_info); - if (ret) - return ret; - /* Reset the MAC */ setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); udelay(2); /* Soft Reset must be asserted for 3 TX clocks */

From: Hou Zhiqiang Zhiqiang.Hou@nxp.com

Add compatible string "gianfar" support and update the device-tree-bindings doc.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com --- V6: - No change.

doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +- drivers/net/tsec.c | 16 ++++++++++++++-- include/tsec.h | 4 ++++ 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt b/doc/device-tree-bindings/net/fsl-tsec-phy.txt index 8e8574bc97..a44c5fd9d9 100644 --- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt +++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt @@ -2,7 +2,7 @@

Properties:

- - compatible : Should be "fsl,etsec2" + - compatible : Should be "fsl,etsec2" or "gianfar" - reg : Offset and length of the register set for the device - phy-handle : See ethernet.txt file in the same directory. - phy-connection-type : See ethernet.txt file in the same directory. This diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 1e04a89102..e59a107ea8 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -808,11 +808,14 @@ int tsec_probe(struct udevice *dev) struct tsec_private *priv = dev_get_priv(dev); struct ofnode_phandle_args phandle_args; u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE; + struct tsec_data *data; const char *phy_mode; fdt_addr_t reg; ofnode parent; int ret;

+ data = (struct tsec_data *)dev_get_driver_data(dev); + pdata->iobase = (phys_addr_t)dev_read_addr(dev); priv->regs = dev_remap_addr(dev);

@@ -833,7 +836,7 @@ int tsec_probe(struct udevice *dev) return -ENOENT; }

- priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, + priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off, 0, MAP_NOCACHE); }

@@ -885,8 +888,17 @@ static const struct eth_ops tsec_ops = { .mcast = tsec_mcast_addr, };

+static struct tsec_data etsec2_data = { + .mdio_regs_off = TSEC_MDIO_REGS_OFFSET, +}; + +static struct tsec_data gianfar_data = { + .mdio_regs_off = 0x0, +}; + static const struct udevice_id tsec_ids[] = { - { .compatible = "fsl,etsec2" }, + { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data }, + { .compatible = "gianfar", .data = (ulong)&gianfar_data }, { } };

diff --git a/include/tsec.h b/include/tsec.h index 43255e538f..5433cfd966 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -394,6 +394,10 @@ struct tsec {

#define TX_BUF_CNT 2

+struct tsec_data { + u32 mdio_regs_off; +}; + struct tsec_private { struct txbd8 __iomem txbd[TX_BUF_CNT]; struct rxbd8 __iomem rxbd[PKTBUFSRX];

From: Hou Zhiqiang Zhiqiang.Hou@nxp.com

Move vsc7835 firmware uploading to board_early_init_r(), so that the switch also can work in DM eTSEC driver.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com --- V6: - No change.

board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++++++++++---------- 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 7c703b354f..d0562ba95a 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -316,6 +316,10 @@ int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); +#ifdef CONFIG_VSC7385_ENET + unsigned int vscfw_addr; + char *tmp; +#endif

/* * Remap Boot flash region to caching-inhibited @@ -338,6 +342,20 @@ int board_early_init_r(void) set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ + +#ifdef CONFIG_VSC7385_ENET + /* If a VSC7385 microcode image is present, then upload it. */ + tmp = env_get("vscfw_addr"); + if (tmp) { + vscfw_addr = simple_strtoul(tmp, NULL, 16); + printf("uploading VSC7385 microcode from %x\n", vscfw_addr); + if (vsc7385_upload_firmware((void *)vscfw_addr, + CONFIG_VSC7385_IMAGE_SIZE)) + puts("Failure uploading VSC7385 microcode.\n"); + } else { + puts("No address specified for VSC7385 microcode.\n"); + } +#endif return 0; }

@@ -348,10 +366,6 @@ int board_eth_init(struct bd_info *bis) ccsr_gur_t *gur __attribute__((unused)) = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; -#ifdef CONFIG_VSC7385_ENET - char *tmp; - unsigned int vscfw_addr; -#endif

#ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); @@ -375,19 +389,6 @@ int board_eth_init(struct bd_info *bis) return 0; }

-#ifdef CONFIG_VSC7385_ENET - /* If a VSC7385 microcode image is present, then upload it. */ - tmp = env_get("vscfw_addr"); - if (tmp) { - vscfw_addr = simple_strtoul(tmp, NULL, 16); - printf("uploading VSC7385 microcode from %x\n", vscfw_addr); - if (vsc7385_upload_firmware((void *) vscfw_addr, - CONFIG_VSC7385_IMAGE_SIZE)) - puts("Failure uploading VSC7385 microcode.\n"); - } else - puts("No address specified for VSC7385 microcode.\n"); -#endif - mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1); mdio_info.name = DEFAULT_MII_NAME;

From: Hou Zhiqiang Zhiqiang.Hou@nxp.com

P1020RDB implements 3 enhanced three-speed Ethernet controllers, and the connection is shown below: eTSEC1: Connected to RGMII switch VSC7385 eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com --- V6: - No change.

arch/powerpc/dts/p1020-post.dtsi | 20 ++++++++- arch/powerpc/dts/p1020rdb-pc.dts | 1 + arch/powerpc/dts/p1020rdb-pc.dtsi | 55 +++++++++++++++++++++++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 1 + arch/powerpc/dts/p1020rdb-pd.dts | 45 ++++++++++++++++++++ arch/powerpc/dts/pq3-etsec2-0.dtsi | 35 ++++++++++++++++ arch/powerpc/dts/pq3-etsec2-1.dtsi | 35 ++++++++++++++++ arch/powerpc/dts/pq3-etsec2-2.dtsi | 35 ++++++++++++++++ arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 +++++++ arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 +++++++ arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 +++++++ 11 files changed, 273 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi

diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1dce8e86e9..c73539ad5c 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -44,10 +44,26 @@ clock-frequency = <0>; };

- /include/ "pq3-i2c-0.dtsi" - /include/ "pq3-i2c-1.dtsi" +/include/ "pq3-i2c-0.dtsi" +/include/ "pq3-i2c-1.dtsi" + +/include/ "pq3-etsec2-0.dtsi" + enet0: enet0_grp2: ethernet@b0000 { + }; + +/include/ "pq3-etsec2-1.dtsi" + enet1: enet1_grp2: ethernet@b1000 { + }; + +/include/ "pq3-etsec2-2.dtsi" + enet2: enet2_grp2: ethernet@b2000 { + }; };

+/include/ "pq3-etsec2-grp2-0.dtsi" +/include/ "pq3-etsec2-grp2-1.dtsi" +/include/ "pq3-etsec2-grp2-2.dtsi" + /* PCIe controller base address 0x9000 */ &pci1 { compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts index 7ebaa619df..715330dc50 100644 --- a/arch/powerpc/dts/p1020rdb-pc.dts +++ b/arch/powerpc/dts/p1020rdb-pc.dts @@ -32,4 +32,5 @@ }; };

+/include/ "p1020rdb-pc.dtsi" /include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pc.dtsi b/arch/powerpc/dts/p1020rdb-pc.dtsi new file mode 100644 index 0000000000..6bf424fd3f --- /dev/null +++ b/arch/powerpc/dts/p1020rdb-pc.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&soc { + mdio@24000 { + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <3 1 0 0>; + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + + tbi0: tbi-phy@11 { + device_type = "tbi-phy"; + reg = <0x11>; + }; + }; + + mdio@25000 { + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet0: ethernet@b0000 { + phy-connection-type = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + + }; + + enet1: ethernet@b1000 { + phy-handle = <&phy0>; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; +}; diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts index c0e5ef4cf4..7680b7c7e1 100644 --- a/arch/powerpc/dts/p1020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts @@ -32,4 +32,5 @@ }; };

+/include/ "p1020rdb-pc.dtsi" /include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts index 21174a09be..e0e8993dab 100644 --- a/arch/powerpc/dts/p1020rdb-pd.dts +++ b/arch/powerpc/dts/p1020rdb-pd.dts @@ -17,6 +17,51 @@

soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; + + mdio@24000 { + phy0: ethernet-phy@0 { + interrupts = <3 1 0 0>; + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + }; + + mdio@25000 { + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@26000 { + tbi2: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet0: ethernet@b0000 { + phy-connection-type = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + enet1: ethernet@b1000 { + phy-handle = <&phy0>; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; };

pci1: pcie@ffe09000 { diff --git a/arch/powerpc/dts/pq3-etsec2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-0.dtsi new file mode 100644 index 0000000000..f9d3d04650 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-0.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@24000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-mdio"; + reg = <0x24000 0x1000 0xb0030 0x4>; +}; + +ethernet@b0000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb0000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b0000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb0000 0x1000>; + interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-1.dtsi new file mode 100644 index 0000000000..6c01481909 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-1.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@25000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-tbi"; + reg = <0x25000 0x1000 0xb1030 0x4>; +}; + +ethernet@b1000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb1000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b1000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb1000 0x1000>; + interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-2.dtsi new file mode 100644 index 0000000000..2a597c0db6 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-2.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@26000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-tbi"; + reg = <0x26000 0x1000 0xb1030 0x4>; +}; + +ethernet@b2000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb2000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b2000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb2000 0x1000>; + interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi new file mode 100644 index 0000000000..16752a7c45 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&enet0_grp2 { + queue-group@b4000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb4000 0x1000>; + interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi new file mode 100644 index 0000000000..0464938424 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&enet1_grp2 { + queue-group@b5000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb5000 0x1000>; + interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi new file mode 100644 index 0000000000..fe8003c44a --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&enet2_grp2 { + queue-group@b6000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb6000 0x1000>; + interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>; + }; +};

From: Hou Zhiqiang Zhiqiang.Hou@nxp.com

Enable the DM_ETH and DM_MDIO config.

On P1020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V6: - No change.

configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_defconfig | 3 +++ configs/P1020RDB-PC_NAND_defconfig | 3 +++ configs/P1020RDB-PC_SDCARD_defconfig | 3 +++ configs/P1020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PC_defconfig | 3 +++ configs/P1020RDB-PD_NAND_defconfig | 3 +++ configs/P1020RDB-PD_SDCARD_defconfig | 3 +++ configs/P1020RDB-PD_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PD_defconfig | 3 +++ 12 files changed, 36 insertions(+)

diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 6db4bd7d52..e69595102a 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index cacce4d5ec..974bcb15c7 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -57,6 +57,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -68,8 +69,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 3c9e491b08..f3e599869d 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -59,6 +59,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -70,8 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 5c68ea060a..445e796afb 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -46,6 +46,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -57,8 +58,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 9883204787..43fdbdffe4 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 22ba4f6501..282453a290 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -67,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 250b56d216..0a7fa606bf 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -58,6 +58,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -69,8 +70,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 329bd72e6b..cbe9c525dd 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -45,6 +45,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -56,8 +57,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 5d7f16aecb..8512e7a5ab 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -65,6 +65,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -76,8 +77,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 12d70e8ebe..80988c3d35 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -71,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 6da7157e1f..ea28116f4b 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index c39509e4ac..e7b97dbf4a 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -49,6 +49,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -60,8 +61,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y

From: Hou Zhiqiang Zhiqiang.Hou@nxp.com

The board_eth_init() is only used by legacy ethernet driver framework, so do not compile it when DM_ETH config has been selected.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com --- V6: - No change.

board/freescale/p1010rdb/p1010rdb.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index accf2f24e5..4c3a03e7cd 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -484,6 +484,7 @@ int checkboard(void) return 0; }

+#ifndef CONFIG_DM_ETH int board_eth_init(struct bd_info *bis) { #ifdef CONFIG_TSEC_ENET @@ -524,6 +525,7 @@ int board_eth_init(struct bd_info *bis)

return pci_eth_init(bis); } +#endif

#if defined(CONFIG_OF_BOARD_SETUP) void fdt_del_flexcan(void *blob)

From: Hou Zhiqiang Zhiqiang.Hou@nxp.com

P2020RDB implements 3 enhanced three-speed Ethernet controllers, and the connection is shown below: eTSEC1: Connected to RGMII switch VSC7385 eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V6: - No change.

arch/powerpc/dts/p2020-post.dtsi | 8 +++-- arch/powerpc/dts/p2020rdb-pc.dts | 1 + arch/powerpc/dts/p2020rdb-pc.dtsi | 50 ++++++++++++++++++++++++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 + arch/powerpc/dts/pq3-etsec1-0.dtsi | 28 ++++++++++++++++ arch/powerpc/dts/pq3-etsec1-1.dtsi | 28 ++++++++++++++++ arch/powerpc/dts/pq3-etsec1-2.dtsi | 28 ++++++++++++++++ arch/powerpc/dts/pq3-etsec1-3.dtsi | 28 ++++++++++++++++ 8 files changed, 170 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 4ed093dad4..11945295d1 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -38,8 +38,12 @@ clock-frequency = <0>; };

- /include/ "pq3-i2c-0.dtsi" - /include/ "pq3-i2c-1.dtsi" +/include/ "pq3-i2c-0.dtsi" +/include/ "pq3-i2c-1.dtsi" + +/include/ "pq3-etsec1-0.dtsi" +/include/ "pq3-etsec1-1.dtsi" +/include/ "pq3-etsec1-2.dtsi" };

/* PCIe controller base address 0x8000 */ diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index 08befd4c59..f3f6be1080 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -37,4 +37,5 @@ }; };

+/include/ "p2020rdb-pc.dtsi" /include/ "p2020-post.dtsi" diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi b/arch/powerpc/dts/p2020rdb-pc.dtsi new file mode 100644 index 0000000000..0d2acc746e --- /dev/null +++ b/arch/powerpc/dts/p2020rdb-pc.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges) + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&soc { + mdio@24520 { + phy0: ethernet-phy@0 { + interrupts = <3 1 0 0>; + reg = <0x0>; + }; + phy1: ethernet-phy@1 { + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + }; + + mdio@25520 { + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@26520 { + status = "disabled"; + }; + + enet0: ethernet@24000 { + phy-connection-type = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + enet1: ethernet@25000 { + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@26000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index 04b2519e1a..6d983b7d71 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -37,4 +37,5 @@ }; };

+/include/ "p2020rdb-pc.dtsi" /include/ "p2020-post.dtsi" diff --git a/arch/powerpc/dts/pq3-etsec1-0.dtsi b/arch/powerpc/dts/pq3-etsec1-0.dtsi new file mode 100644 index 0000000000..8800243f34 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-0.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; +}; + +mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-1.dtsi b/arch/powerpc/dts/pq3-etsec1-1.dtsi new file mode 100644 index 0000000000..2bc62d1a57 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-1.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>; +}; + +mdio@25520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x25520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-2.dtsi b/arch/powerpc/dts/pq3-etsec1-2.dtsi new file mode 100644 index 0000000000..d45865fe03 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-2.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@26000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <2>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + ranges = <0x0 0x26000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>; +}; + +mdio@26520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x26520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-3.dtsi b/arch/powerpc/dts/pq3-etsec1-3.dtsi new file mode 100644 index 0000000000..853a27359d --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-3.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@27000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <3>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + ranges = <0x0 0x27000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>; +}; + +mdio@27520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x27520 0x20>; +};

From: Vladimir Oltean vladimir.oltean@nxp.com

The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid build errors, enable DM_MDIO in these boards' configs before we actually add DM_MDIO support to tsec.

Signed-off-by: Vladimir Oltean vladimir.oltean@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V6: - No code change, just move it to the tail of this series.

configs/ls1021atsn_qspi_defconfig | 1 + configs/ls1021atsn_sdcard_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + 9 files changed, 9 insertions(+)

diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 06a139be1a..43f9e511cc 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -44,6 +44,7 @@ CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 8046f6452f..49197eeed4 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -55,6 +55,7 @@ CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 30511dd425..d62dcfa751 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -46,6 +46,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 60622b1879..f49a882e0a 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -48,6 +48,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index fa0a118eb0..e75c7b43d2 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 30c107924f..767c364b3e 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -49,6 +49,7 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 0911b9c151..5b3ac2a348 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -61,6 +61,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index eaf5b98f9f..5cc0b90aa7 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -63,6 +63,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 2743848ac9..e3e64f9790 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y