[U-Boot] [PATCH 1/2] ppc4xx: use TCR macro instead of tcr
From: Matthias Fuchs matthias.fuchs@esd.eu
This patch migrates 4xx code from using the lowercase tcr macro to the uppercase TCR macro. Both macros have been defined in the past. So one is to much and uppercase macros are much more common.
The lowercase macro conflicts with the upcoming introduction of the ppc4xx_gpio struct and it's tcr field.
Doing more such migration and getting rid of many defines from include/ppc405.h and include/ppc440.h should be put on our TODO list.
Signed-off-by: Matthias Fuchs matthias.fuchs@esd.eu --- cpu/ppc4xx/cpu_init.c | 4 ++-- cpu/ppc4xx/interrupts.c | 8 ++++---- cpu/ppc4xx/start.S | 2 +- include/ppc405.h | 1 - include/ppc440.h | 1 - 5 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index bbd795d..111f635 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -248,7 +248,7 @@ cpu_init_f (void) #endif
#if defined(CONFIG_WATCHDOG) - val = mfspr(tcr); + val = mfspr(TCR); #if defined(CONFIG_440EP) || defined(CONFIG_440GR) val |= 0xb8000000; /* generate system reset after 1.34 seconds */ #elif defined(CONFIG_440EPX) @@ -260,7 +260,7 @@ cpu_init_f (void) val &= ~0x30000000; /* clear WRC bits */ val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */ #endif - mtspr(tcr, val); + mtspr(TCR, val);
val = mfspr(tsr); val |= 0x80000000; /* enable watchdog timer */ diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 494bd8c..47c12a2 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -102,9 +102,9 @@ int interrupt_init_cpu (unsigned *decrementer_count) * Init PIT */ #if defined(CONFIG_440) - val = mfspr( tcr ); + val = mfspr( TCR ); val &= (~0x04400000); /* clear DIS & ARE */ - mtspr( tcr, val ); + mtspr( TCR, val ); mtspr( dec, 0 ); /* Prevent exception after TSR clear*/ mtspr( decar, 0 ); /* clear reload */ mtspr( tsr, 0x08000000 ); /* clear DEC status */ @@ -126,9 +126,9 @@ int interrupt_init_cpu (unsigned *decrementer_count) /* * Enable PIT */ - val = mfspr(tcr); + val = mfspr(TCR); val |= 0x04400000; - mtspr(tcr, val); + mtspr(TCR, val);
/* * Set EVPR to 0 diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 582c781..22bc409 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -626,7 +626,7 @@ _start: mtspr tbl,r0 /* prevent fit & wdt exceptions */ mtspr tbu,r0 mtspr tsr,r1 /* clear all timer exception status */ - mtspr tcr,r0 /* disable all */ + mtspr TCR,r0 /* disable all */ mtspr esr,r0 /* clear exception syndrome register */ mtxer r0 /* clear integer exception register */
diff --git a/include/ppc405.h b/include/ppc405.h index 917afec..50fc7be 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -61,7 +61,6 @@ #define dear 0x3d5 /* data exeption address register */ #define evpr 0x3d6 /* exeption vector prefix register */ #define tsr 0x3d8 /* timer status register */ - #define tcr 0x3da /* timer control register */ #define pit 0x3db /* programmable interval timer */ #define sgr 0x3b9 /* storage guarded reg */ #define dcwr 0x3ba /* data cache write-thru reg*/ diff --git a/include/ppc440.h b/include/ppc440.h index 01f6eaf..df78eea 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -90,7 +90,6 @@ #define dvc1 0x13e /* data value compare 1 */ #define dvc2 0x13f /* data value compare 2 */ #define tsr 0x150 /* timer status register */ -#define tcr 0x154 /* timer control register */ #define ivor0 0x190 /* interrupt vector offset register 0 */ #define ivor1 0x191 /* interrupt vector offset register 1 */ #define ivor2 0x192 /* interrupt vector offset register 2 */
From: Matthias Fuchs matthias.fuchs@esd.eu
Signed-off-by: Matthias Fuchs matthias.fuchs@esd.eu --- include/asm-ppc/gpio.h | 24 ++++++++++++++++++++++++ 1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h index fc05dc0..23e29b1 100644 --- a/include/asm-ppc/gpio.h +++ b/include/asm-ppc/gpio.h @@ -24,6 +24,8 @@ #ifndef __ASM_PPC_GPIO_H #define __ASM_PPC_GPIO_H
+#include <asm/types.h> + /* 4xx PPC's have 2 GPIO controllers */ #if defined(CONFIG_405EZ) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -34,6 +36,28 @@ #define GPIO_GROUP_MAX 1 #endif
+/* GPIO controller */ +struct ppc4xx_gpio { + u32 or; /* Output Control */ + u32 tcr; /* Tri-State Control */ + u32 osl; /* Output Select 16..31 */ + u32 osh; /* Output Select 0..15 */ + u32 tsl; /* Tri-State Select 16..31 */ + u32 tsh; /* Tri-State Select 0..15 */ + u32 odr; /* Open Drain */ + u32 ir; /* Input */ + u32 rr1; /* Receive Register 1 */ + u32 rr2; /* Receive Register 2 */ + u32 rr3; /* Receive Register 3 */ + u32 reserved; + u32 is1l; /* Input Select 1 16..31 */ + u32 is1h; /* Input Select 1 0..15 */ + u32 is2l; /* Input Select 2 16..31 */ + u32 is2h; /* Input Select 2 0..15 */ + u32 is3l; /* Input Select 3 16..31 */ + u32 is3h; /* Input Select 3 0..15 */ +}; + /* Offsets */ #define GPIOx_OR 0x00 /* GPIO Output Register */ #define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
On Monday 20 July 2009 12:15:38 matthias.fuchs@esd.eu wrote:
From: Matthias Fuchs matthias.fuchs@esd.eu
Signed-off-by: Matthias Fuchs matthias.fuchs@esd.eu
Applied to ppc4xx/master. Thanks.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
Dear matthias.fuchs@esd.eu,
In message 12480849383077-git-send-email-matthias.fuchs@esd.eu you wrote:
This patch migrates 4xx code from using the lowercase tcr macro to the uppercase TCR macro. Both macros have been defined in the past. So one is to much and uppercase macros are much more common.
I think this should not be TCR either. This should be SPRN_TCR as defined in <asm/processor.h>.
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 582c781..22bc409 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -626,7 +626,7 @@ _start: mtspr tbl,r0 /* prevent fit & wdt exceptions */ mtspr tbu,r0 mtspr tsr,r1 /* clear all timer exception status */
- mtspr tcr,r0 /* disable all */
- mtspr TCR,r0 /* disable all */ mtspr esr,r0 /* clear exception syndrome register */ mtxer r0 /* clear integer exception register */
Now this mix of lower case and upper case names is really ugly, isn't it?
diff --git a/include/ppc405.h b/include/ppc405.h index 917afec..50fc7be 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -61,7 +61,6 @@ #define dear 0x3d5 /* data exeption address register */ #define evpr 0x3d6 /* exeption vector prefix register */ #define tsr 0x3d8 /* timer status register */
- #define tcr 0x3da /* timer control register */ #define pit 0x3db /* programmable interval timer */ #define sgr 0x3b9 /* storage guarded reg */ #define dcwr 0x3ba /* data cache write-thru reg*/
diff --git a/include/ppc440.h b/include/ppc440.h index 01f6eaf..df78eea 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -90,7 +90,6 @@ #define dvc1 0x13e /* data value compare 1 */ #define dvc2 0x13f /* data value compare 2 */ #define tsr 0x150 /* timer status register */ -#define tcr 0x154 /* timer control register */ #define ivor0 0x190 /* interrupt vector offset register 0 */ #define ivor1 0x191 /* interrupt vector offset register 1 */ #define ivor2 0x192 /* interrupt vector offset register 2 */
I think all these can be dumped - they should be taken from <asm/processor.h> instead.
Best regards,
Wolfgang Denk
participants (3)
-
matthias.fuchs＠esd.eu -
Stefan Roese -
Wolfgang Denk