Can u please tell me the reason, without D cache i dont see significant performance improvents.

ARM manual, search for a section like this:

CP15 C bit M bit 0 0 DCache disabled. All data accesses are to the external memory.

1 0 DCache enabled, MMU disabled. The C bit is overriden by the M bit setting, which means that the DCache is effectively disabled. All data accesses are noncachable, nonbufferable, with no protection checks. All addresses are flat mapped, that is VA = MVA = PA.

1 1 DCache enabled, MMU enabled. All data accesses are cachable or noncachable depending on the page descriptor C bit and B bit (see Table 4-4), and protection checks are performed. All addresses are remapped from VA to PA, depending on the MMU page table entry, that is the VA is translated to an MVA, and the MVA is remapped to a PA.

And take look at this thread: http://www.mail-archive.com/u-boot@lists.denx.de/msg11249.html

On Mon, Jul 13, 2009 at 12:57 PM, akshay ts takshays@yahoo.co.in wrote:

Hi, Can u please tell me the reason, without D cache i dont see significant performance improvents.

Warm Regards, Akshay

--- On Mon, 13/7/09, Drasko DRASKOVIC drasko.draskovic@gmail.com wrote:

...

From: Drasko DRASKOVIC drasko.draskovic@gmail.com Subject: Re: [U-Boot] Can I and/or D Cache work without MMU enabling in

ARM11 or ARM cortex

...

To: "akshay ts" takshays@yahoo.co.in Cc: u-boot@lists.denx.de Date: Monday, 13 July, 2009, 3:06 PM I yes, D no.

On Mon, Jul 13, 2009 at 9:04 AM, akshay ts takshays@yahoo.co.in wrote:

Hi,

I want to use i and/or D cache in ARM cortex on a OMAP3430 system without MMU. Is it possible?

Warm Regards,

Akshay

  Looking for local information? Find it on Yahoo!

Local http://in.local.yahoo.com/

---

U-Boot mailing list

U-Boot@lists.denx.de

http://lists.denx.de/mailman/listinfo/u-boot

 Looking for local information? Find it on Yahoo! Local

http://in.local.yahoo.com/