[U-Boot] [PATCH 00/11 v3] Fix and Re-organise PWM Timer
This patch set tries to fix few bugs in timer and re-organises PWM clock code.
Changes since v2: - Patch-1: New patch. - Patch-2: None. - Patch-3: None. - Patch-4: None. - Patch-5: Fixed typo paremters in commit message. - Patch-6: None. - Patch-7: Added "Acked-by: Simon Glass". - Patch-8: Fixed typo peripherial to peripheral. - Made exynos5_get_periph_rate static. - Added an empty line. - Replaced "enum periph_id" with "int" in function arguments. - Removed "#include <asm/arch/periph.h>" from clk.h. - Added "Acked-by: Simon Glass". - Patch-9: None. - Patch-10: - Replaced "exynos5_get_pwm_clk" with "clock_get_periph_rate" in get_pwm_clk instead of replacing everywhere. - Added "Acked-by: Simon Glass". - Patch-11: New patch.
Changes since v1: - Patch-1: Added "Acked-by: Simon Glass". - Patch-2: Added "Acked-by: Simon Glass". - Patch-3: Added "Acked-by: Simon Glass". - Patch-4: Added "Acked-by: Simon Glass". - Patch-5: Added "Acked-by: Simon Glass". - Patch-6: None. - Patch-7: Fixed few nits. - Patch-8: Added "Acked-by: Simon Glass". - Patch-9: Restored get_pwm_clk call in case of non-exynos5 cpu.
Akshay Saraswat (11): Exynos5: config: enable time command Exynos: Change get_timer() to work correctly Exynos: Add timer_get_us function Exynos: pwm: Fix two bugs in the exynos pwm configuration code Exynos: Avoid a divide by zero by specifying a non-zero period for pwm 4 Exynos: Tidy up the pwm_config function in the exynos pwm driver Exynos: Add peripherial id for pwm Exynos: clock: Add generic api to get the clk freq Exynos: clock: Correct pwm source clk selection Exynos: pwm: Use generic api to get pwm clk freq Exynos: pwm: Remove dead code of function exynos5_get_pwm_clk
arch/arm/cpu/armv7/exynos/clock.c | 167 ++++++++++++++++++++++++++---- arch/arm/cpu/armv7/s5p-common/pwm.c | 42 ++++---- arch/arm/cpu/armv7/s5p-common/timer.c | 117 ++++++++++----------- arch/arm/include/asm/arch-exynos/clk.h | 15 +++ arch/arm/include/asm/arch-exynos/periph.h | 5 + board/samsung/smdk5250/setup.h | 2 +- include/configs/exynos5250-dt.h | 3 + 7 files changed, 244 insertions(+), 107 deletions(-)
This patch enables time command.
Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- Chnages since v2: - New patch.
include/configs/exynos5250-dt.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 2b9d6ac..b13aade 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -325,4 +325,7 @@ #define LCD_BPP LCD_COLOR16 #endif
+/* Enable Time Command */ +#define CONFIG_CMD_TIME + #endif /* __CONFIG_H */
From: Simon Glass sjg@chromium.org
At present get_timer() does not return sane values. It should count up smoothly in milliscond intervals.
We can change the PWM to count down at 1MHz, providing a resolution of 1us and a range of about an hour between required get_timer() calls.
Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained
Signed-off-by: Simon Glass sjg@chromium.org Signed-off-by: Akshay Saraswat akshay.s@samsung.com Acked-by: Simon Glass sjg@chromium.org --- Changes since v2: - None.
Changes since v1: - Added "Acked-by: Simon Glass".
arch/arm/cpu/armv7/s5p-common/pwm.c | 6 ++ arch/arm/cpu/armv7/s5p-common/timer.c | 100 +++++++++++++--------------------- 2 files changed, 44 insertions(+), 62 deletions(-)
diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index 44d7bc3..3147f59 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -174,6 +174,12 @@ int pwm_init(int pwm_id, int div, int invert)
/* set count value */ offset = pwm_id * 3; + + /* + * TODO(sjg): Use this as a countdown timer for now. We count down + * from the maximum value to 0, then reset. + */ + timer_rate_hz = -1; writel(timer_rate_hz, &pwm->tcntb0 + offset);
val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id)); diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index e78c716..c48a297 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -39,13 +39,33 @@ static inline struct s5p_timer *s5p_get_base_timer(void) return (struct s5p_timer *)samsung_get_base_timer(); }
+/** + * Read the countdown timer. + * + * This operates at 1MHz and counts downwards. It will wrap about every + * hour (2^32 microseconds). + * + * @return current value of timer + */ +static unsigned long timer_get_us_down(void) +{ + struct s5p_timer *const timer = s5p_get_base_timer(); + + return readl(&timer->tcnto4); +} + int timer_init(void) { /* PWM Timer 4 */ - pwm_init(4, MUX_DIV_2, 0); + pwm_init(4, MUX_DIV_4, 0); pwm_config(4, 0, 0); pwm_enable(4);
+ /* Use this as the current monotonic time in us */ + gd->arch.timer_reset_value = 0; + + /* Use this as the last timer value we saw */ + gd->arch.lastinc = timer_get_us_down(); reset_timer_masked();
return 0; @@ -56,48 +76,28 @@ int timer_init(void) */ unsigned long get_timer(unsigned long base) { - return get_timer_masked() - base; + ulong now = timer_get_us_down(); + + /* + * Increment the time by the amount elapsed since the last read. + * The timer may have wrapped around, but it makes no difference to + * our arithmetic here. + */ + gd->arch.timer_reset_value += gd->arch.lastinc - now; + gd->arch.lastinc = now; + + /* Divide by 1000 to convert from us to ms */ + return gd->arch.timer_reset_value / 1000 - base; }
/* delay x useconds */ void __udelay(unsigned long usec) { - struct s5p_timer *const timer = s5p_get_base_timer(); - unsigned long tmo, tmp, count_value; - - count_value = readl(&timer->tcntb4); - - if (usec >= 1000) { - /* - * if "big" number, spread normalization - * to seconds - * 1. start to normalize for usec to ticks per sec - * 2. find number of "ticks" to wait to achieve target - * 3. finish normalize. - */ - tmo = usec / 1000; - tmo *= (CONFIG_SYS_HZ * count_value); - tmo /= 1000; - } else { - /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ * count_value; - tmo /= (1000 * 1000); - } - - /* get current timestamp */ - tmp = get_current_tick(); - - /* if setting this fordward will roll time stamp */ - /* reset "advancing" timestamp to 0, set lastinc value */ - /* else, set advancing stamp wake up time */ - if ((tmo + tmp + 1) < tmp) - reset_timer_masked(); - else - tmo += tmp; - - /* loop till event */ - while (get_current_tick() < tmo) - ; /* nop */ + unsigned long count_value; + + count_value = timer_get_us_down(); + while ((int)(count_value - timer_get_us_down()) < (int)usec) + ; }
void reset_timer_masked(void) @@ -109,30 +109,6 @@ void reset_timer_masked(void) gd->arch.tbl = 0; }
-unsigned long get_timer_masked(void) -{ - struct s5p_timer *const timer = s5p_get_base_timer(); - unsigned long count_value = readl(&timer->tcntb4); - - return get_current_tick() / count_value; -} - -unsigned long get_current_tick(void) -{ - struct s5p_timer *const timer = s5p_get_base_timer(); - unsigned long now = readl(&timer->tcnto4); - unsigned long count_value = readl(&timer->tcntb4); - - if (gd->arch.lastinc >= now) - gd->arch.tbl += gd->arch.lastinc - now; - else - gd->arch.tbl += gd->arch.lastinc + count_value - now; - - gd->arch.lastinc = now; - - return gd->arch.tbl; -} - /* * This function is derived from PowerPC code (read timebase as long long). * On ARM it just returns the timer value.
From: Che-Liang Chiou clchiou@chromium.org
timer_get_us returns the time in microseconds since a certain reference point of history. However, it does not guarantee to return an accurate time after a long period; instead, it wraps around (that is, the reference point is reset to some other point of history) after some periods. The frequency of wrapping around is about an hour (or 2^32 microseconds).
Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained
Signed-off-by: Che-Liang Chiou clchiou@chromium.org Signed-off-by: Akshay Saraswat akshay.s@samsung.com Acked-by: Simon Glass sjg@chromium.org --- Changes since v2: - None.
Changes since v1: - Added "Acked-by: Simon Glass".
arch/arm/cpu/armv7/s5p-common/timer.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index c48a297..de61405 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -90,6 +90,21 @@ unsigned long get_timer(unsigned long base) return gd->arch.timer_reset_value / 1000 - base; }
+unsigned long timer_get_us(void) +{ + static unsigned long base_time_us; + + struct s5p_timer *const timer = + (struct s5p_timer *)samsung_get_base_timer(); + unsigned long now_downward_us = readl(&timer->tcnto4); + + if (!base_time_us) + base_time_us = now_downward_us; + + /* Note that this timer counts downward. */ + return base_time_us - now_downward_us; +} + /* delay x useconds */ void __udelay(unsigned long usec) {
From: Gabe Black gabeblack@google.com
First, the "div" value was being used incorrectly to compute the frequency of the PWM timer. The value passed in is a constant which reflects the value that would be found in a configuration register, 0 to 4. That should correspond to a scaling factor of 1, 2, 4, 8, or 16, 1 << div, but div + 1 was being used instead.
Second, the reset value of the timers were being calculated to give an overall frequency, thrown out, and set to a maximum value. This was done so that PWM 4 could be used as the system clock by counting down from a high value, but it was applied indiscriminantly. It should at most be applied only to PWM 4.
This change also takes the opportunity to tidy up the pwm_init function.
Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly.
Signed-off-by: Gabe Black gabeblack@google.com Signed-off-by: Akshay Saraswat akshay.s@samsung.com Acked-by: Simon Glass sjg@chromium.org --- Changes since v2: - None.
Changes since v1: - Added "Acked-by: Simon Glass".
arch/arm/cpu/armv7/s5p-common/pwm.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index 3147f59..02156d1 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -143,7 +143,7 @@ int pwm_init(int pwm_id, int div, int invert) u32 val; const struct s5p_timer *pwm = (struct s5p_timer *)samsung_get_base_timer(); - unsigned long timer_rate_hz; + unsigned long ticks_per_period; unsigned int offset, prescaler;
/* @@ -167,20 +167,24 @@ int pwm_init(int pwm_id, int div, int invert) val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id); writel(val, &pwm->tcfg1);
- timer_rate_hz = get_pwm_clk() / ((prescaler + 1) * - (div + 1)); + if (pwm_id == 4) { + /* + * TODO(sjg): Use this as a countdown timer for now. We count + * down from the maximum value to 0, then reset. + */ + ticks_per_period = -1UL; + } else { + const unsigned long pwm_hz = 1000; + unsigned long timer_rate_hz = get_pwm_clk() / + ((prescaler + 1) * (1 << div));
- timer_rate_hz = timer_rate_hz / CONFIG_SYS_HZ; + ticks_per_period = timer_rate_hz / pwm_hz; + }
/* set count value */ offset = pwm_id * 3;
- /* - * TODO(sjg): Use this as a countdown timer for now. We count down - * from the maximum value to 0, then reset. - */ - timer_rate_hz = -1; - writel(timer_rate_hz, &pwm->tcntb0 + offset); + writel(ticks_per_period, &pwm->tcntb0 + offset);
val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id)); if (invert && (pwm_id < 4))
From: Gabe Black gabeblack@google.com
The pwm_config function in the exynos pwm driver divides by its period period parameter. A function was calling pwm_config with a 0ns period and a 0ns duty cycle. That doesn't actually make any sense physically, and results in a divide by zero in the driver. This change changes the parameters to be a 100000ns period and duty cycle.
Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly.
Signed-off-by: Gabe Black gabeblack@google.com Signed-off-by: Akshay Saraswat akshay.s@samsung.com Acked-by: Simon Glass sjg@chromium.org --- Changes since v2: - Fixed typo paremters in commit message.
Changes since v1: - Added "Acked-by: Simon Glass".
arch/arm/cpu/armv7/s5p-common/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index de61405..6a0fa58 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -58,7 +58,7 @@ int timer_init(void) { /* PWM Timer 4 */ pwm_init(4, MUX_DIV_4, 0); - pwm_config(4, 0, 0); + pwm_config(4, 100000, 100000); pwm_enable(4);
/* Use this as the current monotonic time in us */
From: Gabe Black gabeblack@google.com
Some small fixes in the exynos pwm driver:
1. NS_IN_HZ is non-sensical since these are not compatible units. This constant actually describes the number of nanoseconds in a second. Renamed it to NS_IN_SEC. Also dropped the unnecessary parenthesis. 2. The variable "period" is not used to hold a period, it's used to hold a frequency. Renamed it to "frequency". 3. tcmp is an unsigned value, so (tcmp < 0) will never be true and the if which checks that condition will never execute. Also, there should be no problem if the pwm never switches, so there's no reason to subtract one from tcmp and therefore no reason to compare it against zero. Removed both ifs. If they weren't removed, tcmp should be a signed value. 4. Add a check for a 0 period.
Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly.
Signed-off-by: Gabe Black gabeblack@google.com Signed-off-by: Akshay Saraswat akshay.s@samsung.com Acked-by: Simon Glass sjg@chromium.org --- Changes since v2: - None.
Changes since v1: - Added "Acked-by: Simon Glass".
arch/arm/cpu/armv7/s5p-common/pwm.c | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index 02156d1..6f401b8 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -70,7 +70,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) return tin_parent_rate / 16; }
-#define NS_IN_HZ (1000000000UL) +#define NS_IN_SEC 1000000000UL
int pwm_config(int pwm_id, int duty_ns, int period_ns) { @@ -79,7 +79,7 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns) unsigned int offset; unsigned long tin_rate; unsigned long tin_ns; - unsigned long period; + unsigned long frequency; unsigned long tcon; unsigned long tcnt; unsigned long tcmp; @@ -89,34 +89,24 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns) * fact that anything faster than 1GHz is easily representable * by 32bits. */ - if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ) + if (period_ns > NS_IN_SEC || duty_ns > NS_IN_SEC || period_ns == 0) return -ERANGE;
if (duty_ns > period_ns) return -EINVAL;
- period = NS_IN_HZ / period_ns; + frequency = NS_IN_SEC / period_ns;
/* Check to see if we are changing the clock rate of the PWM */ - tin_rate = pwm_calc_tin(pwm_id, period); + tin_rate = pwm_calc_tin(pwm_id, frequency);
- tin_ns = NS_IN_HZ / tin_rate; + tin_ns = NS_IN_SEC / tin_rate; tcnt = period_ns / tin_ns;
/* Note, counters count down */ tcmp = duty_ns / tin_ns; tcmp = tcnt - tcmp;
- /* - * the pwm hw only checks the compare register after a decrement, - * so the pin never toggles if tcmp = tcnt - */ - if (tcmp == tcnt) - tcmp--; - - if (tcmp < 0) - tcmp = 0; - /* Update the PWM register block. */ offset = pwm_id * 3; if (pwm_id < 4) {
From: Padmavathi Venna padma.v@samsung.com
Add generic api to get the frequency of the required peripherial. This API gets the source clock frequency and returns the required frequency by dividing with first and second dividers based on the requirement.
Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly.
Signed-off-by: Padmavathi Venna padma.v@samsung.com Signed-off-by: Akshay Saraswat akshay.s@samsung.com Acked-by: Simon Glass sjg@chromium.org --- Changes since v2: - Fixed typo peripherial to peripheral. - Made exynos5_get_periph_rate static. - Added an empty line. - Replaced "enum periph_id" with "int" in function arguments. - Removed "#include <asm/arch/periph.h>" from clk.h. - Added "Acked-by: Simon Glass".
Changes since v1: - Fixed few nits.
arch/arm/cpu/armv7/exynos/clock.c | 144 +++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 15 ++++ 2 files changed, 159 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 956427c..5860c8f 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -27,6 +27,49 @@ #include <asm/arch/clk.h> #include <asm/arch/periph.h>
+/* * + * This structure is to store the src bit, div bit and prediv bit + * positions of the peripheral clocks of the src and div registers + */ +struct clk_bit_info { + int8_t src_bit; + int8_t div_bit; + int8_t prediv_bit; +}; + +/* src_bit div_bit prediv_bit */ +static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { + {0, 0, -1}, + {4, 4, -1}, + {8, 8, -1}, + {12, 12, -1}, + {0, 0, 8}, + {4, 16, 24}, + {8, 0, 8}, + {12, 16, 24}, + {-1, -1, -1}, + {16, 0, 8}, + {20, 16, 24}, + {24, 0, 8}, + {0, 0, 4}, + {4, 12, 16}, + {-1, -1, -1}, + {-1, -1, -1}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, +}; + /* Epll Clock division values to achive different frequency output */ static struct set_epll_con_val exynos5_epll_div[] = { { 192000000, 0, 48, 3, 1, 0 }, @@ -201,6 +244,107 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return fout; }
+static unsigned long exynos5_get_periph_rate(int peripheral) +{ + struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; + unsigned long sclk, sub_clk; + unsigned int src, div, sub_div; + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric0); + break; + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + case PERIPH_ID_PWM4: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric3); + break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + src = readl(&clk->src_peric1); + div = readl(&clk->div_peric1); + break; + case PERIPH_ID_SPI2: + src = readl(&clk->src_peric1); + div = readl(&clk->div_peric2); + break; + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + src = readl(&clk->sclk_src_isp); + div = readl(&clk->sclk_div_isp); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + src = readl(&clk->src_fsys); + div = readl(&clk->div_fsys1); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + sclk = exynos5_get_pll_clk(MPLL); + sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit) + & 0x7) + 1; + div = ((readl(&clk->div_top0) >> bit_info->prediv_bit) + & 0x7) + 1; + return (sclk / sub_div) / div; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + }; + + src = (src >> bit_info->src_bit) & 0xf; + + switch (src) { + case EXYNOS_SRC_MPLL: + sclk = exynos5_get_pll_clk(MPLL); + break; + case EXYNOS_SRC_EPLL: + sclk = exynos5_get_pll_clk(EPLL); + break; + case EXYNOS_SRC_VPLL: + sclk = exynos5_get_pll_clk(VPLL); + break; + default: + return 0; + } + + /* Ratio clock division for this peripheral */ + sub_div = (div >> bit_info->div_bit) & 0xf; + sub_clk = sclk / (sub_div + 1); + + /* Pre-ratio clock division for SDMMC0 and 2 */ + if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { + div = (div >> bit_info->prediv_bit) & 0xff; + return sub_clk / (div + 1); + } + + return sub_clk; +} + +unsigned long clock_get_periph_rate(int peripheral) +{ + if (cpu_is_exynos5()) + return exynos5_get_periph_rate(peripheral); + else + return 0; +} + /* exynos4: return ARM clock frequency */ static unsigned long exynos4_get_arm_clk(void) { diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 1935b0b..73f8063 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -29,6 +29,12 @@ #define VPLL 4 #define BPLL 5
+enum pll_src_bit { + EXYNOS_SRC_MPLL = 6, + EXYNOS_SRC_EPLL, + EXYNOS_SRC_VPLL, +}; + unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_i2c_clk(void); @@ -44,4 +50,13 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); int set_epll_clk(unsigned long rate); int set_spi_clk(int periph_id, unsigned int rate);
+/** + * get the clk frequency of the required peripheral + * + * @param peripheral Peripheral id + * + * @return frequency of the peripheral clk + */ +unsigned long clock_get_periph_rate(int peripheral); + #endif
From: Padmavathi Venna padma.v@samsung.com
MPLL is selected as the source clk of pwm by default
Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly.
Signed-off-by: Padmavathi Venna padma.v@samsung.com Signed-off-by: Akshay Saraswat akshay.s@samsung.com Acked-by: Simon Glass sjg@chromium.org --- Changes since v2: - None.
Changes since v1: - Added "Acked-by: Simon Glass".
board/samsung/smdk5250/setup.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h index a159601..34d8bc3 100644 --- a/board/samsung/smdk5250/setup.h +++ b/board/samsung/smdk5250/setup.h @@ -343,7 +343,7 @@ #define TOP2_VAL 0x0110000
/* CLK_SRC_PERIC0 */ -#define PWM_SEL 0 +#define PWM_SEL 6 #define UART3_SEL 6 #define UART2_SEL 6 #define UART1_SEL 6
From: Padmavathi Venna padma.v@samsung.com
Use generic api to get the pwm clock frequency
Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly.
Signed-off-by: Padmavathi Venna padma.v@samsung.com Signed-off-by: Akshay Saraswat akshay.s@samsung.com Acked-by: Simon Glass sjg@chromium.org --- Changes since v2: - Replaced "exynos5_get_pwm_clk" with "clock_get_periph_rate" in get_pwm_clk instead of replacing everywhere. - Added "Acked-by: Simon Glass".
Changes since v1: - Restored get_pwm_clk call in case of non-exynos5 cpu.
arch/arm/cpu/armv7/exynos/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 5860c8f..1e54e47 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1354,7 +1354,7 @@ unsigned long get_i2c_clk(void) unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) - return exynos5_get_pwm_clk(); + return clock_get_periph_rate(PERIPH_ID_PWM0); else { if (proid_is_exynos4412()) return exynos4x12_get_pwm_clk();
As we shall now be using clock_get_periph_rate function. We find no reason for keeping code in function exynos5_get_pwm_clk. Hence, removing it.
Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- Changes since v2: - New patch.
arch/arm/cpu/armv7/exynos/clock.c | 21 --------------------- 1 file changed, 21 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 1e54e47..223660a 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -468,27 +468,6 @@ static unsigned long exynos4x12_get_pwm_clk(void) return pclk; }
-/* exynos5: return pwm clock frequency */ -static unsigned long exynos5_get_pwm_clk(void) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long pclk, sclk; - unsigned int ratio; - - /* - * CLK_DIV_PERIC3 - * PWM_RATIO [3:0] - */ - ratio = readl(&clk->div_peric3); - ratio = ratio & 0xf; - sclk = get_pll_clk(MPLL); - - pclk = sclk / (ratio + 1); - - return pclk; -} - /* exynos4: return uart clock frequency */ static unsigned long exynos4_get_uart_clk(int dev_index) {
Dear Akshay,
On 28/03/13 23:32, Akshay Saraswat wrote:
This patch set tries to fix few bugs in timer and re-organises PWM clock code.
Changes since v2:
- Patch-1: New patch.
- Patch-2: None.
- Patch-3: None.
- Patch-4: None.
- Patch-5: Fixed typo paremters in commit message.
- Patch-6: None.
- Patch-7: Added "Acked-by: Simon Glass".
- Patch-8: Fixed typo peripherial to peripheral.
- Made exynos5_get_periph_rate static.
- Added an empty line.
- Replaced "enum periph_id" with "int" in function arguments.
- Removed "#include <asm/arch/periph.h>" from clk.h.
- Added "Acked-by: Simon Glass".
- Patch-9: None.
- Patch-10: - Replaced "exynos5_get_pwm_clk" with "clock_get_periph_rate" in get_pwm_clk instead of replacing everywhere.
- Added "Acked-by: Simon Glass".
- Patch-11: New patch.
Changes since v1:
- Patch-1: Added "Acked-by: Simon Glass".
- Patch-2: Added "Acked-by: Simon Glass".
- Patch-3: Added "Acked-by: Simon Glass".
- Patch-4: Added "Acked-by: Simon Glass".
- Patch-5: Added "Acked-by: Simon Glass".
- Patch-6: None.
- Patch-7: Fixed few nits.
- Patch-8: Added "Acked-by: Simon Glass".
- Patch-9: Restored get_pwm_clk call in case of non-exynos5 cpu.
Akshay Saraswat (11): Exynos5: config: enable time command Exynos: Change get_timer() to work correctly Exynos: Add timer_get_us function Exynos: pwm: Fix two bugs in the exynos pwm configuration code Exynos: Avoid a divide by zero by specifying a non-zero period for pwm 4 Exynos: Tidy up the pwm_config function in the exynos pwm driver Exynos: Add peripherial id for pwm Exynos: clock: Add generic api to get the clk freq Exynos: clock: Correct pwm source clk selection Exynos: pwm: Use generic api to get pwm clk freq Exynos: pwm: Remove dead code of function exynos5_get_pwm_clk
arch/arm/cpu/armv7/exynos/clock.c | 167 ++++++++++++++++++++++++++---- arch/arm/cpu/armv7/s5p-common/pwm.c | 42 ++++---- arch/arm/cpu/armv7/s5p-common/timer.c | 117 ++++++++++----------- arch/arm/include/asm/arch-exynos/clk.h | 15 +++ arch/arm/include/asm/arch-exynos/periph.h | 5 + board/samsung/smdk5250/setup.h | 2 +- include/configs/exynos5250-dt.h | 3 + 7 files changed, 244 insertions(+), 107 deletions(-)
The patch-7 seems to did not reached at mailing list. If not, please let me know a link of patchwork.
Thanks, Minkyu Kang.
participants (2)
-
Akshay Saraswat -
Minkyu Kang