[U-Boot] [PATCH v2 1/3] rockchip: rk3036: clean mask definition for cru reg
Embeded the shift in mask MACRO definition in cru header file and clock driver.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
Changes in v2: - split into two patches
arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 70 +++++++++++----------- drivers/clk/rockchip/clk_rk3036.c | 79 +++++++++++-------------- 2 files changed, 69 insertions(+), 80 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h index aaef4b9..eb5eb40 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h @@ -68,102 +68,102 @@ struct pll_div {
enum { /* PLLCON0*/ - PLL_POSTDIV1_MASK = 7, PLL_POSTDIV1_SHIFT = 12, - PLL_FBDIV_MASK = 0xfff, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff,
/* PLLCON1 */ - PLL_DSMPD_MASK = 1, + PLL_RST_SHIFT = 14, PLL_DSMPD_SHIFT = 12, - PLL_LOCK_STATUS_MASK = 1, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, PLL_LOCK_STATUS_SHIFT = 10, - PLL_POSTDIV2_MASK = 7, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, PLL_POSTDIV2_SHIFT = 6, - PLL_REFDIV_MASK = 0x3f, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, PLL_REFDIV_SHIFT = 0, - PLL_RST_SHIFT = 14, + PLL_REFDIV_MASK = 0x3f,
/* CRU_MODE */ - GPLL_MODE_MASK = 3, GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, GPLL_MODE_SLOW = 0, GPLL_MODE_NORM, GPLL_MODE_DEEP, - DPLL_MODE_MASK = 1, DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, DPLL_MODE_SLOW = 0, DPLL_MODE_NORM, - APLL_MODE_MASK = 1, APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, APLL_MODE_SLOW = 0, APLL_MODE_NORM,
/* CRU_CLK_SEL0_CON */ - CPU_CLK_PLL_SEL_MASK = 3, - CPU_CLK_PLL_SEL_SHIFT = 14, - CPU_CLK_PLL_SEL_APLL = 0, - CPU_CLK_PLL_SEL_DPLL, - CPU_CLK_PLL_SEL_GPLL, - ACLK_CPU_DIV_MASK = 0x1f, - ACLK_CPU_DIV_SHIFT = 8, - CORE_CLK_PLL_SEL_MASK = 1, + BUS_ACLK_PLL_SEL_SHIFT = 14, + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, + BUS_ACLK_PLL_SEL_APLL = 0, + BUS_ACLK_PLL_SEL_DPLL, + BUS_ACLK_PLL_SEL_GPLL, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, CORE_CLK_PLL_SEL_APLL = 0, CORE_CLK_PLL_SEL_GPLL, - CORE_DIV_CON_MASK = 0x1f, CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
/* CRU_CLK_SEL1_CON */ - CPU_PCLK_DIV_MASK = 7, - CPU_PCLK_DIV_SHIFT = 12, - CPU_HCLK_DIV_MASK = 3, - CPU_HCLK_DIV_SHIFT = 8, - CORE_ACLK_DIV_MASK = 7, + BUS_PCLK_DIV_SHIFT = 12, + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 8, + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, CORE_ACLK_DIV_SHIFT = 4, - CORE_PERI_DIV_MASK = 0xf, + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, CORE_PERI_DIV_SHIFT = 0, + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
/* CRU_CLKSEL10_CON */ - PERI_PLL_SEL_MASK = 3, PERI_PLL_SEL_SHIFT = 14, + PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, PERI_PLL_APLL = 0, PERI_PLL_DPLL, PERI_PLL_GPLL, - PERI_PCLK_DIV_MASK = 3, PERI_PCLK_DIV_SHIFT = 12, - PERI_HCLK_DIV_MASK = 3, + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, PERI_HCLK_DIV_SHIFT = 8, - PERI_ACLK_DIV_MASK = 0x1f, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
/* CRU_CLKSEL11_CON */ - SDIO_DIV_MASK = 0x7f, SDIO_DIV_SHIFT = 8, - MMC0_DIV_MASK = 0x7f, + SDIO_DIV_MASK = 0x7f << SDIO_DIV_SHIFT, MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x7f << MMC0_DIV_SHIFT,
/* CRU_CLKSEL12_CON */ - EMMC_PLL_MASK = 3, EMMC_PLL_SHIFT = 12, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, EMMC_SEL_APLL = 0, EMMC_SEL_DPLL, EMMC_SEL_GPLL, EMMC_SEL_24M, - SDIO_PLL_MASK = 3, SDIO_PLL_SHIFT = 10, + SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, SDIO_SEL_APLL = 0, SDIO_SEL_DPLL, SDIO_SEL_GPLL, SDIO_SEL_24M, - MMC0_PLL_MASK = 3, MMC0_PLL_SHIFT = 8, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, MMC0_SEL_APLL = 0, MMC0_SEL_DPLL, MMC0_SEL_GPLL, MMC0_SEL_24M, - EMMC_DIV_MASK = 0x7f, EMMC_DIV_SHIFT = 0, + EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT,
/* CRU_SOFTRST5_CON */ DDRCTRL_PSRST_SHIFT = 11, diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 7e3bf96..96c4c21 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -65,12 +65,11 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
rk_clrsetreg(&pll->con0, - PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, + PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); - rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | - PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, - (div->postdiv2 << PLL_POSTDIV2_SHIFT | - div->refdiv << PLL_REFDIV_SHIFT)); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, + (div->postdiv2 << PLL_POSTDIV2_SHIFT | + div->refdiv << PLL_REFDIV_SHIFT));
/* waiting for pll lock */ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) @@ -87,8 +86,7 @@ static void rkclk_init(struct rk3036_cru *cru)
/* pll enter slow-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - APLL_MODE_MASK << APLL_MODE_SHIFT, + GPLL_MODE_MASK | APLL_MODE_MASK, GPLL_MODE_SLOW << GPLL_MODE_SHIFT | APLL_MODE_SLOW << APLL_MODE_SHIFT);
@@ -97,8 +95,8 @@ static void rkclk_init(struct rk3036_cru *cru) rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
/* - * select apll as core clock pll source and - * set up dependent divisors for PCLK/HCLK and ACLK clocks. + * select apll as cpu/core clock pll source and + * set up dependent divisors for PERI and ACLK clocks. * core hz : apll = 1:1 */ aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; @@ -108,19 +106,17 @@ static void rkclk_init(struct rk3036_cru *cru) assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
rk_clrsetreg(&cru->cru_clksel_con[0], - CORE_CLK_PLL_SEL_MASK << CORE_CLK_PLL_SEL_SHIFT | - CORE_DIV_CON_MASK << CORE_DIV_CON_SHIFT, + CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 0 << CORE_DIV_CON_SHIFT);
rk_clrsetreg(&cru->cru_clksel_con[1], - CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT | - CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT, + CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, aclk_div << CORE_ACLK_DIV_SHIFT | pclk_div << CORE_PERI_DIV_SHIFT);
/* - * select apll as cpu clock pll source and + * select apll as pd_bus clock pll source and * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ aclk_div = APLL_HZ / CPU_ACLK_HZ - 1; @@ -133,19 +129,17 @@ static void rkclk_init(struct rk3036_cru *cru) assert((hclk_div + 1) * CPU_HCLK_HZ == APLL_HZ && hclk_div < 0x3);
rk_clrsetreg(&cru->cru_clksel_con[0], - CPU_CLK_PLL_SEL_MASK << CPU_CLK_PLL_SEL_SHIFT | - ACLK_CPU_DIV_MASK << ACLK_CPU_DIV_SHIFT, - CPU_CLK_PLL_SEL_APLL << CPU_CLK_PLL_SEL_SHIFT | - aclk_div << ACLK_CPU_DIV_SHIFT); + BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, + BUS_ACLK_PLL_SEL_APLL << BUS_ACLK_PLL_SEL_SHIFT | + aclk_div << BUS_ACLK_DIV_SHIFT);
rk_clrsetreg(&cru->cru_clksel_con[1], - CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT | - CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT, - pclk_div << CPU_PCLK_DIV_SHIFT | - hclk_div << CPU_HCLK_DIV_SHIFT); + BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, + pclk_div << BUS_PCLK_DIV_SHIFT | + hclk_div << BUS_HCLK_DIV_SHIFT);
/* - * select gpll as peri clock pll source and + * select gpll as pd_peri bus clock source and * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; @@ -160,10 +154,8 @@ static void rkclk_init(struct rk3036_cru *cru) PERI_ACLK_HZ && pclk_div < 0x8);
rk_clrsetreg(&cru->cru_clksel_con[10], - PERI_PLL_SEL_MASK << PERI_PLL_SEL_SHIFT | - PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | - PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | - PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | + PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | pclk_div << PERI_PCLK_DIV_SHIFT | hclk_div << PERI_HCLK_DIV_SHIFT | @@ -171,8 +163,7 @@ static void rkclk_init(struct rk3036_cru *cru)
/* PLL enter normal-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - APLL_MODE_MASK << APLL_MODE_SHIFT, + GPLL_MODE_MASK | APLL_MODE_MASK, GPLL_MODE_NORM << GPLL_MODE_SHIFT | APLL_MODE_NORM << APLL_MODE_SHIFT); } @@ -189,9 +180,9 @@ static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, GPLL_MODE_SHIFT, 0xff }; - static u8 clk_mask[CLK_COUNT] = { - 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, - GPLL_MODE_MASK, 0xff + static u32 clk_mask[CLK_COUNT] = { + 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, + GPLL_MODE_MASK, 0xffffffff }; uint shift; uint mask; @@ -200,18 +191,18 @@ static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, shift = clk_shift[clk_id]; mask = clk_mask[clk_id];
- switch ((con >> shift) & mask) { + switch ((con & mask) >> shift) { case GPLL_MODE_SLOW: return OSC_HZ; case GPLL_MODE_NORM:
/* normal mode */ con = readl(&pll->con0); - postdiv1 = (con >> PLL_POSTDIV1_SHIFT) & PLL_POSTDIV1_MASK; - fbdiv = (con >> PLL_FBDIV_SHIFT) & PLL_FBDIV_MASK; + postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; + fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; con = readl(&pll->con1); - postdiv2 = (con >> PLL_POSTDIV2_SHIFT) & PLL_POSTDIV2_MASK; - refdiv = (con >> PLL_REFDIV_SHIFT) & PLL_REFDIV_MASK; + postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; + refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; case GPLL_MODE_DEEP: default: @@ -229,13 +220,13 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, switch (periph) { case HCLK_EMMC: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; - div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; break; case HCLK_SDIO: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; - div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; + div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; break; default: return -EINVAL; @@ -266,15 +257,13 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, switch (periph) { case HCLK_EMMC: rk_clrsetreg(&cru->cru_clksel_con[12], - EMMC_PLL_MASK << EMMC_PLL_SHIFT | - EMMC_DIV_MASK << EMMC_DIV_SHIFT, + EMMC_PLL_MASK | EMMC_DIV_MASK, mux << EMMC_PLL_SHIFT | (src_clk_div - 1) << EMMC_DIV_SHIFT); break; case HCLK_SDIO: rk_clrsetreg(&cru->cru_clksel_con[11], - MMC0_PLL_MASK << MMC0_PLL_SHIFT | - MMC0_DIV_MASK << MMC0_DIV_SHIFT, + MMC0_PLL_MASK | MMC0_DIV_MASK, mux << MMC0_PLL_SHIFT | (src_clk_div - 1) << MMC0_DIV_SHIFT); break;
- hclk/pclk_div range should use '<=' instead of '<' - use GPLL for pd_bus clock source - pd_bus HCLK/PCLK clock rate should not bigger than ACLK
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 6 +++--- drivers/clk/rockchip/clk_rk3036.c | 18 +++++++++--------- 2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h index eb5eb40..22278e1 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h @@ -16,9 +16,9 @@ #define CORE_PERI_HZ 150000000 #define CORE_ACLK_HZ 300000000
-#define CPU_ACLK_HZ 150000000 -#define CPU_HCLK_HZ 300000000 -#define CPU_PCLK_HZ 300000000 +#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000
#define PERI_ACLK_HZ 148500000 #define PERI_HCLK_HZ 148500000 diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 96c4c21..1fadb0f 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -116,21 +116,21 @@ static void rkclk_init(struct rk3036_cru *cru) pclk_div << CORE_PERI_DIV_SHIFT);
/* - * select apll as pd_bus clock pll source and + * select apll as pd_bus bus clock source and * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ - aclk_div = APLL_HZ / CPU_ACLK_HZ - 1; - assert((aclk_div + 1) * CPU_ACLK_HZ == APLL_HZ && aclk_div < 0x1f); + aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; + assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
- pclk_div = APLL_HZ / CPU_PCLK_HZ - 1; - assert((pclk_div + 1) * CPU_PCLK_HZ == APLL_HZ && pclk_div < 0x7); + pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; + assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
- hclk_div = APLL_HZ / CPU_HCLK_HZ - 1; - assert((hclk_div + 1) * CPU_HCLK_HZ == APLL_HZ && hclk_div < 0x3); + hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; + assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
rk_clrsetreg(&cru->cru_clksel_con[0], BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, - BUS_ACLK_PLL_SEL_APLL << BUS_ACLK_PLL_SEL_SHIFT | + BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | aclk_div << BUS_ACLK_DIV_SHIFT);
rk_clrsetreg(&cru->cru_clksel_con[1], @@ -147,7 +147,7 @@ static void rkclk_init(struct rk3036_cru *cru)
hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); assert((1 << hclk_div) * PERI_HCLK_HZ == - PERI_ACLK_HZ && (pclk_div < 0x4)); + PERI_ACLK_HZ && (hclk_div < 0x4));
pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); assert((1 << pclk_div) * PERI_PCLK_HZ ==
On 15 May 2017 at 06:52, Kever Yang kever.yang@rock-chips.com wrote:
- hclk/pclk_div range should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 6 +++--- drivers/clk/rockchip/clk_rk3036.c | 18 +++++++++--------- 2 files changed, 12 insertions(+), 12 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On 15 May 2017 at 06:52, Kever Yang kever.yang@rock-chips.com wrote:
- hclk/pclk_div range should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 6 +++--- drivers/clk/rockchip/clk_rk3036.c | 18 +++++++++--------- 2 files changed, 12 insertions(+), 12 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro definition in grf header file and pinctrl driver.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
Changes in v2: - add grf code clean
arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 133 ++++++++++++------------ drivers/pinctrl/rockchip/pinctrl_rk3036.c | 44 +++----- 2 files changed, 82 insertions(+), 95 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h index 72d133c..7625f24 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h @@ -83,57 +83,56 @@ check_member(rk3036_grf, sdmmc_det_cnt, 0x304); /* GRF_GPIO0A_IOMUX */ enum { GPIO0A3_SHIFT = 6, - GPIO0A3_MASK = 1, + GPIO0A3_MASK = 1 << GPIO0A3_SHIFT, GPIO0A3_GPIO = 0, GPIO0A3_I2C1_SDA,
GPIO0A2_SHIFT = 4, - GPIO0A2_MASK = 1, + GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, GPIO0A2_GPIO = 0, GPIO0A2_I2C1_SCL,
GPIO0A1_SHIFT = 2, - GPIO0A1_MASK = 3, + GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, GPIO0A1_GPIO = 0, GPIO0A1_I2C0_SDA, GPIO0A1_PWM2,
GPIO0A0_SHIFT = 0, - GPIO0A0_MASK = 3, + GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, GPIO0A0_GPIO = 0, GPIO0A0_I2C0_SCL, GPIO0A0_PWM1, - };
/* GRF_GPIO0B_IOMUX */ enum { GPIO0B6_SHIFT = 12, - GPIO0B6_MASK = 3, + GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, GPIO0B6_GPIO = 0, GPIO0B6_MMC1_D3, GPIO0B6_I2S1_SCLK,
GPIO0B5_SHIFT = 10, - GPIO0B5_MASK = 3, + GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, GPIO0B5_GPIO = 0, GPIO0B5_MMC1_D2, GPIO0B5_I2S1_SDI,
GPIO0B4_SHIFT = 8, - GPIO0B4_MASK = 3, + GPIO0B4_MASK = 3 << GPIO0B4_SHIFT, GPIO0B4_GPIO = 0, GPIO0B4_MMC1_D1, GPIO0B4_I2S1_LRCKTX,
GPIO0B3_SHIFT = 6, - GPIO0B3_MASK = 3, + GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, GPIO0B3_GPIO = 0, GPIO0B3_MMC1_D0, GPIO0B3_I2S1_LRCKRX,
GPIO0B1_SHIFT = 2, - GPIO0B1_MASK = 3, + GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, GPIO0B1_GPIO = 0, GPIO0B1_MMC1_CLKOUT, GPIO0B1_I2S1_MCLK, @@ -148,28 +147,28 @@ enum { /* GRF_GPIO0C_IOMUX */ enum { GPIO0C4_SHIFT = 8, - GPIO0C4_MASK = 1, + GPIO0C4_MASK = 1 << GPIO0C4_SHIFT, GPIO0C4_GPIO = 0, GPIO0C4_DRIVE_VBUS,
GPIO0C3_SHIFT = 6, - GPIO0C3_MASK = 1, + GPIO0C3_MASK = 1 << GPIO0C3_SHIFT, GPIO0C3_GPIO = 0, GPIO0C3_UART0_CTSN,
GPIO0C2_SHIFT = 4, - GPIO0C2_MASK = 1, + GPIO0C2_MASK = 1 << GPIO0C2_SHIFT, GPIO0C2_GPIO = 0, GPIO0C2_UART0_RTSN,
GPIO0C1_SHIFT = 2, - GPIO0C1_MASK = 1, + GPIO0C1_MASK = 1 << GPIO0C1_SHIFT, GPIO0C1_GPIO = 0, GPIO0C1_UART0_SIN,
GPIO0C0_SHIFT = 0, - GPIO0C0_MASK = 1, + GPIO0C0_MASK = 1 << GPIO0C0_SHIFT, GPIO0C0_GPIO = 0, GPIO0C0_UART0_SOUT, }; @@ -177,17 +176,17 @@ enum { /* GRF_GPIO0D_IOMUX */ enum { GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 1, + GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, GPIO0D4_GPIO = 0, GPIO0D4_SPDIF,
GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 1, + GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, GPIO0D3_GPIO = 0, GPIO0D3_PWM3,
GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 1, + GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, GPIO0D2_GPIO = 0, GPIO0D2_PWM0, }; @@ -195,33 +194,33 @@ enum { /* GRF_GPIO1A_IOMUX */ enum { GPIO1A5_SHIFT = 10, - GPIO1A5_MASK = 1, + GPIO1A5_MASK = 1 << GPIO1A5_SHIFT, GPIO1A5_GPIO = 0, GPIO1A5_I2S_SDI,
GPIO1A4_SHIFT = 8, - GPIO1A4_MASK = 1, + GPIO1A4_MASK = 1 << GPIO1A4_SHIFT, GPIO1A4_GPIO = 0, GPIO1A4_I2S_SD0,
GPIO1A3_SHIFT = 6, - GPIO1A3_MASK = 1, + GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, GPIO1A3_GPIO = 0, GPIO1A3_I2S_LRCKTX,
GPIO1A2_SHIFT = 4, - GPIO1A2_MASK = 6, + GPIO1A2_MASK = 6 << GPIO1A2_SHIFT, GPIO1A2_GPIO = 0, GPIO1A2_I2S_LRCKRX, GPIO1A2_I2S_PWM1_0,
GPIO1A1_SHIFT = 2, - GPIO1A1_MASK = 1, + GPIO1A1_MASK = 1 << GPIO1A1_SHIFT, GPIO1A1_GPIO = 0, GPIO1A1_I2S_SCLK,
GPIO1A0_SHIFT = 0, - GPIO1A0_MASK = 1, + GPIO1A0_MASK = 1 << GPIO1A0_SHIFT, GPIO1A0_GPIO = 0, GPIO1A0_I2S_MCLK,
@@ -230,27 +229,27 @@ enum { /* GRF_GPIO1B_IOMUX */ enum { GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = 1, + GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, GPIO1B7_GPIO = 0, GPIO1B7_MMC0_CMD,
GPIO1B3_SHIFT = 6, - GPIO1B3_MASK = 1, + GPIO1B3_MASK = 1 << GPIO1B3_SHIFT, GPIO1B3_GPIO = 0, GPIO1B3_HDMI_HPD,
GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 1, + GPIO1B2_MASK = 1 << GPIO1B2_SHIFT, GPIO1B2_GPIO = 0, GPIO1B2_HDMI_SCL,
GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 1, + GPIO1B1_MASK = 1 << GPIO1B1_SHIFT, GPIO1B1_GPIO = 0, GPIO1B1_HDMI_SDA,
GPIO1B0_SHIFT = 0, - GPIO1B0_MASK = 1, + GPIO1B0_MASK = 1 << GPIO1B0_SHIFT, GPIO1B0_GPIO = 0, GPIO1B0_HDMI_CEC, }; @@ -258,36 +257,36 @@ enum { /* GRF_GPIO1C_IOMUX */ enum { GPIO1C5_SHIFT = 10, - GPIO1C5_MASK = 3, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, GPIO1C5_GPIO = 0, GPIO1C5_MMC0_D3, GPIO1C5_JTAG_TMS,
GPIO1C4_SHIFT = 8, - GPIO1C4_MASK = 3, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, GPIO1C4_GPIO = 0, GPIO1C4_MMC0_D2, GPIO1C4_JTAG_TCK,
GPIO1C3_SHIFT = 6, - GPIO1C3_MASK = 3, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, GPIO1C3_GPIO = 0, GPIO1C3_MMC0_D1, GPIO1C3_UART2_SOUT,
GPIO1C2_SHIFT = 4, - GPIO1C2_MASK = 3, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , GPIO1C2_GPIO = 0, GPIO1C2_MMC0_D0, GPIO1C2_UART2_SIN,
GPIO1C1_SHIFT = 2, - GPIO1C1_MASK = 1, + GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, GPIO1C1_GPIO = 0, GPIO1C1_MMC0_DETN,
GPIO1C0_SHIFT = 0, - GPIO1C0_MASK = 1, + GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, GPIO1C0_GPIO = 0, GPIO1C0_MMC0_CLKOUT, }; @@ -295,56 +294,56 @@ enum { /* GRF_GPIO1D_IOMUX */ enum { GPIO1D7_SHIFT = 14, - GPIO1D7_MASK = 3, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, GPIO1D7_GPIO = 0, GPIO1D7_NAND_D7, GPIO1D7_EMMC_D7, GPIO1D7_SPI_CSN1,
GPIO1D6_SHIFT = 12, - GPIO1D6_MASK = 3, + GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, GPIO1D6_GPIO = 0, GPIO1D6_NAND_D6, GPIO1D6_EMMC_D6, GPIO1D6_SPI_CSN0,
GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = 3, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, GPIO1D5_GPIO = 0, GPIO1D5_NAND_D5, GPIO1D5_EMMC_D5, GPIO1D5_SPI_TXD,
GPIO1D4_SHIFT = 8, - GPIO1D4_MASK = 3, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, GPIO1D4_GPIO = 0, GPIO1D4_NAND_D4, GPIO1D4_EMMC_D4, GPIO1D4_SPI_RXD,
GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 3, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, GPIO1D3_GPIO = 0, GPIO1D3_NAND_D3, GPIO1D3_EMMC_D3, GPIO1D3_SFC_SIO3,
GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 3, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, GPIO1D2_GPIO = 0, GPIO1D2_NAND_D2, GPIO1D2_EMMC_D2, GPIO1D2_SFC_SIO2,
GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 3, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, GPIO1D1_GPIO = 0, GPIO1D1_NAND_D1, GPIO1D1_EMMC_D1, GPIO1D1_SFC_SIO1,
GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 3, + GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, GPIO1D0_GPIO = 0, GPIO1D0_NAND_D0, GPIO1D0_EMMC_D0, @@ -354,42 +353,42 @@ enum { /* GRF_GPIO2A_IOMUX */ enum { GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 1, + GPIO2A7_MASK = 1 << GPIO2A7_SHIFT, GPIO2A7_GPIO = 0, GPIO2A7_TESTCLK_OUT,
GPIO2A6_SHIFT = 12, - GPIO2A6_MASK = 1, + GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, GPIO2A6_GPIO = 0, GPIO2A6_NAND_CS0,
GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, GPIO2A4_GPIO = 0, GPIO2A4_NAND_RDY, GPIO2A4_EMMC_CMD, GPIO2A3_SFC_CLK,
GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, GPIO2A3_GPIO = 0, GPIO2A3_NAND_RDN, GPIO2A4_SFC_CSN1,
GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, GPIO2A2_GPIO = 0, GPIO2A2_NAND_WRN, GPIO2A4_SFC_CSN0,
GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, GPIO2A1_GPIO = 0, GPIO2A1_NAND_CLE, GPIO2A1_EMMC_CLKOUT,
GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, GPIO2A0_GPIO = 0, GPIO2A0_NAND_ALE, GPIO2A0_SPI_CLK, @@ -398,28 +397,28 @@ enum { /* GRF_GPIO2B_IOMUX */ enum { GPIO2B7_SHIFT = 14, - GPIO2B7_MASK = 1, + GPIO2B7_MASK = 1 << GPIO2B7_SHIFT, GPIO2B7_GPIO = 0, GPIO2B7_MAC_RXER,
GPIO2B6_SHIFT = 12, - GPIO2B6_MASK = 3, + GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, GPIO2B6_GPIO = 0, GPIO2B6_MAC_CLKOUT, GPIO2B6_MAC_CLKIN,
GPIO2B5_SHIFT = 10, - GPIO2B5_MASK = 1, + GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, GPIO2B5_GPIO = 0, GPIO2B5_MAC_TXEN,
GPIO2B4_SHIFT = 8, - GPIO2B4_MASK = 1, + GPIO2B4_MASK = 1 << GPIO2B4_SHIFT, GPIO2B4_GPIO = 0, GPIO2B4_MAC_MDIO,
GPIO2B2_SHIFT = 4, - GPIO2B2_MASK = 1, + GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, GPIO2B2_GPIO = 0, GPIO2B2_MAC_CRS, }; @@ -427,43 +426,43 @@ enum { /* GRF_GPIO2C_IOMUX */ enum { GPIO2C7_SHIFT = 14, - GPIO2C7_MASK = 3, + GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, GPIO2C7_GPIO = 0, GPIO2C7_UART1_SOUT, GPIO2C7_TESTCLK_OUT1,
GPIO2C6_SHIFT = 12, - GPIO2C6_MASK = 1, + GPIO2C6_MASK = 1 << GPIO2C6_SHIFT, GPIO2C6_GPIO = 0, GPIO2C6_UART1_SIN,
GPIO2C5_SHIFT = 10, - GPIO2C5_MASK = 1, + GPIO2C5_MASK = 1 << GPIO2C5_SHIFT, GPIO2C5_GPIO = 0, GPIO2C5_I2C2_SCL,
GPIO2C4_SHIFT = 8, - GPIO2C4_MASK = 1, + GPIO2C4_MASK = 1 << GPIO2C4_SHIFT, GPIO2C4_GPIO = 0, GPIO2C4_I2C2_SDA,
GPIO2C3_SHIFT = 6, - GPIO2C3_MASK = 1, + GPIO2C3_MASK = 1 << GPIO2C3_SHIFT, GPIO2C3_GPIO = 0, GPIO2C3_MAC_TXD0,
GPIO2C2_SHIFT = 4, - GPIO2C2_MASK = 1, + GPIO2C2_MASK = 1 << GPIO2C2_SHIFT, GPIO2C2_GPIO = 0, GPIO2C2_MAC_TXD1,
GPIO2C1_SHIFT = 2, - GPIO2C1_MASK = 1, + GPIO2C1_MASK = 1 << GPIO2C1_SHIFT, GPIO2C1_GPIO = 0, GPIO2C1_MAC_RXD0,
GPIO2C0_SHIFT = 0, - GPIO2C0_MASK = 1, + GPIO2C0_MASK = 1 << GPIO2C0_SHIFT, GPIO2C0_GPIO = 0, GPIO2C0_MAC_RXD1, }; @@ -471,22 +470,22 @@ enum { /* GRF_GPIO2D_IOMUX */ enum { GPIO2D6_SHIFT = 12, - GPIO2D6_MASK = 1, + GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, GPIO2D6_GPIO = 0, GPIO2D6_I2S_SDO1,
GPIO2D5_SHIFT = 10, - GPIO2D5_MASK = 1, + GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, GPIO2D5_GPIO = 0, GPIO2D5_I2S_SDO2,
GPIO2D4_SHIFT = 8, - GPIO2D4_MASK = 1, + GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, GPIO2D4_GPIO = 0, GPIO2D4_I2S_SDO3,
GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 1, + GPIO2D1_MASK = 1 << GPIO2D1_SHIFT, GPIO2D1_GPIO = 0, GPIO2D1_MAC_MDC, }; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c index 8d42584..9215d6c 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c @@ -26,19 +26,19 @@ static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id) { switch (pwm_id) { case PERIPH_ID_PWM0: - rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK << GPIO0D2_SHIFT, + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK, GPIO0D2_PWM0 << GPIO0D2_SHIFT); break; case PERIPH_ID_PWM1: - rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK << GPIO0A0_SHIFT, + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK, GPIO0A0_PWM1 << GPIO0A0_SHIFT); break; case PERIPH_ID_PWM2: - rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK << GPIO0A1_SHIFT, + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK, GPIO0A1_PWM2 << GPIO0A1_SHIFT); break; case PERIPH_ID_PWM3: - rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK << GPIO0D3_SHIFT, + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK, GPIO0D3_PWM3 << GPIO0D3_SHIFT); break; default: @@ -52,23 +52,20 @@ static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id) switch (i2c_id) { case PERIPH_ID_I2C0: rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A1_MASK << GPIO0A1_SHIFT | - GPIO0A0_MASK << GPIO0A0_SHIFT, + GPIO0A1_MASK | GPIO0A0_MASK, GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT | GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
break; case PERIPH_ID_I2C1: rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A3_MASK << GPIO0A3_SHIFT | - GPIO0A2_MASK << GPIO0A2_SHIFT, + GPIO0A3_MASK | GPIO0A2_MASK, GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT | GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT); break; case PERIPH_ID_I2C2: rk_clrsetreg(&grf->gpio2c_iomux, - GPIO2C5_MASK << GPIO2C5_SHIFT | - GPIO2C4_MASK << GPIO2C4_SHIFT, + GPIO2C5_MASK | GPIO2C4_MASK, GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT | GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
@@ -80,24 +77,20 @@ static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs) { switch (cs) { case 0: - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D6_MASK << GPIO1D6_SHIFT, + rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D6_MASK, GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT); break; case 1: - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D7_MASK << GPIO1D7_SHIFT, + rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D7_MASK, GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT); break; } rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D5_MASK << GPIO1D5_SHIFT | - GPIO1D4_MASK << GPIO1D4_SHIFT, + GPIO1D5_MASK | GPIO1D4_MASK, GPIO1D5_SPI_TXD << GPIO1D5_SHIFT | GPIO1D4_SPI_RXD << GPIO1D4_SHIFT);
- rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A0_MASK << GPIO2A0_SHIFT, + rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A0_MASK, GPIO2A0_SPI_CLK << GPIO2A0_SHIFT); }
@@ -106,10 +99,8 @@ static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id) switch (uart_id) { case PERIPH_ID_UART0: rk_clrsetreg(&grf->gpio0c_iomux, - GPIO0C3_MASK << GPIO0C3_SHIFT | - GPIO0C2_MASK << GPIO0C2_SHIFT | - GPIO0C1_MASK << GPIO0C1_SHIFT | - GPIO0C0_MASK << GPIO0C0_SHIFT, + GPIO0C3_MASK | GPIO0C2_MASK | + GPIO0C1_MASK | GPIO0C0_MASK, GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT | GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT | GPIO0C1_UART0_SIN << GPIO0C1_SHIFT | @@ -117,15 +108,13 @@ static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id) break; case PERIPH_ID_UART1: rk_clrsetreg(&grf->gpio2c_iomux, - GPIO2C7_MASK << GPIO2C7_SHIFT | - GPIO2C6_MASK << GPIO2C6_SHIFT, + GPIO2C7_MASK | GPIO2C6_MASK, GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT | GPIO2C6_UART1_SIN << GPIO2C6_SHIFT); break; case PERIPH_ID_UART2: rk_clrsetreg(&grf->gpio1c_iomux, - GPIO1C3_MASK << GPIO1C3_SHIFT | - GPIO1C2_MASK << GPIO1C2_SHIFT, + GPIO1C3_MASK | GPIO1C2_MASK, GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); break; @@ -146,8 +135,7 @@ static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id) GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT | GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT); rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A4_MASK << GPIO2A4_SHIFT | - GPIO2A1_MASK << GPIO2A1_SHIFT, + GPIO2A4_MASK | GPIO2A1_MASK, GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT | GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT); break;
On 15 May 2017 at 06:52, Kever Yang kever.yang@rock-chips.com wrote:
U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro definition in grf header file and pinctrl driver.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Changes in v2:
- add grf code clean
arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 133 ++++++++++++------------ drivers/pinctrl/rockchip/pinctrl_rk3036.c | 44 +++----- 2 files changed, 82 insertions(+), 95 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On 15 May 2017 at 06:52, Kever Yang kever.yang@rock-chips.com wrote:
U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro definition in grf header file and pinctrl driver.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Changes in v2:
- add grf code clean
arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 133 ++++++++++++------------ drivers/pinctrl/rockchip/pinctrl_rk3036.c | 44 +++----- 2 files changed, 82 insertions(+), 95 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
On 15 May 2017 at 06:52, Kever Yang kever.yang@rock-chips.com wrote:
Embeded the shift in mask MACRO definition in cru header file and clock driver.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Changes in v2:
- split into two patches
arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 70 +++++++++++----------- drivers/clk/rockchip/clk_rk3036.c | 79 +++++++++++-------------- 2 files changed, 69 insertions(+), 80 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On 15 May 2017 at 06:52, Kever Yang kever.yang@rock-chips.com wrote:
Embeded the shift in mask MACRO definition in cru header file and clock driver.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Changes in v2:
- split into two patches
arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 70 +++++++++++----------- drivers/clk/rockchip/clk_rk3036.c | 79 +++++++++++-------------- 2 files changed, 69 insertions(+), 80 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
participants (3)
-
Kever Yang -
Simon Glass -
sjg＠google.com