[U-Boot] [PATCH 0/2] board: k2g: Enable ECC support
This series enables ECC support on k2g-evm.
Lokesh Vutla (2): board: ks2: Enable ECC using detected DDR size board: k2g: Enable ECC byte lane
arch/arm/mach-keystone/ddr3.c | 3 +-- board/ti/ks2_evm/board.c | 3 +++ 2 files changed, 4 insertions(+), 2 deletions(-)
EEC is being enabled based on the ddr size populated by SPD data. But not all keystone platforms have SPD data to detect ddr3 size. So, enable ECC using the detected DDR size.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/ks2_evm/board.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 1de7df0..03254e1 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -50,6 +50,9 @@ int dram_init(void)
if (ddr3_size) ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); + else + ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, gd->ram_size >> 30); + return 0; }
On Sat, Aug 27, 2016 at 05:19:15PM +0530, Lokesh Vutla wrote:
EEC is being enabled based on the ddr size populated by SPD data. But not all keystone platforms have SPD data to detect ddr3 size. So, enable ECC using the detected DDR size.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Sat, Aug 27, 2016 at 05:19:15PM +0530, Lokesh Vutla wrote:
EEC is being enabled based on the ddr size populated by SPD data. But not all keystone platforms have SPD data to detect ddr3 size. So, enable ECC using the detected DDR size.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Enable ECC byte lane for k2g-evm
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-keystone/ddr3.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 34606f4..6b92530 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -65,9 +65,8 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) ;
- /* Disable ECC for K2G */ if (cpu_is_k2g()) { - clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1); + setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1); clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1); clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1); clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
On Sat, Aug 27, 2016 at 05:19:16PM +0530, Lokesh Vutla wrote:
Enable ECC byte lane for k2g-evm
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Sat, Aug 27, 2016 at 05:19:16PM +0530, Lokesh Vutla wrote:
Enable ECC byte lane for k2g-evm
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
participants (2)
-
Lokesh Vutla -
Tom Rini