--- arch/i386/include/asm/global_data.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/i386/include/asm/global_data.h b/arch/i386/include/asm/global_data.h index e3f8a25..e9000c3 100644 --- a/arch/i386/include/asm/global_data.h +++ b/arch/i386/include/asm/global_data.h @@ -35,7 +35,7 @@

#ifndef __ASSEMBLY__

-typedef struct { +typedef struct global_data { bd_t *bd; unsigned long flags; unsigned long baudrate; -- 1.7.1.422.g049e9

--- arch/i386/config.mk | 10 ++++++---- arch/i386/cpu/config.mk | 3 ++- board/eNET/config.mk | 3 --- 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/i386/config.mk b/arch/i386/config.mk index 8743f1a..21d1a27 100644 --- a/arch/i386/config.mk +++ b/arch/i386/config.mk @@ -21,8 +21,6 @@ # MA 02111-1307 USA #

-CROSS_COMPILE ?= i386-linux- - STANDALONE_LOAD_ADDR = 0x40000

PLATFORM_CPPFLAGS += -fno-strict-aliasing @@ -33,7 +31,11 @@ PLATFORM_CPPFLAGS += $(call cc-option, -ffreestanding) PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder, $(call cc-option, -fno-unit-at-a-time)) PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector) PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2) -PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ +PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm

-LDFLAGS += --cref --gc-sections PLATFORM_RELFLAGS += -ffunction-sections +PLATFORM_RELFLAGS += -fvisibility=hidden + +PLATFORM_LDFLAGS += -pic --emit-relocs -Bsymbolic -Bsymbolic-functions + +LDFLAGS += --cref --gc-sections diff --git a/arch/i386/cpu/config.mk b/arch/i386/cpu/config.mk index 16a160d..99edacf 100644 --- a/arch/i386/cpu/config.mk +++ b/arch/i386/cpu/config.mk @@ -21,6 +21,7 @@ # MA 02111-1307 USA #

-PLATFORM_RELFLAGS += +CROSS_COMPILE ?= i386-linux-

+PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ PLATFORM_CPPFLAGS += -march=i386 -Werror diff --git a/board/eNET/config.mk b/board/eNET/config.mk index c4242ad..02e4147 100644 --- a/board/eNET/config.mk +++ b/board/eNET/config.mk @@ -23,6 +23,3 @@

CONFIG_SYS_TEXT_BASE = 0x06000000 CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing -PLATFORM_RELFLAGS += -fvisibility=hidden -PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm -PLATFORM_LDFLAGS += -pic --emit-relocs -Bsymbolic -Bsymbolic-functions -- 1.7.1.422.g049e9

--- arch/i386/cpu/config.mk | 6 ++++++ arch/i386/cpu/u-boot.lds | 22 +++++++--------------- board/eNET/config.mk | 1 + 3 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/arch/i386/cpu/config.mk b/arch/i386/cpu/config.mk index 99edacf..83ce73c 100644 --- a/arch/i386/cpu/config.mk +++ b/arch/i386/cpu/config.mk @@ -25,3 +25,9 @@ CROSS_COMPILE ?= i386-linux-

PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ PLATFORM_CPPFLAGS += -march=i386 -Werror + +# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! +LDPPFLAGS += -DRESET_SEG_START=0xffff0000 +LDPPFLAGS += -DRESET_SEG_SIZE=0x10000 +LDPPFLAGS += -DRESET_VEC_LOC=0xfff0 +LDPPFLAGS += -DSTART_16=0xf800 diff --git a/arch/i386/cpu/u-boot.lds b/arch/i386/cpu/u-boot.lds index 3eeb2a2..e712d26 100644 --- a/arch/i386/cpu/u-boot.lds +++ b/arch/i386/cpu/u-boot.lds @@ -84,21 +84,13 @@ SECTIONS __bios_start = LOADADDR(.bios); __bios_size = SIZEOF(.bios);

- /* The load addresses below assumes that the flash - * will be mapped so that 0x387f0000 == 0xffff0000 - * at reset time - * - * The fe00 and ff00 offsets of the start32 and start16 - * segments are arbitrary, the just have to be mapped - * at reset and the code have to fit. - * The fff0 offset of resetvec is important, however. + /* + * The following expressions place the 16-bit Real-Mode code and + * Reset Vector at the end of the Flash ROM */ - . = 0xfffffe00; - .start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); } + . = START_16; + .start16 : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); }

- . = 0xf800; - .start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); } - - . = 0xfff0; - .resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); } + . = RESET_VEC_LOC; + .resetvec : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); } } diff --git a/board/eNET/config.mk b/board/eNET/config.mk index 02e4147..4e066b4 100644 --- a/board/eNET/config.mk +++ b/board/eNET/config.mk @@ -23,3 +23,4 @@

CONFIG_SYS_TEXT_BASE = 0x06000000 CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing +LDPPFLAGS += -DFLASH_SIZE=0x40000 -- 1.7.1.422.g049e9

--- arch/i386/config.mk | 1 + arch/i386/cpu/u-boot.lds | 2 +- arch/i386/lib/realmode.c | 7 +++---- 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/i386/config.mk b/arch/i386/config.mk index f4689ec..7d1281b 100644 --- a/arch/i386/config.mk +++ b/arch/i386/config.mk @@ -32,6 +32,7 @@ PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder, $(call cc-option, PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector) PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm +PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0

PLATFORM_RELFLAGS += -ffunction-sections PLATFORM_RELFLAGS += -fvisibility=hidden diff --git a/arch/i386/cpu/u-boot.lds b/arch/i386/cpu/u-boot.lds index e712d26..98a548d 100644 --- a/arch/i386/cpu/u-boot.lds +++ b/arch/i386/cpu/u-boot.lds @@ -73,7 +73,7 @@ SECTIONS /DISCARD/ : { *(.gnu*) }

/* 16bit realmode trampoline code */ - .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) } + .realmode REALMODE_BASE : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) }

__realmode_start = LOADADDR(.realmode); __realmode_size = SIZEOF(.realmode); diff --git a/arch/i386/lib/realmode.c b/arch/i386/lib/realmode.c index 60fe181..3b56170 100644 --- a/arch/i386/lib/realmode.c +++ b/arch/i386/lib/realmode.c @@ -27,7 +27,6 @@ #include <asm/realmode.h>

-#define REALMODE_BASE ((char*)0x7c0) #define REALMODE_MAILBOX ((char*)0xe00)

@@ -41,13 +40,13 @@ int realmode_setup(void) ulong realmode_size = (ulong)&__realmode_size;

/* copy the realmode switch code */ - if (realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) { + if (realmode_size > (REALMODE_MAILBOX-(char*)REALMODE_BASE)) { printf("realmode switch too large (%ld bytes, max is %d)\n", - realmode_size, (REALMODE_MAILBOX-REALMODE_BASE)); + realmode_size, (REALMODE_MAILBOX-(char*)REALMODE_BASE)); return -1; }

- memcpy(REALMODE_BASE, (void*)realmode_start, realmode_size); + memcpy((char*)REALMODE_BASE, (void*)realmode_start, realmode_size); asm("wbinvd\n");

return 0; -- 1.7.1.422.g049e9

--- arch/i386/cpu/cpu.c | 13 +++- arch/i386/cpu/interrupts.c | 3 +- arch/i386/cpu/sc520/sc520.c | 7 ++- arch/i386/cpu/start.S | 3 +- arch/i386/cpu/start16.S | 5 +- arch/i386/include/asm/processor-flags.h | 100 +++++++++++++++++++++++++++++++ 6 files changed, 121 insertions(+), 10 deletions(-) create mode 100644 arch/i386/include/asm/processor-flags.h

diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c index 1dcbb98..e96380a 100644 --- a/arch/i386/cpu/cpu.c +++ b/arch/i386/cpu/cpu.c @@ -36,6 +36,7 @@ #include <common.h> #include <command.h> #include <asm/processor.h> +#include <asm/processor-flags.h> #include <asm/interrupt.h>

/* Constructor for a conventional segment GDT (or LDT) entry */ @@ -88,12 +89,16 @@ static void reload_gdt(void)

int cpu_init_f(void) { + const u32 em_rst = ~X86_CR0_EM; + const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; + /* initialize FPU, reset EM, set MP and NE */ asm ("fninit\n" \ - "movl %cr0, %eax\n" \ - "andl $~0x4, %eax\n" \ - "orl $0x22, %eax\n" \ - "movl %eax, %cr0\n" ); + "movl %%cr0, %%eax\n" \ + "andl %0, %%eax\n" \ + "orl %1, %%eax\n" \ + "movl %%eax, %%cr0\n" \ + : : "i" (em_rst), "i" (mp_ne_set) : "eax");

return 0; } diff --git a/arch/i386/cpu/interrupts.c b/arch/i386/cpu/interrupts.c index 3a83afc..214953b 100644 --- a/arch/i386/cpu/interrupts.c +++ b/arch/i386/cpu/interrupts.c @@ -30,6 +30,7 @@ #include <common.h> #include <asm/interrupt.h> #include <asm/io.h> +#include <asm/processor-flags.h>

#define DECLARE_INTERRUPT(x) \ ".globl irq_"#x"\n" \ @@ -237,7 +238,7 @@ int disable_interrupts(void)

asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );

- return (flags&0x200); /* IE flags is bit 9 */ + return (flags & X86_EFLAGS_IF); /* IE flags is bit 9 */ }

/* IRQ Low-Level Service Routine */ diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 7acd471..056df56 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -26,6 +26,7 @@

#include <common.h> #include <asm/io.h> +#include <asm/processor-flags.h> #include <asm/ic/sc520.h>

DECLARE_GLOBAL_DATA_PTR; @@ -41,6 +42,8 @@ volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;

void init_sc520(void) { + const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD); + /* * Set the UARTxCTL register at it's slower, * baud clock giving us a 1.8432 MHz reference @@ -84,8 +87,8 @@ void init_sc520(void)

/* turn on the cache and disable write through */ asm("movl %%cr0, %%eax\n" - "andl $0x9fffffff, %%eax\n" - "movl %%eax, %%cr0\n" : : : "eax"); + "andl %0, %%eax\n" + "movl %%eax, %%cr0\n" : : "i" (nw_cd_rst): "eax"); }

unsigned long init_sc520_dram(void) diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index ab9338a..460c21b 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -26,6 +26,7 @@ #include <config.h> #include <version.h> #include <asm/global_data.h> +#include <asm/processor-flags.h>

.section .text @@ -46,7 +47,7 @@ _i386boot_start:

/* Turn of cache (this might require a 486-class CPU) */ movl %cr0, %eax - orl $0x60000000, %eax + orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 wbinvd

diff --git a/arch/i386/cpu/start16.S b/arch/i386/cpu/start16.S index 0a5823d..7dc5358 100644 --- a/arch/i386/cpu/start16.S +++ b/arch/i386/cpu/start16.S @@ -23,6 +23,7 @@ */

#include <asm/global_data.h> +#include <asm/processor-flags.h>

#define BOOT_SEG 0xffff0000 /* linear segment of boot code */ #define a32 .byte 0x67; @@ -45,7 +46,7 @@ board_init16_ret:

/* Turn of cache (this might require a 486-class CPU) */ movl %cr0, %eax - orl $0x60000000, %eax + orl $(X86_CR0_NW & X86_CR0_CD), %eax movl %eax, %cr0 wbinvd

@@ -55,7 +56,7 @@ o32 cs lgdt gdt_ptr

/* Now, we enter protected mode */ movl %cr0, %eax - orl $1, %eax + orl $X86_CR0_PE, %eax movl %eax, %cr0

/* Flush the prefetch queue */ diff --git a/arch/i386/include/asm/processor-flags.h b/arch/i386/include/asm/processor-flags.h new file mode 100644 index 0000000..7a3e836 --- /dev/null +++ b/arch/i386/include/asm/processor-flags.h @@ -0,0 +1,100 @@ +#ifndef _ASM_X86_PROCESSOR_FLAGS_H +#define _ASM_X86_PROCESSOR_FLAGS_H +/* Various flags defined: can be included from assembler. */ + +/* + * EFLAGS bits + */ +#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ +#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ +#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ +#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ +#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ +#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ +#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ +#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ +#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ +#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ +#define X86_EFLAGS_NT 0x00004000 /* Nested Task */ +#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ +#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ +#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ +#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ +#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ +#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ + +/* + * Basic CPU control in CR0 + */ +#define X86_CR0_PE 0x00000001 /* Protection Enable */ +#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */ +#define X86_CR0_EM 0x00000004 /* Emulation */ +#define X86_CR0_TS 0x00000008 /* Task Switched */ +#define X86_CR0_ET 0x00000010 /* Extension Type */ +#define X86_CR0_NE 0x00000020 /* Numeric Error */ +#define X86_CR0_WP 0x00010000 /* Write Protect */ +#define X86_CR0_AM 0x00040000 /* Alignment Mask */ +#define X86_CR0_NW 0x20000000 /* Not Write-through */ +#define X86_CR0_CD 0x40000000 /* Cache Disable */ +#define X86_CR0_PG 0x80000000 /* Paging */ + +/* + * Paging options in CR3 + */ +#define X86_CR3_PWT 0x00000008 /* Page Write Through */ +#define X86_CR3_PCD 0x00000010 /* Page Cache Disable */ + +/* + * Intel CPU features in CR4 + */ +#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ +#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ +#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ +#define X86_CR4_DE 0x00000008 /* enable debugging extensions */ +#define X86_CR4_PSE 0x00000010 /* enable page size extensions */ +#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ +#define X86_CR4_MCE 0x00000040 /* Machine check enable */ +#define X86_CR4_PGE 0x00000080 /* enable global pages */ +#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ +#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ +#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ +#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */ +#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ + +/* + * x86-64 Task Priority Register, CR8 + */ +#define X86_CR8_TPR 0x0000000F /* task priority register */ + +/* + * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h> + */ + +/* + * NSC/Cyrix CPU configuration register indexes + */ +#define CX86_PCR0 0x20 +#define CX86_GCR 0xb8 +#define CX86_CCR0 0xc0 +#define CX86_CCR1 0xc1 +#define CX86_CCR2 0xc2 +#define CX86_CCR3 0xc3 +#define CX86_CCR4 0xe8 +#define CX86_CCR5 0xe9 +#define CX86_CCR6 0xea +#define CX86_CCR7 0xeb +#define CX86_PCR1 0xf0 +#define CX86_DIR0 0xfe +#define CX86_DIR1 0xff +#define CX86_ARR_BASE 0xc4 +#define CX86_RCR_BASE 0xdc + +#ifdef __KERNEL__ +#ifdef CONFIG_VM86 +#define X86_VM_MASK X86_EFLAGS_VM +#else +#define X86_VM_MASK 0 /* No VM86 support */ +#endif +#endif + +#endif /* _ASM_X86_PROCESSOR_FLAGS_H */ -- 1.7.1.422.g049e9

--- arch/i386/cpu/cpu.c | 14 ++++++++++++-- arch/i386/cpu/sc520/sc520.c | 9 ++------- arch/i386/include/asm/u-boot-i386.h | 2 ++ board/eNET/eNET.c | 22 ---------------------- 4 files changed, 16 insertions(+), 31 deletions(-)

diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c index e96380a..06b27c8 100644 --- a/arch/i386/cpu/cpu.c +++ b/arch/i386/cpu/cpu.c @@ -87,7 +87,7 @@ static void reload_gdt(void) }

-int cpu_init_f(void) +int x86_cpu_init_f(void) { const u32 em_rst = ~X86_CR0_EM; const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; @@ -102,15 +102,25 @@ int cpu_init_f(void)

return 0; } +int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));

-int cpu_init_r(void) +int x86_cpu_init_r(void) { + const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD); + + /* turn on the cache and disable write through */ + asm("movl %%cr0, %%eax\n" + "andl %0, %%eax\n" + "movl %%eax, %%cr0\n" + "wbinvd\n" : : "i" (nw_cd_rst): "eax"); + reload_gdt();

/* Initialize core interrupt and exception functionality of CPU */ cpu_init_interrupts (); return 0; } +int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));

int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 056df56..8e8986b 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -40,10 +40,8 @@ DECLARE_GLOBAL_DATA_PTR;

volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;

-void init_sc520(void) +int cpu_init_f(void) { - const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD); - /* * Set the UARTxCTL register at it's slower, * baud clock giving us a 1.8432 MHz reference @@ -85,10 +83,7 @@ void init_sc520(void) /* turn on the SDRAM write buffer */ writeb(0x11, &sc520_mmcr->dbctl);

- /* turn on the cache and disable write through */ - asm("movl %%cr0, %%eax\n" - "andl %0, %%eax\n" - "movl %%eax, %%cr0\n" : : "i" (nw_cd_rst): "eax"); + return x86_cpu_init_f(); }

unsigned long init_sc520_dram(void) diff --git a/arch/i386/include/asm/u-boot-i386.h b/arch/i386/include/asm/u-boot-i386.h index ce097a3..80db52f 100644 --- a/arch/i386/include/asm/u-boot-i386.h +++ b/arch/i386/include/asm/u-boot-i386.h @@ -25,7 +25,9 @@ #define _U_BOOT_I386_H_ 1

/* cpu/.../cpu.c */ +int x86_cpu_init_r(void); int cpu_init_r(void); +int x86_cpu_init_f(void); int cpu_init_f(void);

/* cpu/.../timer.c */ diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 7f0e257..30d8750 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -48,33 +48,11 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; static void enet_timer_isr(void); static void enet_toggle_run_led(void);

-void init_sc520_enet (void) -{ - /* Set CPU Speed to 100MHz */ - writeb(0x01, &sc520_mmcr->cpuctl); - - /* wait at least one millisecond */ - asm("movl $0x2000,%%ecx\n" - "0: pushl %%ecx\n" - "popl %%ecx\n" - "loop 0b\n": : : "ecx"); - - /* turn on the SDRAM write buffer */ - writeb(0x11, &sc520_mmcr->dbctl); - - /* turn on the cache and disable write through */ - asm("movl %%cr0, %%eax\n" - "andl $0x9fffffff, %%eax\n" - "movl %%eax, %%cr0\n" : : : "eax"); -} - /* * Miscellaneous platform dependent initializations */ int board_early_init_f(void) { - init_sc520_enet(); - writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */ writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */ writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */ -- 1.7.1.422.g049e9

--- arch/i386/cpu/sc520/sc520.c | 19 ------------------- board/eNET/eNET.c | 9 +++++++++ 2 files changed, 9 insertions(+), 19 deletions(-)

diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index e75825b..c51f11b 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -42,25 +42,6 @@ volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;

int cpu_init_f(void) { - /* - * Set the UARTxCTL register at it's slower, - * baud clock giving us a 1.8432 MHz reference - */ - writeb(0x07, &sc520_mmcr->uart1ctl); - writeb(0x07, &sc520_mmcr->uart2ctl); - - /* first set the timer pin mapping */ - writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */ - - /* enable PCI bus arbiter (concurrent mode) */ - writeb(0x02, &sc520_mmcr->sysarbctl); - - /* enable external grants */ - writeb(0x1f, &sc520_mmcr->sysarbmenb); - - /* enable posted-writes */ - writeb(0x04, &sc520_mmcr->hbctl); - if (CONFIG_SYS_SC520_HIGH_SPEED) { /* set it to 133 MHz and write back */ writeb(0x02, &sc520_mmcr->cpuctl); diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 30d8750..b2f349f 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -94,12 +94,21 @@ int board_early_init_f(void) writew(0x0615, &sc520_mmcr->romcs1ctl); writew(0x0615, &sc520_mmcr->romcs2ctl);

+ /* + * Set the timer pin mapping + * no clock frequency selected, use 1.1892MHz + */ + writeb(0x72, &sc520_mmcr->clksel); + writeb(0x00, &sc520_mmcr->adddecctl); writeb(0x07, &sc520_mmcr->uart1ctl); writeb(0x07, &sc520_mmcr->uart2ctl); writeb(0x06, &sc520_mmcr->sysarbctl); writew(0x0003, &sc520_mmcr->sysarbmenb);

+ /* enable posted-writes */ + writeb(0x04, &sc520_mmcr->hbctl); + return 0; }

-- 1.7.1.422.g049e9

--- board/eNET/config.mk | 1 - 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/board/eNET/config.mk b/board/eNET/config.mk index 4e066b4..8c16ece 100644 --- a/board/eNET/config.mk +++ b/board/eNET/config.mk @@ -22,5 +22,4 @@ #

CONFIG_SYS_TEXT_BASE = 0x06000000 -CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing LDPPFLAGS += -DFLASH_SIZE=0x40000 -- 1.7.1.422.g049e9

The SC520 has an inbuilt MC146818 - Enable it for the eNET board --- drivers/rtc/mc146818.c | 6 ++++++ include/configs/eNET.h | 2 ++ 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index ac4eb6a..155034f 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -31,6 +31,12 @@ #include <command.h> #include <rtc.h>

+#ifdef __I386__ +#include <asm/io.h> +#define in8(p) inb(p) +#define out8(p,v) outb(v,p) +#endif + #if defined(CONFIG_CMD_DATE)

static uchar rtc_read (uchar reg); diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 78cab29..082f681 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -33,6 +33,7 @@ * Stuff still to be dealt with - */ #define CONFIG_RTC_MC146818 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0

/* * High Level Configuration Options @@ -91,6 +92,7 @@ #define CONFIG_CMD_BDI /* bdinfo */ #define CONFIG_CMD_BOOTD /* bootd */ #define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_DATE #define CONFIG_CMD_ECHO /* echo arguments */ #define CONFIG_CMD_FLASH /* flinfo, erase, protect */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ -- 1.7.1.422.g049e9

--- board/eNET/eNET.c | 6 +++--- include/configs/eNET.h | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 3b74ce9..fa10c6e 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -90,9 +90,9 @@ int board_early_init_f(void) writew(0x0000, &sc520_mmcr->wdtmrctl);

/* Chip Select Configuration */ - writew(0x0033, &sc520_mmcr->bootcsctl); - writew(0x0615, &sc520_mmcr->romcs1ctl); - writew(0x0615, &sc520_mmcr->romcs2ctl); + writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl); + writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl); + writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);

/* * Set the timer pin mapping diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 082f681..4e96a3a 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -247,6 +247,42 @@ #define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */ #define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */

+/* + * BOOTCS Control (for AM29LV040B-120JC) + * + * 000 0 00 0 000 11 0 011 }- 0x0033 + * \ / | | | \ / | | \ / + * | | | | | | | | + * | | | | | | | +---- 3 Wait States (First Access) + * | | | | | | +------- Reserved + * | | | | | +--------- 3 Wait States (Subsequent Access) + * | | | | +------------- Reserved + * | | | +---------------- Non-Paged Mode + * | | +------------------ 8 Bit Wide + * | +--------------------- GP Bus + * +------------------------ Reserved + */ +#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033 + +/* + * BOOTCS Control (for E28F128J3A-150 StrataFlash) + * + * 000 0 01 1 000 01 0 101 }- 0x0615 + * \ / | | | \ / | | \ / + * | | | | | | | | + * | | | | | | | +---- 5 Wait States (First Access) + * | | | | | | +------- Reserved + * | | | | | +--------- 1 Wait State (Subsequent Access) + * | | | | +------------- Reserved + * | | | +---------------- Paged Mode + * | | +------------------ 16 Bit Wide + * | +--------------------- GP Bus + * +------------------------ Reserved + */ +#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615 +#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615 + + #ifndef __ASSEMBLER__ extern unsigned long ip;

-- 1.7.1.422.g049e9

--- board/eNET/eNET.c | 64 +++++++++++++++++++++++++++++++++++++---------- include/configs/eNET.h | 31 +++++++++++++++++++++- 2 files changed, 79 insertions(+), 16 deletions(-)

diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index b4ef183..db3be5f 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -47,6 +47,7 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;

static void enet_timer_isr(void); static void enet_toggle_run_led(void); +static void enet_setup_pars(void);

/* * Miscellaneous platform dependent initializations @@ -69,20 +70,7 @@ int board_early_init_f(void) writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */ writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */

- writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[2]); - writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[3]); - writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[4]); - writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[5]); - writel(CONFIG_SYS_SC520_SDRAM_PAR, &sc520_mmcr->par[6]); - writel(CONFIG_SYS_SC520_STRATA_FLASH1_PAR, &sc520_mmcr->par[7]); - writel(CONFIG_SYS_SC520_STRATA_FLASH2_PAR, &sc520_mmcr->par[8]); - writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[9]); - writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[10]); - writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[11]); - writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[12]); - writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[13]); -/* writel(CONFIG_SYS_SC520_BOOTCS_PAR, &sc520_mmcr->par14); */ -/* writel(CONFIG_SYS_SC520_LLIO_PAR, &sc520_mmcr->par15); */ + enet_setup_pars();

/* Disable Watchdog */ writew(0x3333, &sc520_mmcr->wdtmrctl); @@ -112,6 +100,54 @@ int board_early_init_f(void) return 0; }

+static void enet_setup_pars(void) +{ + /* + * PARs 11 and 12 are 2MB SRAM @ 0x19000000 + * + * These are setup now because older version of U-Boot have them + * mapped to a different PAR which gets clobbered which prevents + * using SRAM for warm-booting a new image + */ + writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]); + writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]); + + /* PARs 0 and 1 are Compact Flash slots (4kB each) */ + writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]); + writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]); + + /* PAR 2 is used for Cache-As-RAM */ + + /* PARs 3 and 4 are SDRAM */ + writel(SC520_SDRAM1_PAR, &sc520_mmcr->par[3]); + writel(SC520_SDRAM2_PAR, &sc520_mmcr->par[4]); + + /* + * PARs 5 through 8 are additional NS16550 UARTS + * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8 + */ + writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]); + writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]); + writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]); + writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]); + + /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */ + writel(CONFIG_SYS_SC520_STRATA_FLASH1_PAR, &sc520_mmcr->par[9]); + writel(CONFIG_SYS_SC520_STRATA_FLASH2_PAR, &sc520_mmcr->par[10]); + + /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */ + writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]); + + /* + * PAR 14 is Low Level I/O (LEDs, Hex Switches etc) + * Already configured in board_init16 (eNET_start16.S) + * + * PAR 15 is Boot ROM + * Already configured in board_init16 (eNET_start16.S) + */ +} + + int board_early_init_r(void) { /* CPU Speed to 100MHz */ diff --git a/include/configs/eNET.h b/include/configs/eNET.h index de73434..9ad10de 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -341,8 +341,35 @@ /* Dual-Port RAM - 4kB @ 0x18100000 on GPCS4 */ #define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100

-/* SDRAM - 128MB @ 0x00000000 */ -#define CONFIG_SYS_SC520_SDRAM_PAR 0xe3ffc000 +/* + * First 128MB of SDRAM RAM + * + * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000 + * \ / | | | | ----+----/ -----+------/ + * | | | | | | +---------- Start at 0x00000000 + * | | | | | +----------------------- 128MB Region Size ((2047 + 1) * 64kB) + * | | | | +------------------------------ 64kB Page Size + * | | | +-------------------------------- Writes Enabled + * | | +---------------------------------- Caching Enabled + * | +------------------------------------ Execution Enabled + * +--------------------------------------- SDRAM + */ +#define SC520_SDRAM1_PAR 0xe3ffc000 + +/* + * Second 128MB of SDRAM RAM + * + * 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800 + * \ / | | | | ----+----/ -----+------/ + * | | | | | | +---------- Start at 0x08000000 + * | | | | | +----------------------- 128MB Region Size ((2047 + 1) * 64kB) + * | | | | +------------------------------ 64kB Page Size + * | | | +-------------------------------- Writes Enabled + * | | +---------------------------------- Caching Disabled + * | +------------------------------------ Execution Disabled + * +--------------------------------------- SDRAM + */ +#define SC520_SDRAM2_PAR 0xe3ffc800

#ifndef __ASSEMBLER__ extern unsigned long ip; -- 1.7.1.422.g049e9

--- arch/i386/cpu/start.S | 12 +++++----- arch/i386/include/asm/global_data.h | 7 +++++- arch/i386/lib/board.c | 36 +++++++++++++++++++++++----------- include/configs/eNET.h | 1 + 4 files changed, 37 insertions(+), 19 deletions(-)

diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 97bac8f..0ce9713 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -127,13 +127,13 @@ mem_ok: /* Set the upper memory limit parameter */ subl $CONFIG_SYS_STACK_SIZE, %eax

- /* Reserve space for global data */ - subl $(GD_SIZE * 4), %eax + /* Pointer to temporary global data */ + movl $CONFIG_SYS_INIT_GD_ADDR, %edx

- /* %eax points to the global data structure */ - movl %esp, (GD_RAM_SIZE * 4)(%eax) - movl %ebx, (GD_FLAGS * 4)(%eax) - movl %ecx, (GD_LOAD_OFF * 4)(%eax) + /* %edx points to the global data structure */ + movl %esp, (GD_RAM_SIZE * 4)(%edx) + movl %ebx, (GD_FLAGS * 4)(%edx) + movl %ecx, (GD_LOAD_OFF * 4)(%edx)

call board_init_f /* Enter, U-boot! */

diff --git a/arch/i386/include/asm/global_data.h b/arch/i386/include/asm/global_data.h index e9000c3..cd067f5 100644 --- a/arch/i386/include/asm/global_data.h +++ b/arch/i386/include/asm/global_data.h @@ -87,7 +87,12 @@ extern gd_t *gd; #define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */ #define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */

- +#if 0 #define DECLARE_GLOBAL_DATA_PTR +#else +#define XTRN_DECLARE_GLOBAL_DATA_PTR extern +#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \ +gd_t *gd +#endif

#endif /* __ASM_GBL_DATA_H */ diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 2cadce8..460a5e9 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -45,7 +45,15 @@ #include <miiphy.h> #endif

-DECLARE_GLOBAL_DATA_PTR; +/* + * Pointer to initial global data area + * + * Here we initialize it. + */ +#undef XTRN_DECLARE_GLOBAL_DATA_PTR +#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ +DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); +

/* Exports from the Linker Script */ extern ulong __text_start; @@ -168,7 +176,7 @@ gd_t *gd; /* * Load U-Boot into RAM, initialize BSS, perform relocation adjustments */ -void board_init_f (ulong gdp) +void board_init_f (ulong mem_top) { void *text_start = &__text_start; void *data_end = &__data_end; @@ -187,11 +195,11 @@ void board_init_f (ulong gdp) Elf32_Rel *re_end;

/* Calculate destination RAM Address and relocation offset */ - dest_addr = (void *)gdp - (bss_end - text_start); + dest_addr = (void *)mem_top - (bss_end - text_start); rel_offset = text_start - dest_addr;

/* Perform low-level initialization only when cold booted */ - if (((gd_t *)gdp)->flags & GD_FLG_COLD_BOOT) { + if (gd->flags & GD_FLG_COLD_BOOT) { /* First stage CPU initialization */ if (cpu_init_f() != 0) hang(); @@ -203,8 +211,8 @@ void board_init_f (ulong gdp)

/* Copy U-Boot into RAM */ dst_addr = (ulong *)dest_addr; - src_addr = (ulong *)(text_start + ((gd_t *)gdp)->load_off); - end_addr = (ulong *)(data_end + ((gd_t *)gdp)->load_off); + src_addr = (ulong *)(text_start + gd->load_off); + end_addr = (ulong *)(data_end + gd->load_off);

while (src_addr < end_addr) *dst_addr++ = *src_addr++; @@ -217,8 +225,8 @@ void board_init_f (ulong gdp) *dst_addr++ = 0x00000000;

/* Perform relocation adjustments */ - re_src = (Elf32_Rel *)(rel_dyn_start + ((gd_t *)gdp)->load_off); - re_end = (Elf32_Rel *)(rel_dyn_end + ((gd_t *)gdp)->load_off); + re_src = (Elf32_Rel *)(rel_dyn_start + gd->load_off); + re_end = (Elf32_Rel *)(rel_dyn_end + gd->load_off);

do { if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE) @@ -226,11 +234,11 @@ void board_init_f (ulong gdp) *(Elf32_Addr *)(re_src->r_offset - rel_offset) -= rel_offset; } while (re_src++ < re_end);

- ((gd_t *)gdp)->reloc_off = rel_offset; - ((gd_t *)gdp)->flags |= GD_FLG_RELOC; + gd->reloc_off = rel_offset; + gd->flags |= GD_FLG_RELOC;

/* Enter the relocated U-Boot! */ - (board_init_r - rel_offset)((gd_t *)gdp, (ulong)dest_addr); + (board_init_r - rel_offset)(gd, (ulong)dest_addr);

/* NOTREACHED - board_init_f() does not return */ while(1); @@ -242,11 +250,15 @@ void board_init_r(gd_t *id, ulong dest_addr) int i; ulong size; static bd_t bd_data; + static gd_t gd_data; init_fnc_t **init_fnc_ptr;

show_boot_progress(0x21);

- gd = id; + /* Global data pointer is now writable */ + gd = &gd_data; + memcpy(gd, id, sizeof(gd_t)); + /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory");

diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 9ad10de..59f8e6d 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -179,6 +179,7 @@ #define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */ #define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */ #define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */ +#define CONFIG_SYS_INIT_GD_ADDR 0x19040000 /* Address of temporary Global Data */

/* timeout values are in ticks */ #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -- 1.7.1.422.g049e9

--- arch/i386/cpu/sc520/Makefile | 2 +- arch/i386/cpu/sc520/sc520.c | 110 ------- arch/i386/cpu/sc520/sc520_asm.S | 608 ------------------------------------- arch/i386/cpu/sc520/sc520_sdram.c | 522 +++++++++++++++++++++++++++++++ arch/i386/cpu/start.S | 48 +-- arch/i386/include/asm/ic/sc520.h | 36 +++ arch/i386/lib/board.c | 8 +- board/eNET/eNET.c | 6 - board/eNET/eNET_start.S | 10 - board/eNET/eNET_start16.S | 5 - include/configs/eNET.h | 2 +- 11 files changed, 580 insertions(+), 777 deletions(-) delete mode 100644 arch/i386/cpu/sc520/sc520_asm.S create mode 100644 arch/i386/cpu/sc520/sc520_sdram.c

diff --git a/arch/i386/cpu/sc520/Makefile b/arch/i386/cpu/sc520/Makefile index 3c25cba..54260b6 100644 --- a/arch/i386/cpu/sc520/Makefile +++ b/arch/i386/cpu/sc520/Makefile @@ -33,10 +33,10 @@ LIB := $(obj)lib$(SOC).o

COBJS-$(CONFIG_SYS_SC520) += sc520.o COBJS-$(CONFIG_PCI) += sc520_pci.o +COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o

-SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o

SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 956b561..19c7100 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -31,13 +31,6 @@

DECLARE_GLOBAL_DATA_PTR;

-/* - * utility functions for boards based on the AMD sc520 - * - * void init_sc520(void) - * unsigned long init_sc520_dram(void) - */ - volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;

int cpu_init_f(void) @@ -65,109 +58,6 @@ int cpu_init_f(void) return x86_cpu_init_f(); }

-unsigned long init_sc520_dram(void) -{ - bd_t *bd = gd->bd; - - u32 dram_present=0; - u32 dram_ctrl; - -#ifdef CONFIG_SYS_SDRAM_DRCTMCTL - /* these memory control registers are set up in the assember part, - * in sc520_asm.S, during 'mem_init'. If we muck with them here, - * after we are running a stack in RAM, we have troubles. Besides, - * these refresh and delay values are better ? simply specified - * outright in the include/configs/{cfg} file since the HW designer - * simply dictates it. - */ -#else - u8 tmp; - u8 val; - - int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY; - int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE; - int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY; - - /* set SDRAM speed here */ - - refresh_rate /= 78; - if (refresh_rate <= 1) { - val = 0; /* 7.8us */ - } else if (refresh_rate == 2) { - val = 1; /* 15.6us */ - } else if (refresh_rate == 3 || refresh_rate == 4) { - val = 2; /* 31.2us */ - } else { - val = 3; /* 62.4us */ - } - - tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4); - writeb(tmp, &sc520_mmcr->drcctl); - - val = readb(&sc520_mmcr->drctmctl) & 0xf0; - - if (cas_precharge_delay==3) { - val |= 0x04; /* 3T */ - } else if (cas_precharge_delay==4) { - val |= 0x08; /* 4T */ - } else if (cas_precharge_delay>4) { - val |= 0x0c; - } - - if (ras_cas_delay > 3) { - val |= 2; - } else { - val |= 1; - } - writeb(val, &c520_mmcr->drctmctl); -#endif - - /* - * We read-back the configuration of the dram - * controller that the assembly code wrote - */ - dram_ctrl = readl(&sc520_mmcr->drcbendadr); - - bd->bi_dram[0].start = 0; - if (dram_ctrl & 0x80) { - /* bank 0 enabled */ - dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22; - bd->bi_dram[0].size = bd->bi_dram[1].start; - } else { - bd->bi_dram[0].size = 0; - bd->bi_dram[1].start = bd->bi_dram[0].start; - } - - if (dram_ctrl & 0x8000) { - /* bank 1 enabled */ - dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14; - bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start; - } else { - bd->bi_dram[1].size = 0; - bd->bi_dram[2].start = bd->bi_dram[1].start; - } - - if (dram_ctrl & 0x800000) { - /* bank 2 enabled */ - dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6; - bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start; - } else { - bd->bi_dram[2].size = 0; - bd->bi_dram[3].start = bd->bi_dram[2].start; - } - - if (dram_ctrl & 0x80000000) { - /* bank 3 enabled */ - dram_present = (dram_ctrl & 0x7f000000) >> 2; - bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start; - } else { - bd->bi_dram[3].size = 0; - } - gd->ram_size = dram_present; - - return dram_present; -} - #ifdef CONFIG_SYS_SC520_RESET void reset_cpu(ulong addr) { diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S deleted file mode 100644 index 2e85370..0000000 --- a/arch/i386/cpu/sc520/sc520_asm.S +++ /dev/null @@ -1,608 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This file is largely based on code obtned from AMD. AMD's original - * copyright is included below - */ - -/* TITLE SIZER - Aspen DRAM Sizing Routine. - * ============================================================================= - * - * Copyright 1999 Advanced Micro Devices, Inc. - * You may redistribute this program and/or modify this program under the terms - * of the GNU General Public License as published by the Free Software Foundation; - * either version 2 of the License, or (at your option) any later version. - * - * This program is distributed WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED - * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. - * - * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY - * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF - * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE. - * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS - * INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY - * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR - * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE - * LIMITATION MAY NOT APPLY TO YOU. - * - * AMD does not assume any responsibility for any errors that may appear in - * the Materials nor any responsibility to support or update the Materials. - * AMD retains the right to make changes to its test specifications at any - * time, without notice. - * ============================================================================== - */ - -/* - ****************************************************************************** - * - * FILE : sizer.asm - SDRAM DIMM Sizing Algorithm - * - * - * - * FUNCTIONS : sizemem() - jumped to, not called. To be executed after - * reset to determine the size of the SDRAM DIMMs. Initializes - * the memory subsystem. - * - * - * AUTHOR : Buddy Fey - Original. - * - * - * DESCRIPTION : Performs sizing on SDRAM DIMMs on ASPEN processor. - * NOTE: This is a small memory model version - * - * - * INPUTS : BP contains return address offset - * CACHE is assumed to be disabled. - * The FS segment limit has already been set to big real mode - * (full 32-bit addressing capability) - * - * - * OUTPUTS : None - * - * - * REG USE : ax,bx,cx,dx,di,si,bp, fs - * - * - * REVISION : See PVCS info below - * - * - * TEST PLAN CROSS REFERENCE: - * - * - * $Workfile: $ - * $Revision: 1.2 $ - * $Date: 1999/09/22 12:49:33 $ - * $Author: chipf $ - * $Log: sizer.asm $ - * Revision 1.2 1999/09/22 12:49:33 chipf - * Add legal header - * - ******************************************************************************* - */ - - -/******************************************************************************* - * FUNCTIONAL DESCRIPTION: - * This routine is called to autodetect the geometry of the DRAM. - * - * This routine is called to determine the number of column bits for the DRAM - * devices in this external bank. This routine assumes that the external bank - * has been configured for an 11-bit column and for 4 internal banks. This gives - * us the maximum address reach in memory. By writing a test value to the max - * address and locating where it aliases to, we can determine the number of valid - * column bits. - * - * This routine is called to determine the number of internal banks each DRAM - * device has. The external bank (under test) is configured for maximum reach - * with 11-bit columns and 4 internal banks. This routine will write to a max - * address (BA1 and BA0 = 1) and then read from an address with BA1=0 to see if - * that column is a "don't care". If BA1 does not affect write/read of data, - * then this device has only 2 internal banks. - * - * This routine is called to determine the ending address for this external - * bank of SDRAM. We write to a max address with a data value and then disable - * row address bits looking for "don't care" locations. Each "don't care" bit - * represents a dividing of the maximum density (128M) by 2. By dividing the - * maximum of 32 4M chunks in an external bank down by all the "don't care" bits - * determined during sizing, we set the proper density. - * - * WARNINGS. - * bp must be preserved because it is used for return linkage. - * - * EXIT - * nothing returned - but the memory subsystem is enabled - ******************************************************************************* - */ - -#include <config.h> -#include <asm/ic/sc520.h> - -.section .text -.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */ -.equ COL11_ADR, 0x0e001e00 /* 11 col addrs */ -.equ COL10_ADR, 0x0e000e00 /* 10 col addrs */ -.equ COL09_ADR, 0x0e000600 /* 9 col addrs */ -.equ COL08_ADR, 0x0e000200 /* 8 col addrs */ -.equ ROW14_ADR, 0x0f000000 /* 14 row addrs */ -.equ ROW13_ADR, 0x07000000 /* 13 row addrs */ -.equ ROW12_ADR, 0x03000000 /* 12 row addrs */ -.equ ROW11_ADR, 0x01000000 /* 11 row addrs/also bank switch */ -.equ ROW10_ADR, 0x00000000 /* 10 row addrs/also bank switch */ -.equ COL11_DATA, 0x0b0b0b0b /* 11 col addrs */ -.equ COL10_DATA, 0x0a0a0a0a /* 10 col data */ -.equ COL09_DATA, 0x09090909 /* 9 col data */ -.equ COL08_DATA, 0x08080808 /* 8 col data */ -.equ ROW14_DATA, 0x3f3f3f3f /* 14 row data (MASK) */ -.equ ROW13_DATA, 0x1f1f1f1f /* 13 row data (MASK) */ -.equ ROW12_DATA, 0x0f0f0f0f /* 12 row data (MASK) */ -.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */ -.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */ - -.globl mem_init -mem_init: - /* Preserve Boot Flags */ - movl %ebx, %ebp - - /* initialize dram controller registers */ - xorw %ax, %ax - movl $SC520_DBCTL, %edi - movb %al, (%edi) /* disable write buffer */ - - movl $SC520_ECCCTL, %edi - movb %al, (%edi) /* disable ECC */ - - movl $SC520_DRCTMCTL, %edi - movb $0x1e, %al /* Set SDRAM timing for slowest */ - movb %al, (%edi) - - /* setup loop to do 4 external banks starting with bank 3 */ - movl $0xff000000, %eax /* enable last bank and setup */ - movl $SC520_DRCBENDADR, %edi /* ending address register */ - movl %eax, (%edi) - - movl $SC520_DRCCFG, %edi /* setup */ - movw $0xbbbb, %ax /* dram config register for */ - movw %ax, (%edi) - - /* issue a NOP to all DRAMs */ - movl $SC520_DRCCTL, %edi /* setup DRAM control register with */ - movb $0x01, %al /* Disable refresh,disable write buffer */ - movb %al, (%edi) - movl $CACHELINESZ, %esi /* just a dummy address to write for */ - movw %ax, (%esi) - - /* delay for 100 usec? */ - movw $100, %cx -sizdelay: - loop sizdelay - - /* issue all banks precharge */ - movb $0x02, %al - movb %al, (%edi) - movw %ax, (%esi) - - /* issue 2 auto refreshes to all banks */ - movb $0x04, %al /* Auto refresh cmd */ - movb %al, (%edi) - movw $0x02, %cx -refresh1: - movw %ax, (%esi) - loop refresh1 - - /* issue LOAD MODE REGISTER command */ - movb $0x03, %al /* Load mode register cmd */ - movb %al, (%edi) - movw %ax, (%esi) - - /* issue 8 more auto refreshes to all banks */ - movb $0x04, %al /* Auto refresh cmd */ - movb %al, (%edi) - movw $0x0008, %cx -refresh2: - movw %ax, (%esi) - loop refresh2 - - /* set control register to NORMAL mode */ - movb $0x00, %al /* Normal mode value */ - movb %al, (%edi) - - /* - * size dram starting with external bank 3 - * moving to external bank 0 - */ - movl $0x3, %ecx /* start with external bank 3 */ - -nextbank: - - /* write col 11 wrap adr */ - movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ - movl $COL11_DATA, %eax /* pattern for max supported columns(11) */ - movl %eax, (%esi) /* write max col pattern at max col adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write col 10 wrap adr */ - movl $COL10_ADR, %esi /* set address to 10 col wrap address */ - movl $COL10_DATA, %eax /* pattern for 10 col wrap */ - movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write col 9 wrap adr */ - movl $COL09_ADR, %esi /* set address to 9 col wrap address */ - movl $COL09_DATA, %eax /* pattern for 9 col wrap */ - movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write col 8 wrap adr */ - movl $COL08_ADR, %esi /* set address to min(8) col wrap address */ - movl $COL08_DATA, %eax /* pattern for min (8) col wrap */ - movl %eax, (%esi) /* write min col pattern @ min col adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write row 14 wrap adr */ - movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */ - movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */ - movl %eax, (%esi) /* write max row pattern at max row adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write row 13 wrap adr */ - movl $ROW13_ADR, %esi /* set address to 13 row wrap address */ - movl $ROW13_DATA, %eax /* pattern for 13 row wrap */ - movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write row 12 wrap adr */ - movl $ROW12_ADR, %esi /* set address to 12 row wrap address */ - movl $ROW12_DATA, %eax /* pattern for 12 row wrap */ - movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write row 11 wrap adr */ - movl $ROW11_ADR, %edi /* set address to 11 row wrap address */ - movl $ROW11_DATA, %eax /* pattern for 11 row wrap */ - movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */ - movl (%edi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* - * write row 10 wrap adr --- this write is really to determine - * number of banks - */ - movl $ROW10_ADR, %edi /* set address to 10 row wrap address */ - movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */ - movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */ - movl (%edi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* - * read data @ row 12 wrap adr to determine * banks, - * and read data @ row 14 wrap adr to determine * rows. - * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM. - * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4 - * if data @ row 12 wrap == 11 or 12, we have 4 banks, - */ - xorw %di, %di /* value for 2 banks in DI */ - movl (%esi), %ebx /* read from 12 row wrap to check banks */ - /* (esi is setup from the write to row 12 wrap) */ - cmpl %ebx, %eax /* check for AA pattern (eax holds the aa pattern) */ - jz only2 /* if pattern == AA, we only have 2 banks */ - - /* 4 banks */ - - movw $0x008, %di /* value for 4 banks in DI (BNK_CNT bit) */ - cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */ - jz only2 - cmpl $ROW12_DATA, %ebx /* and 12 */ - jnz bad_ram /* its bad if not 11 or 12! */ - - /* fall through */ -only2: - /* - * validate row mask - */ - movl $ROW14_ADR, %esi /* set address back to max row wrap addr */ - movl (%esi), %eax /* read actual number of rows @ row14 adr */ - - cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */ - jb bad_ram - - cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */ - ja bad_ram - - cmpb %ah, %al /* verify all 4 bytes of dword same */ - jnz bad_ram - movl %eax, %ebx - shrl $16, %ebx - cmpw %bx, %ax - jnz bad_ram - - /* - * read col 11 wrap adr for real column data value - */ - movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ - movl (%esi), %eax /* read real col number at max col adr */ - - /* - * validate column data - */ - cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */ - jb bad_ram - - cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */ - ja bad_ram - - subl $COL08_DATA, %eax /* normalize column data to zero */ - jc bad_ram - cmpb %ah, %al /* verify all 4 bytes of dword equal */ - jnz bad_ram - movl %eax, %edx - shrl $16, %edx - cmpw %dx, %ax - jnz bad_ram - - /* - * merge bank and col data together - */ - addw %di, %dx /* merge of bank and col info in dl */ - - /* - * fix ending addr mask based upon col info - */ - movb $0x03, %al - subb %dh, %al /* dh contains the overflow from the bank/col merge */ - movb %bl, %dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */ - xchgw %cx, %ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */ - shrb %cl, %dh - incb %dh /* ending addr is 1 greater than real end */ - xchgw %cx, %ax /* cx is bank number again */ - -bad_reint: - /* - * issue all banks precharge - */ - movl $SC520_DRCCTL, %esi /* setup DRAM control register with */ - movb $0x02, %al /* All banks precharge */ - movb %al, (%esi) - movl $CACHELINESZ, %esi /* address to init read buffer */ - movw %ax, (%esi) - - /* - * update ENDING ADDRESS REGISTER - */ - movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */ - movl %ecx, %ebx - addl %ebx, %edi - movb %dh, (%edi) - - /* - * update CONFIG REGISTER - */ - xorb %dh, %dh - movw $0x000f, %bx - movw %cx, %ax - shlw $2, %ax - xchgw %cx, %ax - shlw %cl, %dx - shlw %cl, %bx - notw %bx - xchgw %cx, %ax - movl $SC520_DRCCFG, %edi - movw (%edi), %ax - andw %bx, %ax - orw %dx, %ax - movw %ax, (%edi) - jcxz cleanup - - decw %cx - movl %ecx, %ebx - movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */ - movb $0xff, %al - addl %ebx, %edi - movb %al, (%edi) - - /* - * set control register to NORMAL mode - */ - movl $SC520_DRCCTL, %esi /* setup DRAM control register with */ - movb $0x00, %al /* Normal mode value */ - movb %al, (%esi) - movl $CACHELINESZ, %esi /* address to init read buffer */ - movw %ax, (%esi) - jmp nextbank - -cleanup: - movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */ - movw $0x04, %cx - xorw %ax, %ax -cleanuplp: - movb (%edi), %al - orb %al, %al - jz emptybank - - addb %ah, %al - jns nottoomuch - - movb $0x7f, %al -nottoomuch: - movb %al, %ah - orb $0x80, %al - movb %al, (%edi) -emptybank: - incl %edi - loop cleanuplp - -#if defined CONFIG_SYS_SDRAM_DRCTMCTL - /* just have your hardware desinger _GIVE_ you what you need here! */ - movl $SC520_DRCTMCTL, %edi - movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al - movb %al, (%edi) -#else -#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T) - /* - * Set the CAS latency now since it is hard to do - * when we run from the RAM - */ - movl $SC520_DRCTMCTL, %edi /* DRAM timing register */ - movb (%edi), %al -#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T - andb $0xef, %al -#endif -#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T - orb $0x10, %al -#endif - movb %al, (%edi) -#endif -#endif - movl $SC520_DRCCTL, %edi /* DRAM Control register */ - movb $0x03, %al /* Load mode register cmd */ - movb %al, (%edi) - movw %ax, (%esi) - - - movl $SC520_DRCCTL, %edi /* DRAM Control register */ - movb $0x18, %al /* Enable refresh and NORMAL mode */ - movb %al, (%edi) - - jmp dram_done - -bad_ram: - xorl %edx, %edx - xorl %edi, %edi - jmp bad_reint - -dram_done: - /* Restore Boot Flags */ - movl %ebx, %ebp - ret - -#if CONFIG_SYS_SDRAM_ECC_ENABLE -.globl init_ecc -init_ecc: - /* A nominal memory test: just a byte at each address line */ - movl %eax, %ecx - shrl $0x1, %ecx - movl $0x1, %edi -memtest0: - movb $0xa5, (%edi) - cmpb $0xa5, (%edi) - jne out - shrl $0x1, %ecx - andl %ecx, %ecx - jz set_ecc - shll $0x1, %edi - jmp memtest0 - -set_ecc: - /* clear all ram with a memset */ - movl %eax, %ecx - xorl %esi, %esi - xorl %edi, %edi - xorl %eax, %eax - shrl $0x2, %ecx - cld - rep stosl - - /* enable read, write buffers */ - movb $0x11, %al - movl $SC520_DBCTL, %edi - movb %al, (%edi) - - /* enable NMI mapping for ECC */ - movl $SC520_ECCINT, %edi - movb $0x10, %al - movb %al, (%edi) - - /* Turn on ECC */ - movl $SC520_ECCCTL, %edi - movb $0x05, %al - movb %al,(%edi) - -out: - ret -#endif - -/* - * Read and decode the sc520 DRCBENDADR MMCR and return the number of - * available ram bytes in %eax - */ -.globl get_mem_size -get_mem_size: - movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */ - -bank0: movl (%edi), %eax - movl %eax, %ecx - andl $0x00000080, %ecx - jz bank1 - andl $0x0000007f, %eax - shll $22, %eax - movl %eax, %edx - -bank1: movl (%edi), %eax - movl %eax, %ecx - andl $0x00008000, %ecx - jz bank2 - andl $0x00007f00, %eax - shll $14, %eax - movl %eax, %edx - -bank2: movl (%edi), %eax - movl %eax, %ecx - andl $0x00800000, %ecx - jz bank3 - andl $0x007f0000, %eax - shll $6, %eax - movl %eax, %edx - -bank3: movl (%edi), %eax - movl %eax, %ecx - andl $0x80000000, %ecx - jz done - andl $0x7f000000, %eax - shrl $2, %eax - movl %eax, %edx - -done: - movl %edx, %eax - ret diff --git a/arch/i386/cpu/sc520/sc520_sdram.c b/arch/i386/cpu/sc520/sc520_sdram.c new file mode 100644 index 0000000..74f8233 --- /dev/null +++ b/arch/i386/cpu/sc520/sc520_sdram.c @@ -0,0 +1,522 @@ +/* + * (C) Copyright 2010 + * Graeme Russ graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor-flags.h> +#include <asm/ic/sc520.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct sc520_sdram_info { + u8 banks; + u8 columns; + u8 rows; + u8 size; +}; + +static void sc520_sizemem(void); +static void sc520_set_dram_timing(void); +static void sc520_set_dram_refresh_rate(void); +static void sc520_enable_dram_refresh(void); +static void sc520_enable_sdram(void); +#if CONFIG_SYS_SDRAM_ECC_ENABLE +static void sc520_enable_ecc(void) +#endif + +int dram_init_f(void) +{ + sc520_sizemem(); + sc520_set_dram_timing(); + sc520_set_dram_refresh_rate(); + sc520_enable_dram_refresh(); + sc520_enable_sdram(); +#if CONFIG_SYS_SDRAM_ECC_ENABLE + sc520_enable_ecc(); +#endif + + return 0; +} + +static inline void sc520_dummy_write(void) +{ + writew(0x0000, CACHELINESZ); +} +static inline void sc520_issue_sdram_op_mode_select(u8 command) +{ + writeb(command, &sc520_mmcr->drcctl); + sc520_dummy_write(); +} + +static inline int check_long(u32 test_long) +{ + u8 i; + u8 tmp_byte = (u8)(test_long & 0x000000ff); + + for (i=1; i<4; i++) { + if ((u8)((test_long >> (i * 8)) & 0x000000ff) != tmp_byte) + return -1; + } + + return 0; +} + +static inline int write_and_test(u32 data, u32 address) +{ + writel(data, address); + if (readl(address) == data) + return 0; /* Good */ + else + return -1; /* Bad */ +} + +static void sc520_enable_sdram(void) +{ + u32 par_config; + + /* Enable Writes, Caching and Code Execution to SDRAM */ + par_config = readl(&sc520_mmcr->par[3]); + par_config &= ~(SC520_PAR_EXEC_DIS | + SC520_PAR_CACHE_DIS | + SC520_PAR_WRITE_DIS); + writel(par_config, &sc520_mmcr->par[3]); + + par_config = readl(&sc520_mmcr->par[4]); + par_config &= ~(SC520_PAR_EXEC_DIS | + SC520_PAR_CACHE_DIS | + SC520_PAR_WRITE_DIS); + writel(par_config, &sc520_mmcr->par[4]); +} + +static void sc520_set_dram_timing(void) +{ + u8 drctmctl = 0x00; + +#if defined CONFIG_SYS_SDRAM_DRCTMCTL + /* just have your hardware designer _GIVE_ you what you need here! */ + drctmctl = CONFIG_SYS_SDRAM_DRCTMCTL; +#else + switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY) { + case 2: + break; + case 3: + drctmctl |= 0x01; + break; + case 4: + default: + drctmctl |= 0x02; + break; + } + + switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY) { + case 2: + break; + case 3: + drctmctl |= 0x04; + break; + case 4: + default: + drctmctl |= 0x08; + break; + + case 6: + drctmctl |= 0x0c; + break; + } + + switch (CONFIG_SYS_SDRAM_CAS_LATENCY) { + case 2: + break; + case 3: + default: + drctmctl |= 0x10; + break; + } +#endif + writeb(drctmctl, &sc520_mmcr->drctmctl); + + /* Issue load mode register command */ + sc520_issue_sdram_op_mode_select(0x03); +} + +static void sc520_set_dram_refresh_rate(void) +{ + u8 drctl; + + drctl = readb(&sc520_mmcr->drcctl); + drctl &= 0xcf; + + switch (CONFIG_SYS_SDRAM_REFRESH_RATE) { + case 78: + break; + case 156: + default: + drctl |= 0x10; + break; + case 312: + drctl |= 0x20; + break; + case 624: + drctl |= 0x30; + break; + } + + writeb(drctl, &sc520_mmcr->drcctl); +} + +static void sc520_enable_dram_refresh(void) +{ + u8 drctl; + + drctl = readb(&sc520_mmcr->drcctl); + drctl &= 0x30; /* keep refresh rate */ + drctl |= 0x08; /* enable refresh, normal mode */ + + writeb(drctl, &sc520_mmcr->drcctl); +} + +static void sc520_get_bank_info(int bank, struct sc520_sdram_info *bank_info) +{ + u32 col_data; + u32 row_data; + + u32 drcbendadr; + u16 drccfg; + + u8 banks = 0x00; + u8 columns = 0x00; + u8 rows = 0x00; + + bank_info->banks = 0x00; + bank_info->columns = 0x00; + bank_info->rows = 0x00; + bank_info->size = 0x00; + + if ((bank < 0) || (bank >3)) { + printf("Bad Bank ID\n"); + return; + } + + /* Save configuration */ + drcbendadr = readl(&sc520_mmcr->drcbendadr); + drccfg = readw(&sc520_mmcr->drccfg); + + /* Setup SDRAM Bank to largest possible size */ + writew(0x000b << (bank * 4), &sc520_mmcr->drccfg); + + /* Set ending address for this bank */ + writel(0x000000ff << (bank * 8), &sc520_mmcr->drcbendadr); + + /* write col 11 wrap adr */ + if (write_and_test(COL11_DATA, COL11_ADR) != 0) + goto restore_and_exit; + + /* write col 10 wrap adr */ + if (write_and_test(COL10_DATA, COL10_ADR) != 0) + goto restore_and_exit; + + /* write col 9 wrap adr */ + if (write_and_test(COL09_DATA, COL09_ADR) != 0) + goto restore_and_exit; + + /* write col 8 wrap adr */ + if (write_and_test(COL08_DATA, COL08_ADR) != 0) + goto restore_and_exit; + + col_data = readl(COL11_ADR); + + /* All four bytes in the read long must be the same */ + if (check_long(col_data) < 0) + goto restore_and_exit; + + if ((col_data >= COL08_DATA) && (col_data <= COL11_DATA)) + columns = (u8)(col_data & 0x000000ff); + else + goto restore_and_exit; + + /* write row 14 wrap adr */ + if (write_and_test(ROW14_DATA, ROW14_ADR) != 0) + goto restore_and_exit; + + /* write row 13 wrap adr */ + if (write_and_test(ROW13_DATA, ROW13_ADR) != 0) + goto restore_and_exit; + + /* write row 12 wrap adr */ + if (write_and_test(ROW12_DATA, ROW12_ADR) != 0) + goto restore_and_exit; + + /* write row 11 wrap adr */ + if (write_and_test(ROW11_DATA, ROW11_ADR) != 0) + goto restore_and_exit; + + if (write_and_test(ROW10_DATA, ROW10_ADR) != 0) + goto restore_and_exit; + + /* + * read data @ row 12 wrap adr to determine number of banks, + * and read data @ row 14 wrap adr to determine number of rows. + * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM. + * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4 + * if data @ row 12 wrap == 11 or 12, we have 4 banks, + */ + row_data = readl(ROW12_ADR); + + /* All four bytes in the read long must be the same */ + if (check_long(row_data) != 0) + goto restore_and_exit; + + switch (row_data) { + case ROW10_DATA: + banks = 2; + break; + + case ROW11_DATA: + case ROW12_DATA: + banks = 4; + break; + + default: + goto restore_and_exit; + } + + row_data = readl(ROW14_ADR); + + /* All four bytes in the read long must be the same */ + if (check_long(row_data) != 0) + goto restore_and_exit; + + switch (row_data) { + case ROW11_DATA: + case ROW12_DATA: + case ROW13_DATA: + case ROW14_DATA: + rows = (u8)(row_data & 0x000000ff); + break; + + default: + goto restore_and_exit; + } + + bank_info->banks = banks; + bank_info->columns = columns; + bank_info->rows = rows; + + if ((bank_info->banks != 0) && + (bank_info->columns != 0) && + (bank_info->rows != 0)) { + bank_info->size = bank_info->rows; + bank_info->size >>= (11 - bank_info->columns); + bank_info->size++; + } + +restore_and_exit: + /* Restore configuration */ + writel(drcbendadr, &sc520_mmcr->drcbendadr); + writew(drccfg, &sc520_mmcr->drccfg); +} + +static void sc520_setup_sizemem(void) +{ + u8 i; + + /* Setup PARs for 256MB of non-cached SDRAM */ + writel(SC520_SDRAM1_PAR, &sc520_mmcr->par[3]); + writel(SC520_SDRAM2_PAR, &sc520_mmcr->par[4]); + + /* Disable write buffer */ + writeb(0x00, &sc520_mmcr->dbctl); + + /* Disable ECC */ + writeb(0x00, &sc520_mmcr->eccctl); + + /* Set slowest SDRAM timing */ + writeb(0x1e, &sc520_mmcr->drctmctl); + + /* Issue a NOP to all SDRAM banks */ + sc520_issue_sdram_op_mode_select(0x01); + + /* Delay for 100 microseconds */ + udelay(100); + + /* Issue 'All Banks Precharge' command */ + sc520_issue_sdram_op_mode_select(0x02); + + /* Issue 2 'Auto Refresh Enable' command */ + sc520_issue_sdram_op_mode_select(0x04); + sc520_dummy_write(); + + /* Issue 'Load Mode Register' command */ + sc520_issue_sdram_op_mode_select(0x03); + + /* Issue 8 more 'Auto Refresh Enable' commands */ + sc520_issue_sdram_op_mode_select(0x04); + for (i=0; i<7; i++) + sc520_dummy_write(); + + /* Set control register to 'Normal Mode' */ + writeb(0x00, &sc520_mmcr->drcctl); +} + +static void sc520_sizemem(void) +{ + struct sc520_sdram_info sdram_info[4]; + u8 bank_config = 0x00; + u8 end_addr = 0x00; + u16 drccfg = 0x0000; + u32 drcbendadr = 0x00000000; + u8 i; + + sc520_setup_sizemem(); + + gd->ram_size = 0; + + /* Size each SDRAM bank */ + for (i=0; i<=3; i++) { + sc520_get_bank_info(i, &sdram_info[i]); + + if (sdram_info[i].banks != 0) { + /* Update Configuration register */ + bank_config = sdram_info[i].columns - 8; + + if (sdram_info[i].banks == 4) + bank_config |= 0x08; + + drccfg |= bank_config << (i * 4); + + /* Update End Address register */ + end_addr += sdram_info[i].size; + drcbendadr |= (end_addr | 0x80) << (i * 8); + + gd->ram_size += sdram_info[i].size << 22; + } + + /* Issue 'All Banks Precharge' command */ + sc520_issue_sdram_op_mode_select(0x02); + + /* Set control register to 'Normal Mode' */ + writeb(0x00, &sc520_mmcr->drcctl); + } + + writel(drcbendadr, &sc520_mmcr->drcbendadr); + writew(drccfg, &sc520_mmcr->drccfg); +} + +#if CONFIG_SYS_SDRAM_ECC_ENABLE +static void sc520_enable_ecc(void) + + /* A nominal memory test: just a byte at each address line */ + movl %eax, %ecx + shrl $0x1, %ecx + movl $0x1, %edi +memtest0: + movb $0xa5, (%edi) + cmpb $0xa5, (%edi) + jne out + shrl $0x1, %ecx + andl %ecx, %ecx + jz set_ecc + shll $0x1, %edi + jmp memtest0 + +set_ecc: + /* clear all ram with a memset */ + movl %eax, %ecx + xorl %esi, %esi + xorl %edi, %edi + xorl %eax, %eax + shrl $0x2, %ecx + cld + rep stosl + + /* enable read, write buffers */ + movb $0x11, %al + movl $DBCTL, %edi + movb %al, (%edi) + + /* enable NMI mapping for ECC */ + movl $ECCINT, %edi + movb $0x10, %al + movb %al, (%edi) + + /* Turn on ECC */ + movl $ECCCTL, %edi + movb $0x05, %al + movb %al,(%edi) + +out: + jmp init_ecc_ret +} +#endif + +int dram_init(void) +{ + ulong dram_ctrl; + ulong dram_present = 0x00000000; + + /* + * We read-back the configuration of the dram + * controller that the assembly code wrote + */ + dram_ctrl = readl(&sc520_mmcr->drcbendadr); + + gd->bd->bi_dram[0].start = 0; + if (dram_ctrl & 0x80) { + /* bank 0 enabled */ + dram_present = gd->bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22; + gd->bd->bi_dram[0].size = gd->bd->bi_dram[1].start; + } else { + gd->bd->bi_dram[0].size = 0; + gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start; + } + + if (dram_ctrl & 0x8000) { + /* bank 1 enabled */ + dram_present = gd->bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[2].start - gd->bd->bi_dram[1].start; + } else { + gd->bd->bi_dram[1].size = 0; + gd->bd->bi_dram[2].start = gd->bd->bi_dram[1].start; + } + + if (dram_ctrl & 0x800000) { + /* bank 2 enabled */ + dram_present = gd->bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6; + gd->bd->bi_dram[2].size = gd->bd->bi_dram[3].start - gd->bd->bi_dram[2].start; + } else { + gd->bd->bi_dram[2].size = 0; + gd->bd->bi_dram[3].start = gd->bd->bi_dram[2].start; + } + + if (dram_ctrl & 0x80000000) { + /* bank 3 enabled */ + dram_present = (dram_ctrl & 0x7f000000) >> 2; + gd->bd->bi_dram[3].size = dram_present - gd->bd->bi_dram[3].start; + } else { + gd->bd->bi_dram[3].size = 0; + } + + gd->ram_size = dram_present; + + return 0; +} diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index df9ca0d..95be5a2 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -82,29 +82,22 @@ car_init_ret: * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack */ movl $CONFIG_SYS_INIT_SP_ADDR, %esp + movl $CONFIG_SYS_INIT_GD_ADDR, %ebp

- /* Skip memory initialization if not starting from cold-reset */ - movl %ebx, %ecx - andl $GD_FLG_COLD_BOOT, %ecx - jz skip_mem_init + /* Set Boot Flags in Global Data */ + movl %ebx, (GD_FLAGS * 4)(%ebp)

- /* size memory */ - call mem_init - -skip_mem_init: - /* fetch memory size (into %eax) */ - call get_mem_size - movl %eax, %esp + /* Determine our load offset (and put in Global Data) */ + call 1f +1: popl %ecx + subl $1b, %ecx + movl %ecx, (GD_LOAD_OFF * 4)(%ebp)

-#if CONFIG_SYS_SDRAM_ECC_ENABLE - /* Skip ECC initialization if not starting from cold-reset */ - movl %ebx, %ecx - andl $GD_FLG_COLD_BOOT, %ecx - jz skip_ecc_init - call init_ecc + /* size memory */ + call dram_init_f

-skip_init_ecc: -#endif + /* Setup stack in SDRAM */ + movl (GD_RAM_SIZE * 4)(%ebp), %esp

/* Test the stack */ pushl $0 @@ -118,21 +111,8 @@ skip_init_ecc:

wbinvd

- /* Determine our load offset */ - call 1f -1: popl %ecx - subl $1b, %ecx - - /* Set the upper memory limit parameter */ - subl $CONFIG_SYS_STACK_SIZE, %eax - - /* Pointer to temporary global data */ - movl $CONFIG_SYS_INIT_GD_ADDR, %edx - - /* %edx points to the global data structure */ - movl %esp, (GD_RAM_SIZE * 4)(%edx) - movl %ebx, (GD_FLAGS * 4)(%edx) - movl %ecx, (GD_LOAD_OFF * 4)(%edx) + /* Set parameter to board_init_f() to boot flags */ + movl (GD_FLAGS * 4)(%ebp), %eax

call board_init_f /* Enter, U-boot! */

diff --git a/arch/i386/include/asm/ic/sc520.h b/arch/i386/include/asm/ic/sc520.h index fe217ea..74a544e 100644 --- a/arch/i386/include/asm/ic/sc520.h +++ b/arch/i386/include/asm/ic/sc520.h @@ -285,6 +285,15 @@ extern volatile sc520_mmcr_t *sc520_mmcr; #define SC520_PAR14 (SC520_PAR0 + (0x04 * 14)) #define SC520_PAR15 (SC520_PAR0 + (0x04 * 15))

+#define SC520_PAR_WRITE_DIS 0x04000000 +#define SC520_PAR_CACHE_DIS 0x08000000 +#define SC520_PAR_EXEC_DIS 0x10000000 + +/* + * Programmable Address Regions to cover 256MB SDRAM (Maximum supported) + * required for DRAM sizing code + */ + /* MMCR Register bits (not all of them :) ) */

/* SSI Stuff */ @@ -315,6 +324,33 @@ extern volatile sc520_mmcr_t *sc520_mmcr; #define UART2_DIS 0x02 /* UART2 Disable */ #define UART1_DIS 0x01 /* UART1 Disable */

+/* + * Defines used for SDRAM Sizing (number of columns and rows) + * Refer to section 10.6.4 - SDRAM Sizing Algorithm in the + * Elan SC520 Microcontroller User's Manual (Order #22004B) + */ +#define CACHELINESZ 0x00000010 + +#define COL11_ADR 0x0e001e00 +#define COL10_ADR 0x0e000e00 +#define COL09_ADR 0x0e000600 +#define COL08_ADR 0x0e000200 +#define COL11_DATA 0x0b0b0b0b +#define COL10_DATA 0x0a0a0a0a +#define COL09_DATA 0x09090909 +#define COL08_DATA 0x08080808 + +#define ROW14_ADR 0x0f000000 +#define ROW13_ADR 0x07000000 +#define ROW12_ADR 0x03000000 +#define ROW11_ADR 0x01000000 +#define ROW10_ADR 0x00000000 +#define ROW14_DATA 0x3f3f3f3f +#define ROW13_DATA 0x1f1f1f1f +#define ROW12_DATA 0x0f0f0f0f +#define ROW11_DATA 0x07070707 +#define ROW10_DATA 0xaaaaaaaa + /* 0x28000000 - 0x3fffffff is used by the flash banks */

/* 0x40000000 - 0xffffffff is not adressable by the SC520 */ diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 460a5e9..0dcd828 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -176,7 +176,7 @@ gd_t *gd; /* * Load U-Boot into RAM, initialize BSS, perform relocation adjustments */ -void board_init_f (ulong mem_top) +void board_init_f (ulong boot_flags) { void *text_start = &__text_start; void *data_end = &__data_end; @@ -194,8 +194,12 @@ void board_init_f (ulong mem_top) Elf32_Rel *re_src; Elf32_Rel *re_end;

+ gd->flags = boot_flags; + /* Calculate destination RAM Address and relocation offset */ - dest_addr = (void *)mem_top - (bss_end - text_start); + dest_addr = (void *)gd->ram_size; + dest_addr -= CONFIG_SYS_STACK_SIZE; + dest_addr -= (bss_end - text_start); rel_offset = text_start - dest_addr;

/* Perform low-level initialization only when cold booted */ diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index c585771..ae8ce96 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -157,12 +157,6 @@ int board_early_init_r(void) return 0; }

-int dram_init(void) -{ - init_sc520_dram(); - return 0; -} - void show_boot_progress(int val) { uchar led_mask; diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S index c9e95ee..f920f80 100644 --- a/board/eNET/eNET_start.S +++ b/board/eNET/eNET_start.S @@ -28,16 +28,6 @@ /* board early intialization */ .globl early_board_init early_board_init: - /* Map PAR for first 128MB of RAM */ - movl $SC520_PAR3, %edi - movl $SC520_SDRAM1_PAR, %eax - movl %eax, (%di) - - /* Map PAR for second 128MB of RAM */ - movl $SC520_PAR4, %edi - movl $SC520_SDRAM2_PAR, %eax - movl %eax, (%di) - jmp early_board_init_ret

.globl cpu_halt_asm diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index 6db72ee..b6f2d63 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -56,11 +56,6 @@ board_init16: movl $CONFIG_SYS_SC520_LLIO_PAR, %eax movl %eax, (%di)

- /* Disable SDRAM write buffer */ - movw $(SC520_DBCTL - SC520_MMCR_BASE), %di - xorw %ax, %ax - movb %al, (%di) - /* Disabe MMCR alias */ movw $0xfffc, %dx movl $0x000000cb, %eax diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 4b9d649..36c10a6 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -146,11 +146,11 @@ * SDRAM Configuration */ #define CONFIG_SYS_SDRAM_DRCTMCTL 0x18 +#define CONFIG_SYS_SDRAM_REFRESH_RATE 156 #define CONFIG_NR_DRAM_BANKS 4

/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY -#undef CONFIG_SYS_SDRAM_REFRESH_RATE #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T -- 1.7.1.422.g049e9

--- arch/i386/cpu/start.S | 3 --- arch/i386/lib/board.c | 5 +++++ 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 77f0332..fd018bf 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -93,9 +93,6 @@ car_init_ret: subl $1b, %ecx movl %ecx, (GD_LOAD_OFF * 4)(%ebp)

- /* size memory */ - call dram_init_f - /* Set parameter to board_init_f() to boot flags */ movl (GD_FLAGS * 4)(%ebp), %eax

diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 250bad8..1118322 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -173,6 +173,8 @@ init_fnc_t *init_sequence[] = {

gd_t *gd;

+int dram_init_f(void); + /* * Load U-Boot into RAM, initialize BSS, perform relocation adjustments */ @@ -197,6 +199,9 @@ void board_init_f (ulong boot_flags)

gd->flags = boot_flags;

+ if (dram_init_f() != 0) + hang(); + /* Calculate destination RAM Address and relocation offset */ dest_addr = (void *)gd->ram_size; addr_sp = dest_addr; -- 1.7.1.422.g049e9

--- arch/i386/lib/board.c | 15 ++++++++++++--- 1 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index b04367b..2b06900 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -162,9 +162,6 @@ init_fnc_t *init_sequence[] = { dram_init, /* configure available RAM banks */ interrupt_init, /* set up exceptions */ timer_init, - env_init, /* initialize environment */ - init_baudrate, /* initialze baudrate settings */ - serial_init, /* serial communications setup */ display_banner, display_dram_config,

@@ -199,6 +196,18 @@ void board_init_f (ulong boot_flags)

gd->flags = boot_flags;

+ if (env_init() != 0) + hang(); + + if (init_baudrate() != 0) + hang(); + + if (serial_init() != 0) + hang(); + + if (console_init_f() != 0) + hang(); + if (dram_init_f() != 0) hang();

-- 1.7.1.422.g049e9

--- arch/i386/include/asm/global_data.h | 12 +++- arch/i386/lib/board.c | 111 +++++++++++++++++++++-------------- 2 files changed, 74 insertions(+), 49 deletions(-)

diff --git a/arch/i386/include/asm/global_data.h b/arch/i386/include/asm/global_data.h index cd067f5..f8a16d6 100644 --- a/arch/i386/include/asm/global_data.h +++ b/arch/i386/include/asm/global_data.h @@ -46,6 +46,8 @@ typedef struct global_data { unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; + unsigned long relocaddr; /* Start address of U-Boot in RAM */ + unsigned long start_addr_sp; /* start_addr_stackpointer */ phys_size_t ram_size; /* RAM size */ unsigned long reset_status; /* reset status register at boot */ void **jt; /* jump table */ @@ -67,11 +69,13 @@ extern gd_t *gd; #define GD_ENV_VALID 7 #define GD_CPU_CLK 8 #define GD_BUS_CLK 9 -#define GD_RAM_SIZE 10 -#define GD_RESET_STATUS 11 -#define GD_JT 12 +#define GD_RELOC_ADDR 10 +#define GD_START_ADDR_SP 11 +#define GD_RAM_SIZE 12 +#define GD_RESET_STATUS 13 +#define GD_JT 14

-#define GD_SIZE 13 +#define GD_SIZE 15

/* * Global Data Flags diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index c77c206..abd0551 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -172,30 +172,71 @@ gd_t *gd;

int dram_init_f(void);

-/* - * Load U-Boot into RAM, initialize BSS, perform relocation adjustments - */ -void board_init_f (ulong boot_flags) +static int calculate_relocation_address(void) { void *text_start = &__text_start; - void *data_end = &__data_end; - void *rel_dyn_start = &__rel_dyn_start; - void *rel_dyn_end = &__rel_dyn_end; + void *bss_end = &__bss_end; + void *dest_addr; + ulong rel_offset; + + /* Calculate destination RAM Address and relocation offset */ + dest_addr = (void *)gd->ram_size; + dest_addr -= CONFIG_SYS_STACK_SIZE; + dest_addr -= (bss_end - text_start); + rel_offset = dest_addr - text_start; + + gd->start_addr_sp = gd->ram_size; + gd->relocaddr = (ulong)dest_addr; + gd->reloc_off = rel_offset; + + return 0; +} + +static int copy_uboot_to_ram(void) +{ + ulong *dst_addr = (ulong *)gd->relocaddr; + ulong *src_addr = (ulong *)&__text_start; + ulong *end_addr = (ulong *)&__data_end; + + while (src_addr < end_addr) + *dst_addr++ = *src_addr++; + + return 0; +} + +static int clear_bss(void) +{ void *bss_start = &__bss_start; void *bss_end = &__bss_end;

- ulong *dst_addr; - ulong *src_addr; - ulong *end_addr; + ulong *dst_addr = (ulong *)(bss_start + gd->reloc_off); + ulong *end_addr = (ulong *)(bss_end + gd->reloc_off);;

- void *addr_sp; - void *dest_addr; - ulong rel_offset; - Elf32_Rel *re_src; - Elf32_Rel *re_end; + while (dst_addr < end_addr) + *dst_addr++ = 0x00000000; + + return 0; +}

- gd->flags = boot_flags; +static int do_elf_reloc_fixups(void) +{ + Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start); + Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end);

+ do { + if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE) + if (*(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) >= CONFIG_SYS_TEXT_BASE) + *(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) += gd->reloc_off; + } while (re_src++ < re_end); + + return 0; +} + +/* + * Load U-Boot into RAM, initialize BSS, perform relocation adjustments + */ +void board_init_f (ulong boot_flags) +{ if (env_init() != 0) hang();

@@ -211,12 +252,8 @@ void board_init_f (ulong boot_flags) if (dram_init_f() != 0) hang();

- /* Calculate destination RAM Address and relocation offset */ - dest_addr = (void *)gd->ram_size; - addr_sp = dest_addr; - dest_addr -= CONFIG_SYS_STACK_SIZE; - dest_addr -= (bss_end - text_start); - rel_offset = dest_addr - text_start; + if (calculate_relocation_address() != 0) + hang();

/* First stage CPU initialization */ if (cpu_init_f() != 0) @@ -227,35 +264,19 @@ void board_init_f (ulong boot_flags) hang();

/* Copy U-Boot into RAM */ - dst_addr = (ulong *)dest_addr; - src_addr = (ulong *)(text_start + gd->load_off); - end_addr = (ulong *)(data_end + gd->load_off); - - while (src_addr < end_addr) - *dst_addr++ = *src_addr++; - - /* Clear BSS */ - dst_addr = (ulong *)(bss_start + rel_offset); - end_addr = (ulong *)(bss_end + rel_offset); - - while (dst_addr < end_addr) - *dst_addr++ = 0x00000000; + if (copy_uboot_to_ram() != 0) + hang();

- /* Perform relocation adjustments */ - re_src = (Elf32_Rel *)(rel_dyn_start + gd->load_off); - re_end = (Elf32_Rel *)(rel_dyn_end + gd->load_off); + if (clear_bss() != 0) + hang();

- do { - if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE) - if (*(Elf32_Addr *)(re_src->r_offset + rel_offset) >= CONFIG_SYS_TEXT_BASE) - *(Elf32_Addr *)(re_src->r_offset + rel_offset) += rel_offset; - } while (re_src++ < re_end); + if (do_elf_reloc_fixups() != 0) + hang();

- gd->reloc_off = rel_offset; gd->flags |= GD_FLG_RELOC;

/* Enter the relocated U-Boot! */ - relocate_code((ulong)addr_sp, gd, (ulong)dest_addr); + relocate_code(gd->start_addr_sp, gd, gd->relocaddr);

/* NOTREACHED - relocate_code() does not return */ while(1); -- 1.7.1.422.g049e9

--- arch/i386/lib/board.c | 68 +++++++++++++++++++++--------------------------- 1 files changed, 30 insertions(+), 38 deletions(-)

diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 35d7afd..6888d53 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -156,7 +156,29 @@ static void display_flash_config (ulong size) */ typedef int (init_fnc_t) (void);

-init_fnc_t *init_sequence[] = { +int dram_init_f(void); +static int calculate_relocation_address(void); +static int copy_uboot_to_ram(void); +static int clear_bss(void); +static int do_elf_reloc_fixups(void); + +init_fnc_t *init_sequence_f[] = { + cpu_init_f, + board_early_init_f, + env_init, + init_baudrate, + serial_init, + console_init_f, + dram_init_f, + calculate_relocation_address, + copy_uboot_to_ram, + clear_bss, + do_elf_reloc_fixups, + + NULL, +}; + +init_fnc_t *init_sequence_r[] = { cpu_init_r, /* basic cpu dependent setup */ board_early_init_r, /* basic board dependent setup */ dram_init, /* configure available RAM banks */ @@ -170,8 +192,6 @@ init_fnc_t *init_sequence[] = {

gd_t *gd;

-int dram_init_f(void); - static int calculate_relocation_address(void) { void *text_start = &__text_start; @@ -237,41 +257,13 @@ static int do_elf_reloc_fixups(void) */ void board_init_f (ulong boot_flags) { - /* First stage CPU initialization */ - if (cpu_init_f() != 0) - hang(); - - /* First stage Board initialization */ - if (board_early_init_f() != 0) - hang(); - - if (env_init() != 0) - hang(); - - if (init_baudrate() != 0) - hang(); - - if (serial_init() != 0) - hang(); - - if (console_init_f() != 0) - hang(); - - if (dram_init_f() != 0) - hang(); - - if (calculate_relocation_address() != 0) - hang(); - - /* Copy U-Boot into RAM */ - if (copy_uboot_to_ram() != 0) - hang(); - - if (clear_bss() != 0) - hang(); + init_fnc_t **init_fnc_ptr;

- if (do_elf_reloc_fixups() != 0) - hang(); + for (init_fnc_ptr = init_sequence_f; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr)() != 0) { + hang (); + } + }

gd->flags |= GD_FLG_RELOC;

@@ -309,7 +301,7 @@ void board_init_r(gd_t *id, ulong dest_addr) mem_malloc_init((((ulong)dest_addr - CONFIG_SYS_MALLOC_LEN)+3)&~3, CONFIG_SYS_MALLOC_LEN);

- for (init_fnc_ptr = init_sequence, i=0; *init_fnc_ptr; ++init_fnc_ptr, i++) { + for (init_fnc_ptr = init_sequence_r, i=0; *init_fnc_ptr; ++init_fnc_ptr, i++) { show_boot_progress(0xa130|i);

if ((*init_fnc_ptr)() != 0) { -- 1.7.1.422.g049e9

--- include/configs/eNET.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 36c10a6..faad327 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -182,7 +182,7 @@ #define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */ #define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */ #define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */ -#define CONFIG_SYS_INIT_GD_ADDR 0x19040000 /* Address of temporary Global Data */ +#define CONFIG_SYS_INIT_GD_ADDR CONFIG_SYS_CAR_ADDR /* Address of temporary Global Data */

/* timeout values are in ticks */ #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -- 1.7.1.422.g049e9