[PATCH v2 0/3] arm: dts: k3-j721e: Enable OSPI1/QSPI

The patch series enables he OSPI1 aka QSPI node. This is a precursor for enabling QSPI boot on j721e.
Changes in v2:
* Moved the pin definitions out of u-boot.dtsi to r5 and a72 based dts files.
Keerthy (3): arm: dts: k3-j721e: Enable ospi1/qspi arm: dts: k3-j721e-mcu-wakeup: Add assigned-clocks/rates properties for ospi1/qspi arm: dts: k3-j721e-r5-common-proc-board: Add ospi1 flash node
.../k3-j721e-common-proc-board-u-boot.dtsi | 12 ++++++ arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 2 + .../arm/dts/k3-j721e-r5-common-proc-board.dts | 39 +++++++++++++++++++ 3 files changed, 53 insertions(+)

Enable the ospi1/qspi for both r5 and a72 configurations.
Signed-off-by: Keerthy j-keerthy@ti.com --- Changes in v2:
* Moved the pin definitions out of u-boot.dtsi to r5 and a72 based dts files.
.../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 12 ++++++++++++ arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 14 ++++++++++++++ 2 files changed, 26 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index d422100d42..7b01e4204f 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -365,3 +365,15 @@ u-boot,dm-spl; }; }; + +&ospi1 { + u-boot,dm-spl; + + flash@0 { + u-boot,dm-spl; + }; +}; + +&mcu_fss0_ospi1_pins_default { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index ebea9efa58..44da8eabc2 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -134,6 +134,20 @@ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ >; }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + u-boot,dm-spl; + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ + J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ + J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ + J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ + J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ + J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ + J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ + J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ + >; + }; };
&main_pmx0 {

Add assigned-clocks/rates properties for ospi1/qspi. This is the expected rate as per ROM configuration.
Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index a9e97f219b..2eed50aa5a 100644 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi @@ -170,6 +170,8 @@ cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; clocks = <&k3_clks 104 0>; + assigned-clocks = <&k3_clks 104 0>; + assigned-clock-rates = <133333333>; power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>;

Add ospi1 flash node required for QSPI boot.
Signed-off-by: Keerthy j-keerthy@ti.com --- .../arm/dts/k3-j721e-r5-common-proc-board.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 44da8eabc2..84bfb1025e 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -320,4 +320,29 @@ }; };
+&ospi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + u-boot,dm-spl; + + reg = <0x0 0x47050000 0x0 0x100>, + <0x0 0x58000000 0x0 0x8000000>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-spl; + }; +}; + #include "k3-j721e-common-proc-board-u-boot.dtsi"

On 04/03/20 10:10 am, Lokesh Vutla wrote:
On 04/03/20 10:09 AM, Keerthy wrote:
The patch series enables he OSPI1 aka QSPI node. This is a precursor for enabling QSPI boot on j721e.
How did you test this using R5 defconig?
#define CONFIG_SF_DEFAULT_BUS 1
So as to force SPI boot to OSPI1/QSPI.
Booted using OSPI boot probed sf probe 1:0 & burnt all the boot images on to QSPI.
Then booted from QSPI.
- Keerthy
Thanks and regards, Lokesh

On 04/03/20 10:09 AM, Keerthy wrote:
The patch series enables he OSPI1 aka QSPI node. This is a precursor for enabling QSPI boot on j721e.
Changes in v2:
- Moved the pin definitions out of u-boot.dtsi to r5 and a72 based dts files.
Applied to u-boot-ti next.
Thanks and regards, Lokesh
participants (2)
-
Keerthy
-
Lokesh Vutla